Complete Solution Altera introduces APEXII device family: highper

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Complete Solution Altera introduces APEXII device family: highper

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APEX
Complete Solution
Altera introduces APEXII device family: highperformance, high-bandwidth programmable logic devices (PLDs) targeted towards emerging network communications applications protocols. APEX devices support protocols such UTOPIA RapidIO, CSIX, POS-PHY Level making them ideal solution complex systems. APEX device family features 1-Gbps dedicated True-LVDScircuitry, phase-locked loops (PLLs), embedded system blocks (ESBs), content-addressable memory (CAM), enhanced all-layer-copper interconnects.
Advanced High-Performance LVDS
1-Gbps True-LVDS input 1-Gbps True-LVDS
output channels
624-Mbps Flexible-LVDSinput channels
624-Mbps Flexible-LVDS output channels
LVDS/LVPECL/PCML/HyperTransport support
Supported Protocols
RapidIO POS-PHY Flexbus PCI-X UTOPIA CSIX Zero-bus turnaround (ZBT),
Enhanced Architecture
Kbits memory Dual-port+ ESBs with
bidirectional read/write ports
Eight output taps high-speed registers
element
double-data rate (DDR), quad-data rate (QDR) memory interface support
Complete Solution
high-density Altera® APEX device family offers advanced features support total systemon-a-programmable-chip (SOPC) solution. look-up-table (LUT)based APEX devices based 0.15-/0.13-µm all-layer-copper interconnect technology address increasing performance bandwidth requirements communication applications. These devices offer versatility flexibility high-performance SOPC applications. APEX device densities range from 16,640 logic elements (LEs) 89,280 (1.9 million million maximum system gates). Based state-of-the-art SRAM process technology, APEX device family supports wide range high-speed standards such LVDS, PCML, LVPECL, HyperTransport, HSTL, SSTL, enabling high-speed data transfers. With True-LVDS circuitry, APEX devices achieve data transfer rates Gbps channel, fully 64-bit, 66-MHz PCI-X compliant. APEX devices
feature four general-purpose PLLs that drive eight different global clock nets and/or circuit signals comprehensive clock management synthesis needs. following page, Table describes some highlights APEX devices, Table shows wide range features packages available.
Standard Support High-Bandwidth Applications
APEX devices have dedicated support cutting-edge standards such HSTL, SSTL, LVPECL, PCML, HyperTransport, CTT, GTL+, PCI-X, AGP, LVTTL, LVCMOS, LVDS-with performance Gbps. These standards allow APEX device interface with other on-board devices high-bandwidth applications shown Figure APEX devices also feature MultiVoltI/O interface, allowing them interface with devices using different voltage levels, including Table details support APEX devices offer advanced standard applications.
Figure APEX Interface Support
True-LVDS Solution
Gbps channel LVDS, LVPECL, PCML,
Processor
Host Processor Interface
RapidIO HyperTransport PCI-X
HyperTransport input output channels
Clock-Data Synchronization
Memory Interface
Memory
ZBT, DDR, SRAM Single-data rate (SDR)
Flexible-LVDS Solution
Mbps channel LVDS, LVPECL Hyper-
SDRAM
Transport
input output
PHY-Link Layer Interface
UTOPIA
Switch Fabric Interface
CSIX
channels
ASSP
POS-PHY Flexbus
Altera Corporation
Table APEX Highlights
Feature
1-Gbps True-LVDS solution 624-Mbps Flexible-LVDS solution Clock-data synchronization (CDS) registers element Enhanced PLLs Advanced ESBs PCI-X compliance SignalTap® logic analysis Density 89,280 logic elements MultiVolt operation FineLine BGApackaging Vertical migration
Benefit
Provides input output high-speed channels high-performance applications. Supports LVDS, LVPECL, PCML, HyperTransport input output channels high-bandwidth needs. Supports LVDS, LVPECL, HyperTransport Allows independent data channels interface with APEX device Provides support high-speed external memory interfaces such ZBT-, DDR-, QDR-based memory devices Supports ClockLockTM, ClockBoostTM, ClockShiftcircuitry flexible clock synthesis clock management with eight output taps off-chip outputs Implements dual-port with bidirectional read/write ports, first-in first-out (FIFO) buffers, ROM, CAM. Kbits memory Meets specifications 64-bit 66-MHz PCI-X Improves verification chip functionality Addresses system-level needs high-density device Ideal mixed voltage systems Area-optimized, 1.0-mm ball pitch provides high count Addresses changing device density without need re-spin board
Table APEX Device Overview
Feature
Maximum system gates Typical gates Logic elements ESBs General-purpose PLLs Maximum bits True-LVDS channels (transmit/receive) Flexible-LVDS channels (transmit/receive) Maximum user pins Available packages
EP2A15
1,900,000 600,000 16,640 425,984 36/36 56/56 724-Pin 672-Pin FineLine
EP2A25
2,750,000 900,000 24,320 622,592 36/36 56/56 724-Pin 672- 1,020-Pin FineLine
EP2A40
3,000,000 1,500,000 38,400 655,360 36/36 88/88 724-Pin 672- 1,020-Pin FineLine
EP2A70
5,250,000 3,000,000 67,200 1,146,880 36/36 88/88 1,038 724-Pin 1,508-Pin FineLine
EP2A90
7,000,000 4,000,000 89,280 1,523,712 36/36 88/88 1,048 724-Pin 1,508-Pin FineLine
Table APEX Protocol Support Advanced Applications
Application
RapidIO HyperTransport CSIX UTOPIA POS-PHY Level
Data Width (Bits)
Standard
LVDS LVDS HSTL Class LVDS LVDS LVTTL
Device Throughput (Gbps)
32.0 51.2 32.0 10.0 10.0
Altera Corporation
High-Performance Differential Support
APEX devices support multiple high-speed differential standards including True-LVDS Flexible-LVDS solutions, LVPECL, PCML, HyperTransport. Differential signaling techniques facilitate high data transfer rates, reduce electromagnetic interference, simplify printed circuit board design.
Flexible-LVDS Solution
Flexible-LVDS feature uses ESBs SERDES functions, enabling data transfers Mbps each Flexible-LVDS channel. APEX devices support receiver transmitter channels. Flexible-LVDS channels support LVDS, HyperTransport I/O, LVPECL inputs, LVDS HyperTransport outputs.
Clock-Data Synchronization True-LVDS Solution
True-LVDS solution uses dedicated circuitry perform high-speed data serialization/deserialization (SERDES). Each True-LVDS channel supports data transfer rates Gbps, shown Figure APEX devices feature receiver channels transmitter channels, well independent LVDS clock domains. Each channel supports LVPECL, PCML, HyperTransport well independent clock multiplication feature. True-LVDS clock-data synchronization (CDS) correct fixed multi-bit-period skew between different LVDS receiver channels, synchronizing them single clock input. APEX offers dedicated circuitry compensate fixed clock-to-data skew. offers designers flexibility synchronizing data from independent high-speed sources varying trace lengths skews, shown Figure Synchronizing clock data channels each high-speed True-LVDS channel independently significantly simplifies board design helps designers fully utilize high-speed capabilities APEX devices.
Figure APEX Clock-Data Synchronization
Enhances Chip-to-Chip Performance
Data Data Data
Clock
Figure 1-Gbps True-LVDS Solution APEX Devices
Clock
Clock
Clock
High-Speed External Memory Interfaces
element APEX devices supports emerging high-speed memory interfaces such ZBT, SRAMs, SDRAMs. APEX support external memory detailed Table Each element consists input registers, output registers, output-enable registers that facilitate these advanced memory access standards. addition APEX element, Altera also provides APEX optimized intellectual property (IP) MegaCore® functions implement memory controllers
Altera Corporation
Table External Memory Interface Support
Memory Type
SRAM
Memory
SRAM SRAM SRAM
Standard
LVTTL HSTL HSTL LVTTL SSTL
Breakthrough Performance with All-Layer-Copper Interconnect
APEX devices built state-of-the-art all-layercopper interconnect technology. Copper lower resistance better electromigration characteristics than aluminum. Copper interconnect delays lower than aluminum, translating core performance improvements, copper more scalable than aluminum, resulting smaller sizes.
DRAM
SDRAM* SDRAM
*SDRAM synchronous DRAM
that control data access from external memory devices. Please refer MegaStoresite list available controllers different types memory devices.
Advanced Phase-Locked Loops
APEX devices include four embedded generalpurpose PLLs with enhanced ClockLock, ClockBoost, ClockShift circuitry. These devices also feature four dedicated LVDS PLLs high-performance applications. ClockLock circuitry reduces clock delay skew within device. ClockBoost circuitry provides clock frequency multiplication division, minimizing number external clocks needed design. ClockShift circuitry provides programmable clock delay phase shift capability aligning clock edges. Each output taps with maximum eight output taps device that independently feed eight global clock lines internal device. Each APEX device also external clock output pins directly from separate PLLs.
Enhanced Embedded System Blocks
APEX devices feature ESBs total 1.45 Mbits memory. Each accommodates Kbits memory that configured various data widths: 256x16, 512x8, 1,024x4, 2,048x2, 4,096x1 bits. 4-Kbit ESBs split into 2-Kbit blocks, effectively doubling number ESBs. APEX ESBs support bidirectional read write ports based independent clocks, synchronous asynchronous operation, high-speed first-in first-out (FIFO) buffers. ESBs also configured highperformance used high-speed search applications. Multiple ESBs combined create deeper, wider CAM.
Altera Corporation
Quartus Development Tool Simplify Design
Altera QuartusII development tool allows designers process multi-million gate designs. Quartus software supports systemlevel solutions, integrates seamlessly with standard revision control software, allows designers implement advanced features such LVDS, CAM, PLLs into their device designs. Using Quartus software, designers easily integrate complex cores into their designs. shown Table Quartus software offers variety features system designer, making ideal platform multi-million-gate designs.
Table Quartus Highlights
Feature
LogicLockincremental design capability SignalTap embedded logic analyzer PowerFitfitting technology NativeLinkintegration Internet awareness
Benefit
Allows incremental optimization design Reduces verification time enabling designers internal signal values while system running speed Optimizes designs based user's timing specifications meets design requirements with minimal user effort Allows seamless integration with third-party tools Provides up-to-the-minute information file exchanges, software updates, support services through Internet
Contact Altera Today
APEX device family provides ideal solution your SOPC design needs. Visit Altera site today learn more about APEX device family complete solution http://www.altera.com.
Altera Corporation
Programmable Solutions Company
Altera Offices
Altera Corporation Innovation Drive Jose, 95134 Tel: (408) 544-7000 http://www.altera.com Altera U.K., Ltd. Holmers Farm High Wycombe, Buckinghamshire HP12 Tel: (44) Altera Japan, Ltd. Shinjuku i-Land Tower 5-1, Nishi-Shinjuku, 6-Chome Shinjuku-ku, Tokyo 163-1332 Japan Tel: (81) 3340 9480 http://www.altera.com/japan Altera International, Ltd. Suites 908-920, Tower MetroPlaza Hing Fong Road Kwai Fong, Territories Hong Kong Tel: (852) 2487 2030
Copyright 2001 Altera Corporation. Altera, APEX, APEX ClockLock, ClockBoost, ClockShift, FineLine BGA, Flexible-LVDS, MegaStore, LogicLock, MegaCore, MultiVolt, NativeLink, Quartus, Quartus PowerFit, SignalTap, True-LVDS, Programmable Solutions Company, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved. M-GB-APEXII-01

Complete Solution Altera introduces APEXII device family: highper

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