CS5651 High Performance Dual Channel Current Mode Controller with

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CS5651 High Performance Dual Channel Current Mode Controller with

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CS5651
CS5651
High Performance Dual Channel Current Mode Controller with ENABLE
CS5651 high performance, fixed frequency, dual current mode controller specifically designed Off-Line converter applications. offers designer cost effective solution with minimal external components. This integrated circuit features unique oscillator precise duty cycle limit frequency control, temperature compensated reference, high gain error amplifiers, current sensing comparators, high current totem pole outputs ideally suited driving power MOSFETs. outputs, VOUT2 switchable ENABLE2 pin. Also included protective features consisting input reference undervoltage lockouts, each with hysteresis; cycle-by-cycle current limiting; latch single pulse metering each output. CS5651 compatible with MC34065H.
Features
Oscillator Precise Duty Cycle Limit Frequency Control 500kHz Current Mode Operation Automatic Feed Forward Compensation Separate Latching PWMs Cycle-By-Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout Switchable Second Output High Current Totem Pole Outputs Input Undervoltage Lockout with Hysteresis
Block Diagram
VREF
5.0V
Undervoltage Lockout
VREF Undervoltage Lockout
SYNC Latching Oscillator
VOUT1
Sense1
Package Options
PDIP Wide
VFB1
Error COMP1 ENABLE2 Latching VOUT2
SYNC
VREF ENABLE2 VFB2 COMP2 Sense2 VOUT2
VFB2
Error COMP2
Sense2
VFB1 COMP1 SENSE1 VOUT1
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Site: www.cherry-semi.com
Rev. 3/9/99
Company
CS5651
Absolute Maximum Ratings Output Current, Source Sink (Note .400mA Output Energy (capacitive load cycle) .5.0µJ Current Sense, Enable Voltage .-0.3 +5.5V Feedback Inputs Sync Input High State (Voltage).5.5V State (Reverse Current).-5.0mA Error Output Sink Current.10mA Storage Temperature Range .-65 +150°C Operating Junction Temperature.+150°C Lead Temperature Soldering Wave Solder (through hole styles only).10 sec. max, 260°C peak Reflow (SMD styles only).60 sec. above 183°C, 230°C peak
Electrical Characteristics: 15V, 8.2k, 3.3nF, 70°C [Note unless otherwise specified.
PARAMETER TEST CONDITIONS UNIT
Reference Section Reference Output Voltage, VREF Line Regulation Load Regulation Total Output Variation over Line, Load Temperature Output Short Circuit Current Oscillator Sections Total Frequency Variation 15V, Tlow Thigh over Line Temperature Frequency Change with Voltage Duty Cycle each Output SYNC Current Maximum High State 2.4V State 0.8V 46.0 46.5 49.0 49.5 51.5 52.0 IOUT 1.0mA, 25°C 1.0mA IOUT 10mA 4.85 20.0 25.0 5.15
Error Amplifiers Voltage Feedback Input Input Bias Current Open-Loop Voltage Gain Unity Gain Bandwidth Output Current Output Voltage Swing VOUT 2.5V 5.0V 2.0V VOUT 4.0V 25°C (Note Source VOUT 3.0V, 2.3V Sink VOUT 1.2V, 2.7V High State ground, 2.3V State VREF, 2.7V -0.45 2.00 2.42 2.50 -0.1 -1.00 12.00 2.58 -1.0
Power Supply Rejection Ratio
CS5651
Electrical Characteristics: 15V, 8.2k, 3.3nF, 70°C [Note unless otherwise specified.
PARAMETER TEST CONDITIONS UNIT
Current Sense Section Current Sense Input Voltage Gain Maximum Current Sense Input Threshold Input Bias Current Propagation Delay Output Enable Enable Voltage High State State State Input Current Drive Outputs Output Voltage State High State Output Voltage with UVLO Activated Output Voltage Rise Time Output Voltage Fall Time ISINK 20mA ISINK 200mA ISOURCE 20mA ISOURCE 200mA 6.0V, ISINK 1.0mA 1.0nF (Note 1.0nF (Note 13.5 13.4 ENABLE2 enabled ENABLE2 disabled VREF Current Sense Input Output (Note (Notes (Note 2.75 3.00 -2.0 3.25 -30.0
13.0 12.0
Undervoltage Lockout Section Start-Up Threshold Minimum Operating Voltage Hysteresis Total Device Start-Up Current Operating Current (Note 10.0 11.0
Note Maximum package power dissipation limits must observed. Note duty cycle pulse techniques used during test maintain junction temperature close ambient possible. Note This parameter measured latch trip point with
Note Comparator gain defined
Compensation Current Sense
Note These parameters guaranteed design 100% tested production.
CS5651
Package PACKAGE SYMBOL FUNCTION
PDIP Wide SYNC positive going pulse applied this input will synchronize oscillator. voltage within range 2.4V 5.5V will inhibit oscillator. Timing capacitor connects ground setting oscillator frequency. Resistor connects ground setting charge current value must between 4.0k 16k. inverting input error amplifier Normally connected switching power supply output. output error amplifier loop compensation. Output pulse pulse current limit. Drives power switch output Logic ground Power ground. Power device return connected this pin. Drives power switch output Output pulse pulse current limit. Output error amplifier loop compensation. Inverting input error amplifier Normally connected switching power supply output. Output disable. logic this disables VOUT2. 5.0V reference output. source current excess 30mA. positive supply minimum operating voltage range after start-up Typical Performance Characteristics Timing Resistor Oscillator Frequency
2.2n
VFB1 COMP1 Sense1 VOUT1 VOUT2 Sense2 COMP2 VFB2 ENABLE2 VREF
Max. Output Duty Cycle Oscillator Frequency
MAXIMUM DUTY CYCLE 4.0k 15pF 25°C 100k 300k 500k 1.0M
TIMING RESISTOR
100p
1.0n
VCC= TA=25°C 100k 300k 500k 1.0M OSCILLATOR FREQUENCY (Hz)
OSCILLATOR FREQUENCY (Hz)
Error Open-Loop Gain Phase Frequency
AVOL, OPEN-LOOP VOLTAGE GAIN (dB) GAIN 1.5V 2.5V 100k 25°C PHASE Phase Margin (DEGREES)
Current Sense Input Threshold Error Output Voltage
Vth, CURRENT SENSE INPUT THRESHHOLD ERROR OUTPUT VOLTAGE 125°C 25°C -55°C
100k
1.0k
100k
1.0M
FREQUENCY (Hz)
CS5651
Typical Performance Characteristics: continued Reference Voltage Change Source Current
VREF, REFERENCE Voltage (mV) -4.0 -8.0 ref, REFERENCE SOURCE CURRENT (mA) 125°C 25°C
Reference Short Circuit Current Temperature
ISC, REFERENCE SHORT CIRCUIT CURRENT (mA)
-55°C
AMBIENT TEMPERATURE (°C)
Output Saturation Voltage Load Current
Supply Current Supply Voltage
ICC, SUPPLY CURRENT (mA)
RT=8.2k CT=3.3nF 2=0V CURRENT SENSE 2=0V TA=25°C
SOURCE SATURATION (LOAD GROUND)
Vsat, OUTPUT SATURATION VOLTAGE
-1.0 -2.0
VCC=15V 80µS PULSED LOAD 120Hz RATE TA=25°C
-55°C
-55°C TA=25°C
SINK SATURATION (LOAD VCC)
OUTPUT LOAD CURRENT (mA)
VCC, SUPPLY VOLTAGE CS-5651
Operating Description CS5651 high performance, fixed frequency, dual channel current mode controller Off-Line converter applications. Each channel contains high gain error amplifier, current sensing comparator, pulse width modulator latch, totem pole output driver. oscillator, reference, undervoltage lockout circuits common both channels.
Oscillator
making this controller suitable high frequency power conversion applications. noise sensitive applications necessary synchronize converter with external system clock. This accomplished applying external clock signal. reliable synchronization, oscillator frequency should about slower than clock frequency. rising edge clock signal applied SYNC, terminates charging VOUT2 conduction. tailoring clock waveform symmetry, accurate duty cycle clamping either output achieved.
Error Amplifier
oscillator both precise frequency duty cycle control. oscillator frequency programmed timing components Capacitor charged discharged equal magnitude internal current source sink, that generates symmetrical percent duty cycle waveform oscillator peak valley thresholds 3.5V 1.6V respectively. source/ sink current controlled resistor proper operation over temperature range RT's value should between 4.0k 16k. charges discharges, internal blanking pulse generated that alternately drives inputs upper lower gates high. This, conjunction with precise amount delay time introduced into each channel, produces well defined non-overlapping output duty cycles. Output enabled while charging, Output enabled during discharge. Even 500kHz, each output capable approximately duty cycle,
Each channel contains fully-compensated error amplifier with access output inverting input. amplifier features typical voltage gain unity gain bandwidth with degrees phase margin. non-inverting input internally biased 2.5V. converter output voltage typically divided down monitored inverting input through resistor divider. maximum input bias current -1.0 which will cause output voltage error that equal product input bias current equivalent input divider resistance. output voltage offset diode drops (1.4V) divided three before connects inverting input current sense comparator. This guarantees that both
CS5651
Operating Description: continued outputs disabled when error amplifier output lowest state (VOUT(LOW)). This occurs when power supply operating light no-load conditions, beginning soft-start interval. minimum allowable error amplifier feedback resistance limited amplifier's source current capability (0.5 output voltage (VOUT(High)) required reach current sense comparator 1.0V clamp level with error amplifier inverting input ground. This condition happens during initial system start when sensed output shorted: RF(min) 1.0V) 1.4V 8.8k 0.5mA comparator built-in hysteresis prevent erratic output behavior their respective thresholds crossed. comparator upper lower thresholds CS5651. VREF comparator disables outputs until internal circuitry functional. This comparator upper lower thresholds 3.6V 3.4V. guaranteed minimum operating voltage after turn-on CS5651. Outputs Power Ground Each channel contains single totem-pole output stage specifically designed driving power MOSFET. outputs have ±1.0A peak current capability have typical rise fall time 28ns with 1.0nF load. Internal circuitry been added keep outputs active pull-down mode whenever undervoltage lockout active. external pull-down resistor needed. Cross-conduction current totem-pole output stage been minimized high speed operation. average added power cross-conduction with only 60mW 500kHz. Although outputs were optimized MOSFET's, they easily supply negative base current required bipolar transistors enhanced turn-off. Because outputs contain internal current limiting circuitry, external series resistor required prevent peak output current from exceeding ±1.0A maximum rating. sink saturation voltage (VOL) less than 0.4V 100mA. separate Power Ground provided will significantly reduce level switching transient noise imposed control circuitry. This becomes particularly important when Ipk(max) clamp level reduced. This input used switch VOUT2. VOUT1 used control circuitry that runs continuously; e.g. volatile memENABLE2 ory, system clock, remote controlled receiver. VOUT2 output control high power circuitry that turned when needed.
Current Sense Comparator Latch CS5651 operates current mode controller. Output switch conduction initiated oscillator terminated when peak inductor current reaches threshold level established error amplifier output. error signal controls peak inductor current cycleby-cycle basis. current sense comparator-PWM Latch combination ensures that only single pulse appears output during given oscillator cycle. current converted voltage connecting sense resistor RSense series with source output switch ground. This voltage monitored Sense1,2 pins compared voltage derived from error output. peak current under normal operating conditions controlled voltage COMP where: VCOMP 1.4V 3RSense
Abnormal operating conditions occur when power supply output overloaded output voltage high. Under these conditions, current sense comparator threshold will internally clamped 1.0V. Therefore maximum peak switch current Ipk(max) 1.0V RSense
Voltage Reference 5.0V bandgap reference trimmed ±2.0% tolerance. reference short circuit protection capable sourcing 30mA powering additional external circuitry. Design Considerations High frequency circuit layout techniques imperative prevent pulse-width jitter. This usually caused excessive noise pick-up imposed current sense voltage feed-back inputs. Noise immunity improved lowering circuit impedances these points. printed circuit board layout should contain ground plane with current signal high current switch output grounds returning separate paths back input fil6
Erratic operation noise pickup result there excessive reduction Ipk(max) clamp voltage. narrow spike leading edge current waveform usually observed cause power supply exhibit instability when output lightly loaded. addition filter current sense input reduces this spike acceptable level. Undervoltage Lockout undervoltage lockout comparators have been incorporated guarantee that fully functional before output stages enabled. reference output VREF monitored separate comparators. Each
CS5651
Operating Description: continued capacitor. Ceramic bypass capacitors (0.1µF) connected directly VREF required improve noise filtering. This provides impedance path filtering high frequency noise. high current loops should kept short possible using heavy copper runs. error compensation circuitry converter output voltage-divider should located close possible from power switch other noise generating components.
Timing Diagram
SYNC Capacitor Latch "Set" Input COMP1 Sense1 Latch "Reset" Input VOUT1
ENABLE2 Latch "Set" Input COMP2 Sense2 Latch "Reset" Input VOUT2
Typical Application Diagram
Dual Boost Regulator
5.0V VREF 2.5V Sync VOUT1 RFB1 RFB2 VFB1 COMP1 ENABLE2 VOUT2 RFB3 RFB4 VFB2 COMP2 Error Error Oscillator Current Sense Comparator 1.0VREF 1.0V Internal Bias 3.4V
Reference Regulator
UVLO VOUT1 COUT1
VREF UVLO
Latch
VOUT1 RSense1 Sense1 VOUT2 COUT2
250µA Current Sense Comparator 1.0mA 1.0V Latch
VOUT2
Sense2
RSense2
CS5651
Package Specification
PACKAGE DIMENSIONS (INCHES) PACKAGE THERMAL DATA
Lead Count Lead PDIP Lead Wide
Metric 19.69 18.67 10.50 10.10
English .775 .735 .413 .398
Thermal Data
Lead PDIP
Lead Wide
°C/W °C/W
Plastic (N); wide
7.11 (.280) 6.10 (.240)
8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115)
1.77 (.070) 1.14 (.045)
2.54 (.100)
.356 (.014) .203 (.008)
0.39 (.015) MIN. .558 (.022) .356 (.014) Some lead packages have lead package. specs same.
REF: JEDEC MS-001
Surface Mount Wide Body (DW); wide
7.60 (.299) 7.40 (.291)
10.65 (.419) 10.00 (.394)
0.51 (.020) 0.33 (.013)
1.27 (.050)
2.49 (.098) 2.24 (.088)
2.65 (.104) 2.35 (.093)
1.27 (.050) 0.40 (.016)
REF: JEDEC MS-013
0.32 (.013) 0.23 (.009) 0.30 (.012) 0.10 (.004)
Ordering Information
Part Number CS5651GN16 CS5651GDW16 CS5651GDWR16
Rev. 3/9/99
Description PDIP Wide Wide (Tape Reel)
Cherry Semiconductor Corporation reserves right make changes specifications without notice. Please contact Cherry Semiconductor Corporation latest available information.
1999 Cherry Semiconductor Corporation

CS5651 High Performance Dual Channel Current Mode Controller with

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