16-Bit CS5181 fully calibrated high-speed analog-todigital conver

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16-Bit CS5181 fully calibrated high-speed analog-todigital conver

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CS5181 Modulator 16-Bit
16-Bit
CS5181 fully calibrated high-speed analog-todigital converter, capable kSamples/second output word rate (OWR). scales with master clock. consists order modulator, decimation filter, serial interface. chip 2.375 on-chip voltage reference, external reference. input voltage range VREFIN fully differential. Multiple CS5181s fully synchronized multi-channel applications with sync signal. part power-down mode minimize power consumption times system inactivity. high speed digital lines have complementary signals help reduce radiated noise from traces board layout. CS5181 also operated modulator-only mode which provides delta-sigma modulator bitstream output. ORDERING INFORMATION CS5181-BL 28-pin PLCC
Delta-Sigma Converter Fully Differential Input with Range Dynamic Range: Spurious Free Dynamic Range: Harmonic Distortion: Output Word Rate Missing Codes Non-Aliasing Low-Pass Digital Filter High Speed 3-Wire Serial Interface Supply Requirements:
Modulator
Output Mode Power-Down Mode
AGND
DGND
AIN+ AINVREFVREF+ VREFIN x1.6
Modulator
Decimator
Clock
MCLK MCLK
Mode Selector
MFLAG
VREFOUT VREFCAP
Reference
Timing Control
Serial Interface
SCLK SCLK
PWDN
SYNC RESET MODE
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved)
Preliminary Product Information
Cirrus Logic, Inc. P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
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CS5181
TABLE CONTENTS
CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS. DYNAMIC CHARACTERISTICS DIGITAL CHARACTERISTICS. SWITCHING CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS GENERAL DESCRIPTION THEORY OPERATION Converter Initialization: Calibration Synchronization Clock Generator Voltage Reference Analog Input Output Coding Modulator-Only mode Instability Indicator Digital Filter Characteristics Serial Interface Power Supplies Board Layout Power-down Mode DESCRIPTIONS PARAMETER DEFINITIONS APPENDIX CIRCUIT APPLICATIONS PACKAGE OUTLINE DIMENSIONS
Contacting Cirrus Logic Support
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Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
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CS5181
TABLE FIGURES
Serial Port Timing (not scale) RESET SYNC logic timing. CS5181 connection diagram using internal voltage reference. CS5181 connection diagram using external voltage reference. Modulator Only Mode Data Format. Circuit Reconstruct Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream. Magnitude versus frequency spectrum modulator bitstream (MCLK 40.0 MHz). Expanded view magnitude versus frequency spectrum modulator bitstream (MCLK MHz). CS5181 Digital Filter Magnitude Response (MCLK MHz) CS5181 Digital Filter Phase Response (MCLK MHz) CS5181 System Connection Diagram Single amplifier driving only AIN+, with AIN- held steady value Performance amplifier Figure overdriving AIN+ input CS5181 Performance amplifier Figure with AIN+ driven Four amplifier balanced driver. Performance amplifier Figure Performance amplifier Figure CS5181 Differential Non-linearity plot. (Data taken with repeating ramp) Histogram from Figure CS5181 Noise Histogram, 32768 samples.
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CS5181
CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS ±5%, ±0.3V; AGND DGND MCLK 40.0 MHz; VREFIN VREFOUT; MODE VD+; Analog Source Impedance Ohms with 2200 AGND; Full-Scale input Sinewave kHz; Unless otherwise noted.)
Parameter Symbol (Note (Note SINAD SFDR (Note (Note (Note (Notes (Note (Note (Note (Note CMRR 2.25 (Note 2.25 ±6.0 VREFIN ±160 2.375 2.375 ±0.5 VREFIN 0.25 ±320 ±320 ±500 Unit ppm/°C µV/°C
Dynamic Performance Dynamic Range Total Harmonic Distortion Signal (Noise Distortion) Spurious Free Dynamic Range Static Performance Integral Nonlinearity Differential Non-Linearity Full Scale Error Full Scale Drift with Internal Reference Offset Error Offset Drift Analog Input Differential Input Voltage Range
Common Mode Range Input Capacitance Differential Input Impedance (capacitive) Common Mode Rejection Ratio Common Mode Input Current
Reference Input VREFIN VREFIN Current Reference Output VREFOUT Voltage VREFOUT Output Current VREFOUT Impedance
Notes: Dynamic range tested with input signal below full scale. Specification guaranteed design, characterization, and/or test. Full scale fully-differential input span nominally VREFIN voltage. peak negative excursion signals AIN+ AIN- should below AGND proper operation. VREFIN current less than under normal operation, high ±320 during calibration. Drift on-chip reference alone typically about ppm/°C. using external reference, total full scale drift will that external reference plus additional ppm/°C, which typical drift X1.6 buffer. Applies after self-calibration final operating ambient temperature.
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CS5181
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol (Note PSRR 92.4 0.062 18.9 0.062 Unit
Power Supplies
Power Supply Current (MODE PWDN VA1+, VA2+ VD1+, VD2+
Power Supply Current (MODE PWDN (Notes VA1+, VA2+ VD1+, VD2+ Power Supply Current (MODE PWDN VA1+, VA2+ VD1+, VD2+ (Note
Power Supply Current (MODE PWDN (Notes VA1+, VA2+ VD1+, VD2+ Power Supply Rejection (Note
Notes: outputs unloaded. inputs except MCLK held static DGND. Power consumption when PWDN applies only master clock applied (MCLK held high low). Measured with mVpp sine wave supplies frequency
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Word Rate Symbol MCLK MCLK/64 MCLK/142.3804 MCLK/128 2370/MCLK ±0.05 Unit
Filter Characteristics Corner Passband Ripple Stopband Frequency Stopband Rejection Group Delay
(Note
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage -100 Low-Level Output Voltage Input Leakage Current Input Capacitance
3.3V ±0.3V; AGND DGND Unit
Symbol
Specifications subject change without notice.
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CS5181
SWITCHING CHARACTERISTICS ±5%,
AGND DGND MODE VD+) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Notes Digital Input, Except MCLK MCLK Digital Output (Notes Digital Input, Except MCLK MCLK Digital Output trise tfall 1/MCLK 1/MCLK 988205/MCLK 5161/MCLK 5168/MCLK MCLK/3 1/MCLK 2/MCLK 2/MCLK 2E-9 1/MCLK 2E-9 .2/MCLK .2/MCLK (Note Symbol MCLK 0.512 Unit ±0.3
Fall Times
Calibration/Sync
RESET rising MCLK rising RESET rising recognized, falling SYNC rising MCLK rising SYNC rising recognized falling PWDN rising recognized falling SYNC high time RESET time
Serial Port Timing SCLK frequency SCLK high time SCLK time falling SCLK rising SCLK falling data SCLK rising rising
(Note
Notes: Rise Fall times specified points waveform. RESET, SYNC, PWDN have Schmitt-trigger inputs. Specifications applicable complementary signals SCLK SDO.
SCLK SDATA MSB-1 LSB-1
Figure Serial Port Timing (not scale)
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CS5181
RECOMMENDED OPERATING CONDITIONS (AGND DGND
Parameter Power Supplies Analog Reference Voltage AGND DGND differential Operating Junction Temperature Digital Analog Symbol VREFIN 4.75 2.25 -100 5.25 Unit
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supplies Symbol Ground AGND/DGND Digital Analog Iout VINA VIND Tstg -0.3 -0.3 -0.3 -0.3 -0.3 (VD+) 1000 (VA+) (VD+) Unit
Input Current, except Supplies Output Current Power Dissipation (Total) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
Specifications subject change without notice.
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CS5181
GENERAL DESCRIPTION
CS5181 monolithic CMOS 16-bit converter designed operate continuous mode after being reset. CS5181 operate modulator-only mode which stream from modulator data output from device. CS5181 designed perform conversions continuously with output rate that equivalent MCLK/64. conversions performed serial port updated independent external controls. converter designed measure differential bipolar input signals, unipolar signals, with common mode voltage between VREF 0.25 Calibration performed when RESET signal device released. RESET properly framed MCLK, converter synchronized specific MCLK cycle system level. SYNC signal also used synchronize multiple converters system. When SYNC used, converter does perform calibration. SYNC signal recognized first rising edge MCLK after SYNC goes high. SYNC aligns output conversion occur every MCLK clock cycles after SYNC signal recognized filter settled. After SYNC initiated going high, converter will wait 5,161 MCLK cycles digital filter settle before putting fully-settled conversion word. synchronize multiple converters system, SYNC pulse should rise falling edge MCLK signal. This ensures that SYNC input CS5181s system will recognized next rising edge MCLK. SYNC input
THEORY OPERATION
front page this data sheet illustrates block diagram CS5181.
Converter Initialization: Calibration Synchronization
CS5181 does have internal power-on reset circuit. Therefore when power first applied device RESET should held until power established. This resets converter's logic known state. When power fully established converter will perform self-calibration, starting with first MCLK rising edge after RESET goes high. converter will 988,205 MCLK cycles complete calibration allow digital filter fully settle, after which, will output fullysettled conversion words. converter will then continue output conversion words output word rate equal MCLK/64. Figure illustrates RESET SYNC logic timing converter.
CS5181
RESET RESET
MCLK RESET
MCLK MCLK SYNC
988205 MCLK Cycles
SYNC SYNC
5161 MCLK Cycles
Figure RESET SYNC logic timing.
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CS5181
necessary make converter operate properly. unused should tied DGND. Conversion data output from pins device. data output from first, two's complement format. converter furnishes serial clock SCLK complement SCLK latch data bits; data frame signal, Frame Signal Output (FSO), which frames output conversion word. SCLK output frequency MCLK/3.
Voltage Reference
CS5181 configured operate from either internal voltage reference, from external voltage reference. on-chip voltage reference nominally 2.375 referenced AGND pins. This 2.375 reference output from VREFOUT pin. then filtered returned VREFIN pin. VREFIN connected buffer which typical gain 1.6. This scales on-chip reference 2.375 This value sets peak-to-peak input voltage into pins converter. Figure illustrates CS5181 connected internal voltage reference. Note that capacitor shown connected VREFCAP filter noise. larger capacitor used, require longer reset period when first powering part allow reference stabilize before part self-calibrates. Alternatively, CS5181 configured external voltage reference. Figure illustrates CS5181 connected external reference. this case, maximum peak-to-peak signal input pins
Clock Generator
CS5181 must driven from CMOS-compatible clock MCLK pin. MCLK input powered from supply signal input should exceed this supply. required MCLK (Output Word Rate). achieve Output Word Rate kHz, MCLK frequency must kHz, MHz. second clock input pin, MCLK, actually used inside device allows user fully differential clock converter minimize radiated noise from board layout. CS5181 operated with MCLK frequencies from MHz. output word rate scales with MCLK rate with MCLK/64.
CS5181
VREFIN VREF+ VREF-
X1.6 Modulator
VREFOUT VREFCAP
Reference
Figure CS5181 connection diagram using internal voltage reference.
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CS5181
CS5181
VREFIN
X1.6 Modulator
VREF+ VREF-
VREFOUT VREFCAP
Reference
Figure CS5181 connection diagram using external voltage reference.
Analog Input
analog signal converter input into AIN+ AIN- pins. input signal fully differential with maximum peak-to-peak amplitude VREFIN signal needs have common mode voltage range from VREF 0.25 minimum distortion. resistor-capacitor filter should included AIN+ AIN- inputs converter. This should consist resistor 2200 capacitor each input ground illustrated system connection diagram (Figure 11).
Fully Differential Bipolar Input Voltage1 >(VFS LSB) -0.5 -VFS <(-VFS LSB)
Twos Complement 7FFF 7FFF 7FFE 0000 FFFF 8001 8000 8000
Notes: VREFIN Table Output Coding.
Output Coding
Table illustrates output coding converter when operating with digital filter (MODE converter outputs data from serial port twos complement format, first. chip offers MFLAG signal indicate when modulator gone unstable. MFLAG when overrange signal forces modulator into unstable condition. Under this condition, output
codes from converter will locked either plus minus full scale appropriate overrange condition.
Modulator-Only mode
CS5181 operated modulator-only mode connecting MODE logic (DGND). modulator-only mode noise-shaped bitstream from fifth-order delta-sigma modulator output from (inverse bitstream) pins.
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CS5181
MCLK Modulator Data Reconstructed Data
Figure Modulator Only Mode Data Format.
data from modulator output from SDO/SDO (Return Zero) format. circuit Figure used reconstruct data captured with rising falling edge MCLK. Table illustrates magnitude input signal into chip versus ones density modulator. table does take into account potential offset gain errors modulator their effect ones density.
Fully Differential Bipolar Input Voltage2 -VFS Modulator Ones Density3
Figure Figure illustrate magnitude versus frequency plots modulator bitstream when running 40.0 MHz.
Notes: VREFIN Ones density approximate; does take offset gain errors into consideration. Table Modulator-Only Mode Ones Density.
Figure Magnitude versus frequency spectrum modulator bitstream (MCLK 40.0 MHz).
Reconstructed Data
Reconstructed Data
Figure Circuit Reconstruct Return-to-Zero (RTZ) Data from SDO/SDO into Original Modulator Bitstream.
Figure Expanded view magnitude versus frequency spectrum modulator bitstream (MCLK MHz).
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CS5181
Instability Indicator
MFLAG signal functional both modes operation part indicates when modulator been overdriven into unstable condition. modulator only mode (MODE MFLAG signal will remain MCLK cycles when modulator goes unstable, before being returned reset state. While input condition causing modulator instability persists, MFLAG signal will continually MCLK cycles then reset. When decimation filter part operational (MODE MFLAG signal when modulator goes unstable. this mode, however, MFLAG signal stays until 5,120 MCLK cycles after input condition causing modulator instablility removed. This delay provided allow digital filter time settle, part will output fully settled conversion words after MFLAG signal goes low.
Figure CS5181 Digital Filter Magnitude Response (MCLK MHz)
250.00 200.00 150.00
Phase (deg.)
100.00 50.00 0.00 -50.00 -100.00 -150.00 -200.00 -250.00
100k 150k 200k Freq (Hz) 250k 300k
Digital Filter Characteristics
Figure illustrates magnitude versus frequency plot converter when operating output word rate. filter non-aliasing 4265 filter with corner 0.4495 output word rate out-of-band attenuation least frequencies above half output word rate. passband ripple less than ±0.05 corner frequency. Figure illustrates phase response digital filter with converter operating output word rate. filter characteristics change proportional changes MCLK rate. group delay digital filter 2370 MCLK cycles (59.3 with MCLK MHz), settling time 4740 MCLK cycles (118.5 µs).
Figure CS5181 Digital Filter Phase Response (MCLK MHz)
rial Data Output (SDO), complement (SDO); Serial Clock (SCLK), complement (SCLK); Frame Sync Output (FSO). falls beginning output word. Data output twos complement format, first. stays SCLK cycles. SCLK output rate equal MCLK/3.
Serial Interface
CS5181 serial interface through which conversion words output synchronous selfclocking format. serial port consists Se12
Power Supplies Board Layout
CS5181 requires analog supply voltage Volts digital supply voltage Volts (nominal) proper operation.
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CS5181
Figure illustrates system connection diagram chip. best performance, each supply pins should bypassed nearest ground chip. bypass capacitors should located close chip possible. chip surface mounted bypass capacitors should same side circuit card chip. CS5181 high speed component that requires adherence standard high-frequency printed circuit board layout techniques maintain optimum performance. These include ground power planes, using noise power supplies conjunction with proper supply decoupling, minimizing circuit trace lengths, physical separation digital analog components circuit traces. preferred that clock oscillator circuitry located ground plane separate from digital plane order ensure that digital noise does induce clock jitter. additional insight, CDB5181 evaluation board more details. Also refer Application Note AN18 which covers layout design rules high resolution data converters.
AGND1
DGND1
VA1+
VD1+
+3.3
VA2+
CS5181
VD2+
AGND2
DGND2
AGND3 PWDN MODE RESET SYNC MFLAG VREF+ MCLK
VREFOUT
VREFIN VREF-
Control Logic
MCLK
VREFCAP
Clock Source
AIN+
Fully Differential 2.375
SCLK SCLK
Data Interface
2200 2200 AIN-
fully differential input span converter's internal voltage reference 2.375 input span fully differential would result external voltage reference used.
Figure CS5181 System Connection Diagram
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CS5181
Power-down Mode
CS5181 PWDN (power-down) function. When active low, power most converter's circuitry will reduced. MCLK stopped save power, should stopped until least clock cycles after PWDN taken low. clock cycles required allow part turn it's internal circuitry. part does full clock cycles, will still into power down state, power dissipation could more than listed specifications full power down condition. When PWDN active, calibration information inside converter maintained. When coming power-down state, converter recalibrated will start-up similar when SYNC initiated.
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CS5181
DESCRIPTIONS
Analog Ground Pos. Reference Neg. Reference Pos. Reference Input Analog Ground Analog Supply Invalid Conversion Sync. Filter Digital Ground Pos. Digital Supply Inverse Serial Clock Serial Clock AGND VREF+ VREFVREFIN
VA1+ AINAIN+ PWDN
Positive Analog Supply Negative Analog Input Positive Analog Input Power Down Mode Modulator Only Mode Digital Ground Positive Digital Supply Master Clock Inverse Master Clock Analog Ground Frame Sync Output Serial Data Inverse Serial Data Out\ Analog Ground Positive Analog Supply Analog Ground Negative Analog Input Positive Analog Input Analog Ground Power Down Mode Modulator Only Mode Digital Ground Digital Ground Positive Digital Supply Positive Digital Supply Digital Ground Master Clock Inverse Master Clock Digital Ground Analog Ground Frame Sync Output Serial Data Inverse Serial Data Out\
Reference Output VREFOUT Reference Bypass VREFCAP AGND VA2+ MFLAG SYNC DGND VD2+ SCLK SCLK
MODE DGND VD1+ MCLK MCLK AGND AGND
RESET Reset Calibration
CS5181
Analog Ground Pos. Reference Neg. Reference Analog Ground Analog Ground Reference Input Analog Ground Analog Ground Analog Supply Analog Supply Invalid Conversion Sync. Filter Digital Ground Digital Ground Pos. Digital Supply Pos. Digital Supply Digital Ground Inverse Serial Clock Serial Clock
AGND VREF+ VREFAGND AGND VREFIN
4443424140393837363534
VA1+ AGND AINAIN+ AGND PWDN MODE DGND DGND VD1+ VD1+ DGND MCLK MCLK DGND AGND
Reference Output VREFOUT
Reference Bypass VREFCAP AGND AGND VA2+ VA2+ MFLAG SYNC DGND DGND VD2+ VD2+ DGND SCLK SCLK
RESET Reset Calibration
CS5181
12131415 16171819202122
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CS5181
Supply Inputs VA1+, VA2+ Positive Analog Supply Input positive analog supply +5.0 typical when AGND AGND Analog Ground Analog ground circuits supplied VA+. VD1+, VD2+ Positive Digital Supply Input positive digital supply +3.3 typical when DGND DGND Digital Ground Digital ground circuits supplied VD+. Signal Reference Related Inputs AIN+, AIN- Differential Analog Inputs Fully differential signal inputs. VREFIN Voltage Reference Input VREFOUT external reference connected VREFIN. Analog input voltage (full scale fully differential peak-to-peak) into converter times this value. VREF+ Positive Voltage Reference Filter capacitor connection reference input buffer. voltage this equals VREFIN 1.6. VREF- Negative Voltage Reference VREF- connected AGND. VREFOUT Voltage Reference Output Output 2.375 volt on-chip reference relative AGND. VREFCAP Reference Bypass Filter capacitor connection internal reference. Serial Interface Signals SCLK, SCLK Serial Interface Clock Serial Clock Output. gated serial clock output from converter rate equal MCLK clock rate. SCLK output complement SCLK helps reduce radiated noise lines adjacent board layout drive balanced load.
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CS5181
SDO, Serial Data Serial Data Output. Output 16-bit serial data word. output complement helps reduce radiated noise lines adjacent board layout. Output data output twos complement format first. Frame Sync Output Frame Sync Output. Frame Sync Output turns indicate beginning output word from pin. returns high after data bits have been clocked out. Control Pins RESET Reset Calibration When RESET pulled logic converter will perform reset digital logic. When level this brought back logic high chip starts normal operation, following clock cycle delay period. When MODE chip goes through internal gain offset calibration routine following this reset sequence. PWDN Power Down Mode logic PWDN will device into power-down mode. MODE Modulator Only Mode MODE held logic high normal operation. normal operation device utilizes digital decimation filter calibration ciruitry. MODE puts part modulator only mode whereby most digital circuitry powered-down modulator bit-stream output from pins. SYNC Synchronization Filter SYNC input used restart digital filter converter beginning convolution cycle. SYNC input used synchronize filters multiple converters system. When SYNC signal goes high, filter will initialized will begin convolution cycle next rising edge MCLK. used, SYNC DGND. MFLAG Invalid Conversion Flag MFLAG goes high modulator portion converter goes unstable. MFLAG high, output data from converter invalid. MCLK, MCLK Master Clock Signal Master clock input accepts CMOS level clock input converter with worst case duty cycle 45-55% (typically MHz). MCLK actually used inside device, used radiated noise cancellation MCLK MCLK adjacent each other board.
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CS5181
PARAMETER DEFINITIONS
Differential Non-Linearity Error deviation code's width from ideal. Units LSBs. Integral Non-Linearity Error deviation code from straight line passing through endpoints transfer function after zero- full-scale errors have been accounted for. "Zero-scale" point below first code transition "full-scale" point beyond code transition ones. deviation measured from middle each particular code. Units LSB's. Full-Scale Error FSEP deviation last code transition from ideal (VREF-3/2 LSB's). Units LSB's. Offset Error deviation mid-scale transition from ideal (1/2 below Volts). Units LSB's. Spurious-Free-Dynamic-Range SFDR ratio value full-scale signal, value next largest spectral component (excepting dc). This component often aliased harmonic when signal frequency significant proportion sampling rate. Units (decibels relative carrier). Total Harmonic Distortion ratio significant harmonics (2nd thru 7th), value full-scale signal. Units decibels. Dynamic Range ratio value inferred full-scale signal, broadband noise signals below Nyquist rate (excepting distortion terms). Expressed decibels. Dynamic Range tested with input signal below full scale. then added resulting number refer noise level full-scale signal. This technique ensures that distortion components below noise level affect measurement. Signal-to-Noise-and-Distortion (s/[n+d]) SINAD ratio value full-scale signal, other spectral components below Nyquist rate (excepting dc), including distortion components. Expressed decibels. Group Delay time delay through digital filter section part. Units seconds.
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CS5181
Resolution number different output codes possible. Expressed where number available output codes. Noise measure variability converter's output when fixed input (usually ground) applied input large number samples taken. noise determined statistically Standard Deviation Probability Density Function derived from histogram with differential inputs shorted together tied appropriate common mode voltage. Common Mode Rejection Ratio CMRR measure device's ability cancel effect common voltage applied both differential inputs. CMRR specified ratio differential signal gain gain common-mode signal. Units Offset Drift Changes offset error part after self calibration changes ambient temperature. Specified microvolts degree relative input signal. Full Scale Drift Changes full scale error part after self calibration changes ambient temperature. Specified parts-per-million (PPM) full scale range degree
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CS5181
APPENDIX CIRCUIT APPLICATIONS
Several amplifier circuits have been tested with CS5181. Performance higher frequencies generally limited operational amplifiers used drive converter. Figure illustrates single operational amplifier circuit which accept single-ended ground-referenced signal condition input CS5181. amplifier AC-coupled signal source. this circuit AIN- input CS5181 held constant value AIN+ input driven actually overdriven achieve high dynamic range, this sacrifices performance with regard distortion). common mode voltage CS5181 input should designed stay between VREF 0.25 when driven AIN+ AIN- inputs. single amplifier circuit figure disadvantages that common mode restriction limits input signal range also causes errors variation common mode voltage, opposed applying balanced differential signal. Figures illustrate performance amplifier Figure operating with input into AIN+ input; with input into AIN+ input respectively.
Figure Performance amplifier Figure overdriving AIN+ input CS5181
Test Signal: 30.14 85.46 71.25 S/N+D 71.09 8192 Samples
Figure Performance amplifier Figure with AIN+ driven
0.15
AIN+ 2200
CS5181
AIN-
2200 VREFOUT
Figure Single amplifier driving only AIN+, with AIN- held steady value
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CS5181
AIN2200
CS5181
2200
AIN+
VREFOUT
Figure Four amplifier balanced driver.
Figure illustrates four amplifier circuit which gives best performance keeping everything balanced. Performance generally limited amplifiers. Again, output resistors used scale down input signal. Figures illustrate performance CS5181 with this amplifier circuit. Figure illustrates Differential Non-linearity plot converter. Data plot taken using repeating ramp. Figure histogram data Figure Figure illustrates noise histogram converter with inputs shorted connected proper common mode voltage.
Test Signal: 93.2 88.6 S/N+D 87.2 8192 Samples
Figure Performance amplifier Figure
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CS5181
Test Signal: 92.0 85.9 S/N+D 85.0 8192 Samples
Figure Performance amplifier Figure
Figure CS5181 Differential Non-linearity plot. (Data taken with repeating ramp)
Figure Histogram from Figure
Figure CS5181 Noise Histogram, 32768 samples.
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PACKAGE OUTLINE DIMENSIONS
PLCC PACKAGE DRAWING
D2/E2
INCHES 0.165 0.090 0.013 0.485 0.450 0.390 0.485 0.450 0.390 0.040 0.180 0.120 0.021 0.495 0.456 0.430 0.495 0.456 0.430 0.060
MILLIMETERS 4.043 4.572 2.205 3.048 0.319 0.533 11.883 12.573 11.025 11.582 9.555 10.922 11.883 12.573 11.025 11.582 9.555 10.922 0.980 1.524
JEDEC MS-018
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16-Bit CS5181 fully calibrated high-speed analog-todigital conver

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