BiCMOS Interface Logic, Octal D-Type Flip-Flops, Three-State CD74

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BiCMOS Interface Logic, Octal D-Type Flip-Flops, Three-State CD74

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CD74FCT564, CD74FCT574
BiCMOS Interface Logic, Octal D-Type Flip-Flops, Three-State
CD74FCT564 CD74FCT574 octal D-Type, three-state, positive edge triggered flip-flops which small geometry BiCMOS technology. output stage combination bipolar CMOS transistors that limits output HIGH level diode drops below VCC. This resultant lowering output swing 3.7V) reduces power ringing source EMI) minimizes bounce ground bounce their effects during simultaneous output switching. output configuration also enhances switching speed capable sinking milliamperes. eight flip-flops enter data into their registers HIGH transition clock (CP). Output Enable (OE) controls three state outputs independent register operation. When Output Enable (OE) HIGH, outputs high impedance state. CD74FCT564 CD74FCT574 share same configurations; CD74FCT564, however, inverted outputs CD74FCT574 noninverted outputs.
January 1997
Features
Buffered Inputs
ENDE IGNS ology Techn
Typical Propagation Delay: 5.6ns 25oC Positive Edge Triggered CD74FCT564 Inverting CD74FCT574 Noninverting Latchup Resistant BiCMOS Process Circuit Design Speed Bipolar FASTTM/AS/S 48mA Output Sink Current Output Voltage Swing Limited 3.7V Controlled Output Edge Rates Input/Output Isolation BiCMOS Technology with Quiescent Power
Ordering Information
PART NUMBER CD74FCT564E CD74FCT574E CD74FCT564M CD74FCT574M CD74FCT574SM TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC SSOP PKG. E20.3 E20.3 M20.3 M20.3 M20.209
NOTE: When ordering suffix packages, entire part number. suffix obtain variant tape reel.
Pinouts
CD74FCT564 (PDIP, SOIC, SSOP) VIEW
CD74FCT574 (PDIP, SOIC, SSOP) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis trademark Fairchild Semiconductor. Copyright Harris Corporation 1997
File Number
2295.2
CD74FCT564, CD74FCT574 Functional Diagram
TRUTH TABLE (NOTE
CD74FCT574 CD74FCT564
OUTPUTS INPUTS CD74FCT564 CD74FCT574
NOTE:
High Level (Steady State) Level (Steady State) Don't Care Transition from high level level before indicated steady state input conditions were established. HIGH Impedance
Logic Symbols
CD74FCT564
CD74FCT574
CD74FCT564, CD74FCT574
Absolute Maximum Ratings
Supply Voltage (VCC) -0.5V Diode Current, (For -0.5V) -20mA Output Diode Current, (for -0.5V) -50mA Output Sink Current Output Pin, 70mA Output Source Current Output Pin, -30mA Current (ICC) 140mA Ground Current (IGND). 400mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package SSOP Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC SSOP-Lead Tips Only)
Operating Conditions
Operating Temperature Range, .0oC 70oC Supply Voltage Range, .4.75V 5.25V Input Voltage, Output Voltage, Input Rise Fall Slew Rate, dt/dv. 10ns/V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications Temperature Range 70oC, 5.25V, 4.75V
AMBIENT TEMPERATURE (TA) TEST CONDITIONS PARAMETER High Level Input Voltage Level Input Voltage High Level Output Voltage SYMBOL IOZH IOZL Input Clamp Voltage 3.4V (Note (mA) 25oC 70oC UNITS
Level Output Voltage
0.55
0.55
High Level Input Current Level Input Current Three-State Leakage Current
-0.1 -0.5 -1.2
-1.2
Short Circuit Output Current (Note
Quiescent Supply Current,
Additional Quiescent Supply Current Input Inputs High, Unit Load NOTES:
more than output should shorted time. Test duration should exceed 100ms. Inputs that measured GND. Input Loading: inputs unit load. Unit load limit specified Static Characteristics Chart, e.g., 1.6mA 70oC.
CD74FCT564, CD74FCT574
Switching Specifications Over Operating Range 2.5ns, 50pF, Figure
AMBIENT TEMPERATURE (TA) 25oC PARAMETER Propagation Delays Clock Clock Output Disable Output Enable Output Disable Output Enable Power Dissipation Capacitance CD74FCT574 CD74FCT564 CD74FCT574 CD74FCT574 CD74FCT564 CD74FCT564 tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH (Note VOHV (Figure VOLP (Figure Typical 12.5 12.5 SYMBOL 70oC UNITS
Minimum (Valley) VOHV During Switching Other Outputs (Output Under Test Switching) Maximum (Peak) VOLP During Switching Other Outputs (Output Under Test Switching) Input Capacitance Three State Output Capacitance NOTE:
CPD, measured flip-flop, used determine dynamic power consumption. (per package) (VCC2 where: supply voltage flow through current unit load output load capacitance duty cycle input high output frequency input frequency
Prerequisite Switching
AMBIENT TEMPERATURE (TA) 25oC PARAMETER Clock Pulse Width CD74FCT574 CD74FCT564 Setup Time Data Clock Data Clock Hold Time CD74FCT574 CD74FCT564 Maximum Clock Frequency NOTE: minimum 4.5V. minimum 4.75V 70oC. Typical fMAX (Note SYMBOL 70oC UNITS
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

BiCMOS Interface Logic, Octal D-Type Flip-Flops, Three-State CD74

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