BiCMOS Interface Logic, Octal Buffers/Line Drivers, Three-State C

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BiCMOS Interface Logic, Octal Buffers/Line Drivers, Three-State C

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CD74FCT540, CD74FCT541
BiCMOS Interface Logic, Octal Buffers/Line Drivers, Three-State
CD74FCT540 CD74FCT541 octal buffers/line drivers small geometry BiCMOS technology. output stage combination bipolar CMOS transistors that limits output HIGH level diode drops below VCC. This resultant lowering output swing 3.7V) reduces power ringing source EMI) minimizes bounce ground bounce their effects during simultaneous output switching. output configuration also enhances switching speed capable sinking milliamperes. CD74FCT540 three-state buffer having active output enables. CD74FCT541 noninverting three state buffer having active output enables.
January 1997
Features
ENDE IGNS ology Techn
Buffered Inputs Typical Propagation Delay: 6.4ns 25oC, 50pF CD74FCT540 Inverting CD74FCT541 Noninverting Latchup Resistant BiCMOS Process Circuit Design Speed Bipolar FASTTM/AS/S 64mA Output Sink Current Output Voltage Swing Limited 3.7V Controlled Output Edge Rates Input/Output Isolation BiCMOS Technology with Quiescent Power
Ordering Information
PART NUMBER CD74FCT540E CD74FCT541E CD74FCT540M CD74FCT541M CD74FCT541SM TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC SSOP PKG. E20.3 E20.3 M20.3 M20.3 M20.209
NOTE: When ordering suffix packages, entire part number. suffix obtain variant tape reel.
Pinouts
CD74FCT540 (PDIP, SOIC) VIEW CD74FCT541 (PDIP, SOIC, SSOP) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis trademark Fairchild Semiconductor. Copyright Harris Corporation 1997
File Number
2383.2
CD74FCT540, CD74FCT541 Functional Diagram
TRUTH TABLE (Note INPUTS NOTE: HIGH Voltage Level Voltage Level Immaterial HIGH Impedance OUTPUTS CD74FCT540 CD74FCT541
Logic Symbol
CD74FCT540
CD74FCT541
CD74FCT540, CD74FCT541
Absolute Maximum Ratings
Supply Voltage (VCC) -0.5V Input Diode Current, (For -0.5V) -20mA Output Diode Current, (for -0.5V) -50mA Output Sink Current Output Pin, 70mA Output Source Current Output Pin, -30mA Current (ICC) 140mA Ground Current (IGND). 528mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package SSOP Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC SSOP-Lead Tips Only)
Operating Conditions
Operating Temperature Range (TA) .0oC 70oC Supply Voltage Range, .4.75V 5.25V Input Voltage, Output Voltage, Input Rise Fall Slew Rate, dt/dv. 10ns/V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications Commercial Temperature Range 70oC, 5.25V, 4.75V (Note
AMBIENT TEMPERATURE (TA) TEST CONDITIONS PARAMETER High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage High Level Input Current Level Input Current Three State Leakage Current SYMBOL IOZH IOZL Input Clamp Voltage Short Circuit Output Current (Note Quiescent Supply Current, Additional Quiescent Supply Current Input Inputs High, Unit Load NOTES: more than output should shorted time. Test duration should exceed 100ms. Inputs that measured GND. Input Loading: inputs unit load. Unit load limit specified Static Characteristics Chart, e.g., 1.6mA Max. 70oC. 3.4V (Note (mA) 4.75 5.25 4.75 5.25 25oC 0.55 -0.1 -0.5 -1.2 70oC 0.55 -1.2 UNITS
CD74FCT540, CD74FCT541
Switching Specifications Over Operating Range Series 2.5ns, 50pF, (Figure (Note
25oC PARAMETER Propagation Delays Data Outputs CD74FCT540 CD74FCT541 Output Disable Output Output Enable Output Power Dissipation Capacitance CD74FCT540 CD74FCT541 Minimum (Valley) VOHV During Switching Other Outputs (Output Under Test Switching) Maximum (Peak) VOLP During Switching Other Outputs (Output Under Test Switching) Input Capacitance Three-State Output Capacitance NOTES: 5.25V 70oC, 4.75V 70oC, CPD, measured flip-flop, used determine dynamic power consumption. (per package) (VCC2 where: supply voltage flow through current unit load output load capacitance duty cycle input high output frequency input frequency VOHV VOLP tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH (Note SYMBOL (Note 70oC UNITS
CD74FCT540, CD74FCT541
Test Circuits Waveforms
2.5ns (NOTE PULSE 50pF
SWITCH POSITION TEST tPLZ, tPZL, Open Drain tPHZ, tPZH, tPLH, tPHL SWITCH Closed Open
NOTE: Pulse Generator Pulses: Rate 1.0MHz; ZOUT 2.5ns. FIGURE TEST CIRCUIT
DEFINITIONS: Load capacitance, includes probe capacitance. Termination resistance, should equal ZOUT Pulse Generator. Input: 2.5ns (10% 90%), unless otherwise specified
ENABLE CONTROL INPUT tPZL 3.5V OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 1.5V
DISABLE 1.5V tPLZ 3.5V OUTPUT 0.3V tPHZ 0.3V OPPOSITE PHASE INPUT TRANSITION tPLH tPHL SAME PHASE INPUT TRANSITION tPLH tPHL
1.5V 1.5V 1.5V
FIGURE ENABLE DISABLE TIMING
FIGURE PROPAGATION DELAY
OTHER OUTPUTS OUTPUT UNDER TEST VOHV VOLP
NOTES: VOLP measured with respect ground reference near output under test. VOHV measured with respect VOH. Input pulses have following characteristics: 1MHz, 2.5ns, 2.5ns, skew 1ns. R.F. fixture with 700MHz design rules required. should soldered into test board bypassed with 0.1µF capacitor. Scope probes require 700MHz bandwidth. FIGURE SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

BiCMOS Interface Logic, Octal Buffers/Line Drivers, Three-State C

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