Dual D-Type Flip-Flop with Reset Positive-Edge-Triggered Harris C

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Dual D-Type Flip-Flop with Reset Positive-Edge-Triggered Harris C

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CD74AC74, CD74ACT74
Dual D-Type Flip-Flop with Reset Positive-Edge-Triggered
Harris CD74AC74 CD74ACT74 dual D-type, positive edge triggered flip-flops Harris ADVANCED CMOS technology. These flip-flops have independent DATA, SET, RESET, CLOCK inputs outputs. logic level present data input transferred output during positive going transition clock pulse. RESET independent clock accomplished level appropriate input.
September 1998
/Title (CD74 AC74, CD74 ACT74 /Subject (Dual DType FlipFlop with Reset PositiveEdgeTriggered) /Autho /Keywords (Harris Semiconductor, Advan CMOS Harris Semiconductor, Advan
Features
Buffered Inputs Typical Propagation Delay (AC00) 4.9ns 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Lachup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC74E CD74ACT74E CD74AC74EX CD74ACT74EX CD74AC74M CD74ACT74M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information. TEMP. RANGE (oC) PACKAGE PDIP PDIP PDIP PDIP SOIC SOIC PKG. E14.3 E14.3 E14.3 E14.3 M14.15 M14.15
Pinout
CD74AC74, CD74ACT74 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright Harris Corporation 1998
File Number
1881.1
CD74AC74, CD74ACT74 Functional Diagram
TRUTH TABLE INPUTS NOTES: High level (steady state), level (steady state), Don't care, Transition from High level. level before indicated input conditions were established. This configuration nonstable, that will persist when reset inputs return their inactive (high) level. RESET OUTPUTS
(Note (Note
CD74AC74, CD74ACT74
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC74, CD74ACT74
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current, TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current, Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT UNIT LOAD 0.53 0.58
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD74AC74, CD74ACT74
Prerequisite Switching Function
-40oC 85oC PARAMETER TYPES Data Setup Time (Note (Note Hold Time Removal Time, tREM Pulse Width, Pulse Width, Frequency fMAX TYPES Data Setup Time Hold Time Removal Time, Pulse Width, Pulse Width, Frequency NOTES: 3.3V 3.6V. 4.5V. tREM fMAX (Note SYMBOL -55oC 125oC UNITS
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, tPLH, tPHL (Note (Note 12.7 SYMBOL -55oC 125oC UNITS
CD74AC74, CD74ACT74
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Propagation Delay, SYMBOL tPLH tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Propagation Delay, tPHL tPLH tPLH tPHL Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption flip-flop. CPDVCC2 (CLVCC2 where input frequency, output frequency, output load capacitance, supply voltage. (Note (Note 10.5 11.4 11.5 12.5 (Note (Continued) -55oC 125oC 13.4 14.6 10.4 14.7 10.5 16.1 11.5 UNITS
-40oC 85oC
INPUT LEVEL INPUT LEVEL tPHL tPLH INPUT tPLH tREM
FIGURE
FIGURE
INPUT LEVEL INPUT LEVEL
tSU(L)
tH(L)
tSU(H)
tH(H)
FIGURE
CD74AC74, CD74ACT74
OUTPUT (NOTE) OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, CD74AC Input Level Input Switching Voltage, Output Switching Voltage, CD74ACT 1.5V
FIGURE PROPAGATION DELAY TIMES
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

Dual D-Type Flip-Flop with Reset Positive-Edge-Triggered Harris C

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