BiCMOS Interface Logic, Octal-Bus Tranceivers, Three-State CD54/7

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BiCMOS Interface Logic, Octal-Bus Tranceivers, Three-State CD54/7

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CD54FCT245, CD74FCT245
BiCMOS Interface Logic, Octal-Bus Tranceivers, Three-State
CD54/74FCT245 octal transceiver uses small geometry BiCMOS technology. output stage combination bipolar CMOS transistors that limits output HIGH level diode drops below VCC. This resultant lowering output swing 3.7V) reduces power ringing source EMI) minimizes bounce ground bounce their effects during simultaneous output switching. output configuration also enhances switching speed capable sinking 48mA 64mA. CD54/74FCT245 noninverting, three-state, bidirectional transceiver/buffer intended two-way transmission from"A" bus. logic level present Direction Input (DIR) determines data direction. When Output Enable input HIGH, outputs high impedance state.
January 1997 Revised October 1999
Features
Buffered Inputs Typical Propagation Delay: 5.0ns 25oC Noninverting Latchup Resistant BiCMOS Process Circuit Design Speed Bipolar FASTTM/AS/S 64mA Output Sink Current Series) 48mA Output Sink Current Series) Output Voltage Swing Limited 3.7V Controlled Output Edge Rates Input/Output Isolation BiCMOS Technology with Quiescent Power
Ordering Information
PART NUMBER CD74FCT245E CD74FCT245M CD54FCT245E TEMP. RANGE (oC) PACKAGE PDIP SOIC PDIP PKG. E20.3 M20.3 E20.3
NOTE: When ordering suffix packages, entire part number. suffix obtain variant tape reel.
Pinout
CD54FCT245, CD74FCT245 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis trademark Fairchild Semiconductor. Copyright 1999, Texas Instruments Incorporated
CD54FCT245, CD74FCT245 Functional Diagram
TRUTH TABLE (NOTE CONTROL INPUTS NOTES: High Voltage Level Voltage Level Irrelevant prevent excess currents High-Z (isolation) modes, terminals should terminated with resistors. OPERATION Data Data Isolation
Logic Symbol
CD74FCT245, CD54FCT245
3EN1 3EN1
CD54FCT245, CD74FCT245
Absolute Maximum Ratings
Supply Voltage (VCC) -0.5V 6.0V Input Diode Current, (for -0.5V) -20mA Output Diode Current, (for -0.5V) -50mA Output Sink Current Output Pin, 70mA Output Source Current Output Pin, -30mA Current (ICC) 140mA Ground Current (IGND). 528mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Operating Temperature Range (TA) -55oC 125oC Supply Voltage Range, CD74 Series, 70oC .4.75V 5.25V CD54 Series,TA -55oC 125oC .4.5V 5.5V Input Voltage, Output Voltage, Input Rise Fall Slew Rate, dt/dv. 10ns/V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: calculated accordance with JESD
Electrical Specifications 74FCT Commercial Temperature Range 70oC, 5.25V, 4.75V
54FCT Extended Industrial Temperature Range -55oC 125oC; 5.5V, 4.5V TEST CONDITIONS PARAMETER High Level Input Voltage Level Input Voltage High Level Output Voltage SYMBOL Level Output Voltage High Level Input Current Level Input Current Three-State Leakage Current Short Circuit Output Current (Note Input Clamp Voltage Quiescent Supply Current, Additional Quiescent Supply Current Input Inputs High, Unit Load NOTES: more than output should shorted time. Test duration should exceed 100ms. Inputs that measured GND. Input Loading: inputs unit load. Unit load limit specified Static Characteristics Chart, e.g., 1.6mA 70oC. IOZH IOZL 3.4V (Note (mA) AMBIENT TEMPERATURE (TA) 25oC 0.55 0.55 -0.1 -0.5 70oC 0.55 -55oC 125oC 0.55 UNITS
-1.2
-1.2
-1.2
CD54FCT245, CD74FCT245
Switching Specifications 2.5ns, 50pF, Figure
AMBIENT TEMPERATURE (TA) 25oC PARAMETER Propagation Delays Data Outputs) Output Enable Output Output Disable Output Power Dissipation Capacitance (Valley) VOHV During Switching Other Outputs (Output Under Test Switching) (Peak) VOLP During Switching Other Outputs (Output Under Test Switching) Input Capacitance Input/Output Capacitance NOTES: 5.5V, 4.5V. 5.25V 70oC, 4.75V 70oC, CPD, measured function, used determine dynamic power consumption. (per package) (VCC2 where: supply voltage flow through current unit load output load capacitance duty cycle input high output frequency input frequency SYMBOL tPLH, tPHL tPZL, tPZH tPLZ, tPHZ VOHV 70oC -55oC 125oC UNITS
VOLP
CI/O
CD54FCT245, CD74FCT245 Test Circuits Waveforms
2.5ns (NOTE PULSE 50pF
SWITCH POSITION TEST tPLZ, tPZL, Open Drain tPHZ, tPZH, tPLH, tPHL SWITCH Closed Open
NOTE: Pulse Generator Pulses: Rate 1.0MHz; ZOUT 2.5ns. FIGURE TEST CIRCUIT
DEFINITIONS: Load capacitance, includes probe capacitance. Termination resistance, should equal ZOUT Pulse Generator. Input: 2.5ns (10% 90%), unless otherwise specified
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL tREM
1.5V 1.5V 1.5V
LOW-HIGH-LOW PULSE
1.5V
SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 1.5V HIGH-LOW-HIGH PULSE
1.5V
FIGURE SETUP, HOLD, RELEASE TIMING
FIGURE PULSE WIDTH
ENABLE CONTROL INPUT tPZL 3.5V OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 1.5V
DISABLE 1.5V tPLZ 3.5V OUTPUT 0.3V tPHZ 0.3V OPPOSITE PHASE INPUT TRANSITION tPLH tPHL SAME PHASE INPUT TRANSITION tPLH tPHL
1.5V 1.5V 1.5V
FIGURE ENABLE DISABLE TIMING
FIGURE PROPAGATION DELAY
Test Circuits Waveforms
(Continued)
OTHER OUTPUTS OUTPUT UNDER TEST VOHV VOLP
NOTES: VOLP measured with respect ground reference near output under test. VOHV measured with respect VOH. Input pulses have following characteristics: 1MHz, 2.5ns, 2.5ns, skew 1ns. R.F. fixture with 700MHz design rules required. should soldered into test board bypassed with 0.1µF capacitor. Scope probes require 700MHz bandwidth. FIGURE SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

BiCMOS Interface Logic, Octal-Bus Tranceivers, Three-State CD54/7

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