October 1987 Revised January 1999 CD4071BC CD4081BC Quad 2-Input

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October 1987 Revised January 1999 CD4071BC CD4081BC Quad 2-Input

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CD4071BC CD4081BC Quad 2-Input Buffered Series Gate Quad 2-Input Buffered Series Gate
October 1987 Revised January 1999
CD4071BC CD4081BC Quad 2-Input Buffered Series Gate Quad 2-Input Buffered Series Gate
CD4071BC CD4081BC quad gates monolithic complementary (CMOS) integrated circuits constructed with P-channel enhancement mode transistors. They have equal source sink current capabilities conform standard series output drive. devices also have buffered outputs which improve transfer characteristics providing very high gain. inputs protected against static discharge with diodes VSS.
Features
power compatibility: driving driving 74LS 5V-10V-15V parametric ratings Symmetrical output characteristics Maximum input leakage over full temperature range
Ordering Code:
Order Number CD4071BCM CD4071BCN CD4081BCM CD4081BCN Package Number M14A N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
Connection Diagrams
Assignments SOIC CD4071B CD4081B
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View
1999 Fairchild Semiconductor Corporation
DS005977.prf
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CD4071BC CD4081BC
Schematic Diagrams CD4071B
device shown
J=A+B Logical HIGH Logical *All inputs protected standard CMOS protection circuit.
CD4081B
device shown
Logical HIGH Logical inputs protected standard CMOS protection circuit.
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CD4071BC CD4081BC
Absolute Maximum Ratings(Note
(Note Voltage Power Dissipation (PD) Dual-In-Line Small Outline Range Storage Temperature (TS) Lead Temperature (TL) (Soldering, seconds) 260°C (Note -0.5 -65°C +150°C -0.5V +0.5V
Recommended Operating Conditions
Operating Range (VDD Operating Temperature Range (TA) CD4071BC, CD4081BC -40°C +85°C
Note "Absolute Maximum Ratings" those values beyond which safety device cannot guaranteed. Except "Operating Temperature Range" they meant imply that devices should operated these limits. table "Electrical Characteristics" provides conditions actual device operation. Note voltages measured with respect unless otherwise specified.
Electrical Characteristics
CD4071BC/CD4081BC Symbol Parameter Quiescent Device Current Level Output Voltage HIGH Level Output Voltage Level Input Voltage HIGH Level Input Voltage Level Output Current (Note HIGH Level Output Current (Note Input Current
Conditions
-40°C 0.05
+25°C 0.004 0.005 0.006 4.95 9.95 14.95 11.0 0.44 -0.44 -1.1 -3.0 0.88 2.25 -0.88 -2.25 -8.8 -10-5 10-5 -0.30 0.30 0.05 0.05 0.05
+85°C 0.05 0.05 0.05 4.95 9.95 14.95 11.0 0.36 -0.36 -0.9 -2.4 -1.0
Units
|IO| 4.95 |IO| 9.95 14.95
0.05 0.05
0.5V 10V, 1.0V 15V, 1.5V 4.5V 10V, 9.0V 15V, 13.5V 0.4V 10V, 0.5V 15V, 1.5V 4.6V 10V, 9.5V 15V, 13.5V 15V, 15V, 11.0 0.52 -0.52 -1.3 -3.6
-0.30 0.30
Note tested output time.
Electrical Characteristics
tPHL Propagation Delay Time, HIGH-to-LOW Level tPLH Propagation Delay Time, LOW-to-HIGH Level tTHL, tTLH Transition Time
(Note
Units
CD4071BC 25°C, Input Typical temperature coefficient 0.3%/°C Symbol Parameter Conditions Average Input Capacitance Power Dissipation Capacity Input Gate
Note Parameters guaranteed correlated testing.
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CD4071BC CD4081BC
Electrical Characteristics
Symbol tPHL Parameter Propagation Delay Time, HIGH-to-LOW Level tPLH Propagation Delay Time, LOW-to-HIGH Level tTHL, tTLH Transition Time
(Note
Conditions Units
CD4081BC 25°C, Input Typical temperature coefficient 0.3%/°C Average Input Capacitance Power Dissipation Capacity Input Gate
Note Parameters guaranteed correlated testing.
Typical Performance Characteristics
Typical Transfer Characteristics Typical Transfer Characteristics
Typical Transfer Characteristics
Typical Transfer Characteristics
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CD4071BC CD4081BC
Typical Performance Characteristics
(Continued)
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CD4071BC CD4081BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A
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CD4071BC CD4081BC Quad 2-Input Buffered Series Gate Quad 2-Input Buffered Series Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices systems device system whose failure perform reawhich, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose failure device system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury www.fairchildsemi.com user.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.

October 1987 Revised January 1999 CD4071BC CD4081BC Quad 2-Input

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