General Purpose High Current Transistor Arrays CA3081 CA3082 cons

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General Purpose High Current Transistor Arrays CA3081 CA3082 cons

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CA3081, CA3082
General Purpose High Current Transistor Arrays
CA3081 CA3082 consist seven high current 100mA) silicon transistors common monolithic substrate. CA3081 connected common emitter configuration CA3082 connected common collector configuration. CA3081 CA3082 capable directly driving seven segment displays, light emitting diode (LED) displays. These types also well suited variety other drive applications, including relay control thyristor firing.
Features
CA3081 Common Emitter Array CA3082 Common Collector Array Directly Drive Seven Segment Incandescent Displays Light Emitting Diode (LED) Display Transistors Permit Wide Range Applications Either Common Emitter (CA3081) Common Collector (CA3082) Configuration High 100mA (Max) VCESAT 50mA) 0.4V (Typ)
Ordering Information
PART NUMBER (BRAND) CA3081 CA3081F CA3081M (3081) CA3082 CA3082M (3082) CA3082M96 (3082) TEMP. RANGE (oC) PACKAGE PDIP CERDIP SOIC PDIP SOIC SOIC Tape Reel PKG. E16.3 F16.3 M16.15 E16.3 M16.15 M16.15
Applications
Drivers Incandescent Display Devices Displays Relay Control Thyristor Firing
Pinouts
CA3081 COMMON EMITTER CONFIGURATION (PDIP, CERDIP, SOIC) VIEW
SUBSTRATE
CA3082 COMMON COLLECTOR CONFIGURATION (PDIP, SOIC) VIEW
SUBSTRATE
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Copyright Intersil Corporation 1999
CA3081, CA3082
Absolute Maximum Ratings 25oC
Collector-to-Emitter Voltage (VCEO) .16V Collector-to-Base Voltage (VCBO) Collector-to-Substrate Voltage (VCIO Note Emitter-to-Base Voltage (VEBO) Collector Current (IC) 100mA Base Current (IB) 20mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) CERDIP Package. PDIP Package SOIC Package Maximum Power Dissipation (Any Transistor) 500mW Maximum Junction Temperature (Ceramic Package) .175oC Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range -55oC 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: collector each transistor CA3081 CA3082 isolated from substrate integral diode. substrate must connected voltage which more negative than collector voltage order maintain isolation between transistors provide normal transistor action. avoid undesired coupling between transistors, substrate terminal should maintained either signal (AC) ground. suitable bypass capacitor used establish signal ground. measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER
Equipment Design 25oC SYMBOL V(BR)CBO V(BR)CIO V(BR)CEO V(BR)EBO VBESAT VCESAT 30mA, 50mA, 50mA, ICEO ICBO 10V, 10V, 0.27 TEST CONDITIONS 500µA, 500µA, 1mA, 500µA 0.5V, 30mA 0.8V, 50mA 30mA, 0.87 UNITS
Collector-to-Base Breakdown Voltage Collector-to-Substrate Breakdown Voltage Collector-to-Emitter Breakdown Voltage Emitter-to-Base Breakdown Voltage Forward Current Transfer Ratio
Base-to-Emitter Saturation Voltage (Figure Collector-to-Emitter Saturation Voltage CA3081, CA3082 CA3081 (Figure CA3082 (Figure Collector Cutoff Current Collector Cutoff Current
Typical Read Driver Applications
CA3082 (COMMON COLLECTOR) (NOTE) LIGHT EMITTING DIODE (LED) 40736R SEGMENT INCANDESCENT DISPLAY (DR2000 SERIES EQUIVALENT) FROM DECODER CA3081 (COMMON EMITTER)
NOTE:
Resistance determined relationship:
Where: Input Pulse Voltage Forward Voltage Drop Across Diode
FIGURE SCHEMATIC DIAGRAM SHOWING TRANSISTOR CA3081 DRIVING SEGMENT INCANDESCENT DISPLAY
FIGURE SCHEMATIC DIAGRAM SHOWING TRANSISTOR CA3082 DRIVING LIGHT EMITTING DIODE (LED)
CA3081, CA3082 Typical Performance Curves
BASE-TO-EMITTER SATURATION VOLTAGE FORWARD CURRENT TRANSFER RATIO (hFE) 25oC 25oC
70oC
COLLECTOR CURRENT (mA)
COLLECTOR CURRENT (mA)
FIGURE FORWARD CURRENT TRANSFER RATIO COLLECTOR CURRENT
25oC COLLECTOR-TO-EMITTER SATURATION VOLTAGE
FIGURE BASE-TO-EMITTER SATURATION VOLTAGE COLLECTOR CURRENT
COLLECTOR-TO-EMITTER SATURATION VOLTAGE MAXIMUM 70oC
MAXIMUM
TYPICAL
TYPICAL
COLLECTOR CURRENT (mA)
COLLECTOR CURRENT (mA)
FIGURE COLLECTOR-TO-EMITTER SATURATION VOLTAGE COLLECTOR CURRENT
FIGURE COLLECTOR-TO-EMITTER SATURATION VOLTAGE COLLECTOR CURRENT
CA3081, CA3082 Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E16.3 (JEDEC MS-001-BB ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 2.93 10.92 3.81
CA3081, CA3082 Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M16.15 (JEDEC MS-012-AC ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 9.80 3.80 1.75 0.25 0.51 0.25 10.00 4.00 NOTES Rev. 12/93
0.0532 0.0040 0.013 0.0075 0.3859 0.1497
0.0688 0.0098 0.020 0.0098 0.3937 0.1574
0.10(0.004)
0.25(0.010)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
CA3081, CA3082 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES Rev. 4/94
eA/2
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 7.62 3.81 3.18 0.38 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension This dimension allows off-center lid, meniscus, glass overrun. Dimension shall measured from seating plane base plane. Measure dimension four corners. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
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Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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