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AlchemySolutions Au1000TM, Au1100and Au1500Processors SDRAM Performance Application Note
Revision: Issue Date: April 2003
Revision Issue Date October 2002 April 2003 Earlier version Removed references four 8-bit wide SDRAM devices Added Alchemylogo coversheet Description Changes
2002, 2003 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Contacts www.amd.com pcs.support@amd.com Trademarks AMD, Arrow logo, combinations thereof, Au1000, Au1100, Au1500, Alchemy trademarks Advanced Micro Devices, Inc. Other product names used this publication identification purposes only trademarks their respective companies.
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SDRAM Performance Au1000TM, Au1100and Au1500Processors
Introduction
Au1000TM, Au1100and Au1500(Au1x00) processors each feature integrated, high-performance SDRAM controller connecting 32-bit wide external SDRAM memory. This document describes performance characteristics SDRAM controller techniques optimizing SDRAM performance.
SDRAM Controller Overview
SDRAM controller Au1x00 processor supports three ranks 32-bit wide SDRAM. rank physical grouping SDRAM devices, tied same chip select. term `rank' used distinguish physical grouping SDRAM chips from internal banks SDRAM chip. Each rank independently programmed with size, column size, bank size, RAS, other timing values further described data books). SDRAM data interface 32-bits wide supports various arrangements SDRAM devices: 32-bit wide SDRAM device 16-bit wide SDRAM devices SDRAM controller supports maximum loads, physical arrangement SDRAM limits number devices that installed system. SDRAM interface operates one-half Au1x00 internal system clock, maximum frequency MHz. Utilizing 396-MHz Au1x00 system example, core runs (sys_cpupll 33), system operates one-half core frequency (sys_powerctrl[SD]=00), thus SDRAM interface operates MHz. NOTE: Au1x00 processor rated MHz, SDRAM clock possible, this frequency within operating capability controller commodity desktop SDRAM (133-MHz PC133). core system operate higher frequencies than SDRAM interface; result, Au1x00 processor capable saturating SDRAM interface both reads writes from/to SDRAM. Thus, with properly configured SDRAM interface, actual, realized SDRAM throughput limited SDRAM controller; instead highly dependent upon run-time aspects software applications running system.
SDRAM Performance
performance SDRAM interface measured throughput, which amount data that transferred from SDRAM given time period. maximum throughput SDRAM controller approximated this equation: SDCLK ((RR (2+CPR)) CPW)) Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
where throughput (bytes/second) SDCLK SDRAM clock frequency (cycles/second) number bytes transfer, (bytes/transfer) read ratio; percentage accesses that reads, expressed decimal, e.g. 0.75 must equal 1.0) cycles read bytes (cycles/transfer) write ratio; percentage accesses that writes, expressed decimal, e.g. 0.25 must equal 1.0) cycles write bytes (cycles/transfer)
This equation approximation since actual number bytes transfer (BPT) to/from SDRAM always (8-word burst), because read ratio (RR) write ratio (WR) vary greatly depending upon software applications running system. Heuristically, read accesses (instruction fetches data loads) out-number write accesses (data stores) three one. Furthermore, this approximation does take into account other aspects SDRAM, such refresh cycles open banks. Nonetheless, approximate SDRAM throughput example 396-MHz Au1x00 system utilizing SDRAM with latency becomes: 99MHz ((0.75 (2+12)) (0.25 10)) 248.9MB/s read ratio 0.75 write ratio 0.25 reflect that reads heuristically out-number writes three-to-one. cycles read cycle activate command cycle cycle read command 1cycle latency cycles burst words cycles synchronizing internal system bus). cycles write cycle activate command cycle cycles burst words). SDRAM throughput approximation equation tends yield realistic upper-bound SDRAM throughput. profiling application(s) running Au1x00 system, obtain more accurate values read ratio write ratio average number bytes transfer which turn will yield closer approximation actual SDRAM throughput. Au1x00-based design, following items tuned (both hardware software decisions) achieve best overall SDRAM throughput: SDRAM clock latency Refreshes Access pattern
practice, SDRAM throughput influenced (both positively negatively) software Application Note
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SDRAM Performance Au1000TM, Au1100and Au1500Processors
running system. Software initiates accesses SDRAM requesting instruction fetches, data loads stores, activity. access pattern generated software determines efficiently SDRAM interface utilized transfer data from memory, ultimately throughput SDRAM. examples that follow, 99-MHz SDRAM clock SDRAM latency assumed unless otherwise stated.
SDRAM Clock
SDRAM clock dominating factor determining SDRAM throughput. Simply stated, higher frequency SDRAM clock, higher SDRAM throughput. Since SDRAM clock frequency derived from core frequency, process selecting specific speed-grade Au1x00 device should take into account resulting SDRAM clock frequency. Table "Au1 Core SDRAM frequencies" page lists some common core SDRAM frequencies.
SDRAM Latency
SDRAM latency determines number cycles until data read from SDRAM. latency varies depending upon SDRAM device, usually either SDRAM device with latency will yield better throughput than SDRAM with latency 396-MHz Au1x00 system utilizing SDRAM with latency approximate throughput becomes: 99MHz ((0.75 (2+13)) (0.25 10)) 237.6MB/s Utilizing SDRAM reduces throughput 11.3MB/s relative SDRAM. Clearly utilizing SDRAM with latency desirable.
SDRAM Refreshes
case dynamic RAM, SDRAM requires periodic refreshes ensure integrity data arrays. During SDRAM refresh, accesses core stalled until refresh completes. result, actual number transfers that occur SDRAM reduced, which turn reduces overall SDRAM throughput. example, many SDRAMs require periodic refresh rows every milliseconds. SDRAM devices with 4096 rows, this equates refresh cycle every 15.7 microseconds 63694 refreshes second. 100-MHz SDRAM devices, auto refresh phase typically requires about nine cycles (Trp Trc); thus, 63694 573246 SDRAM clock cycles consumed each second refreshes, data accesses. While number small fraction available 99-MHz SDRAM clock cycles (0.58%), does represent throughput reduction nearly 1.5MBytes/second.
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Refresh cycles have another adverse effect: SDRAM banks must closed prior refresh cycle. result, next read write SDRAM must first re-open bank which increases number cycles necessary read write. With refresh interval 15.7microseconds, only 1570 SDRAM clocks occur between refreshes (15.7e-6 10.0e-9), which permits maximum burst reads between refreshes before banks closed again next refresh. Clearly, refresh interval that conservative (shorter than necessary) only reduces SDRAM throughput with additional benefit.
SDRAM Access Pattern
SDRAM clock, latency refresh interval "static" variables that optimized according SDRAM devices ensure efficient operation. However, "dynamic" variable, software, that influences, both positively negatively, actual, realized SDRAM throughput. This "dynamic" variable access pattern created software during run-time, generally classified follows: burst accesses single beat accesses locality references
access patterns direct result software running system.
3.4.1 Burst Accesses
SDRAM accesses require cycles setup time before data accessed. maximize throughput, setup time needs minimized. Since steps access SDRAM pre-determined, setup time [typically] reduced, amortized minimize impact. Burst accesses amortize setup time reading/writing more data same, fixed setup time. Burst accesses initiated instruction cache loads, data cache loads, data cache line cast-out, write-buffer, engines. core utilizes word (32-byte) cache lines, writebuffer burst words (32-bytes), engines burst well. SDRAM throughput approximation equation intentionally utilizes 32-byte transfers match core cache line size; after all, majority SDRAM accesses initiated caches. 8-word read burst SDRAM that requires cycles, efficiency access bytes cycles 2.67 bytes/cycle. ideal maximum sustain bytes/cycle 32-bit SDRAM interface, this possible non-zero setup time required SDRAM accesses. Only system where majority SDRAM accesses burst accesses actual SDRAM throughput approach maximum.
Application Note
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SDRAM Performance Au1000TM, Au1100and Au1500Processors
3.4.2 Single-Beat Accesses
Single-beat accesses occur when only single memory location accessed SDRAM access. such, SDRAM setup time dominates access. very nature single-beat access, less data read written which lowers overall SDRAM throughput. single word read access SDRAM, cycles necessary which yields bytes cycles 0.66 bytes/cycle. Compared word read burst access, single-beat access nearly four times less efficient. Single-beat accesses degrade overall SDRAM throughput. single-beat accesses occur initiated data cache write misses (because core uses read-allocate cache policy) non-cached reads writes. access write, access travels through write-buffer SDRAM. Performance features within write-buffer reduce inefficiency single-beat access. write-buffer both merging gathering. Merging delays writes same word address until word address presented write-buffer. Gathering bundles sequential word addresses into burst access SDRAM. description Au1x00 data books ("2.3 Write Buffer") further details. non-cacheable accesses take advantage write-buffer features, write must marked with encoding (see "2.2.4 Cache Coherency Attributes" data books). Cache-able write accesses that miss data cache automatically marked merge-able gatherable write-buffer. access non-cached read, access least efficient access possible.
3.4.3 Locality References
phrase "locality reference" means that related instructions and/or data physically located near another memory. phenomenon "locality reference" drove creation instruction data caches that reaped huge overall system performance increases. example, subroutine array data merely sequence items, physically located adjacent memory addresses. subroutine fetches instruction from memory address instruction cache fetches instruction from memory, several more subsequent instructions into cache. Then when subroutine requests instruction from address (and there high probability that this will case), instruction cache already instruction eliminates need access memory. same locality reference phenomenon applies equally memory cells; cell just accessed, then there high probability that cell will next. This mirrors behavior instruction data caches reason SDRAMs have burst capability.
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
3.4.3.1 SDRAM Open Bank SDRAMs take advantage locality reference phenomenon with "open bank policy". open bank policy allows SDRAM bank remain open after access reduce setup time needed subsequent access same within open bank. reducing setup time, efficiency SDRAM interface increases throughput increases well. Au1x00 SDRAM controller ability keep banks open rank, total banks open time. When access SDRAM occurs, controller automatically leaves bank open. access open bank occurs same row, SDRAM controller simply asserts CAS# completes access. This removes cycles from access permits faster accesses frequently accessed banks. series 8-word burst accesses same bank, number cycles required cycles. efficiency access bytes cycles bytes/cycle, improvement over 2.67 bytes/cycle non-open bank burst access. take explicit advantage SDRAM open bank feature, configuration SDRAM needs taken into consideration. direct result locality reference phenomenon, open bank feature best exploited with large size. Various SDRAM configurations provided Table illustrate effect SDRAM configuration size.
Table SDRAM Device Configurations
SDRAM Device Density 16Mb (2MB) 512Kbit banks 64Mb (8MB) 1Mbit banks 64Mb (8MB) 512Kbit banks 64Mb (8MB) 512Kbit banks 128Mb (16MB) 2Mbit banks 128Mb (16MB) 1Mbit banks 256Mb (32MB) 4Mbit banks 256Mb (32MB) 2Mbit banks Bits BS=1,RS=11,CS=8 BS=2,RS=12,CS=8 BS=2,RS=12,CS=7 BS=2,RS=11,CS=8 BS=2,RS=12,CS=9 BS=2,RS=12,CS=8 BS=2,RS=13,CS=9 BS=2,RS=13,CS=8 Rank Configuration (Total Size) (4MB) (16MB) (8MB) (8MB) (32MB) (16MB) (64MB) (32MB) Bank Size 16MB Size 512B
last columns yield effective bank size given SDRAM configuration. Software take advantage both bank size size improve SDRAM throughput. Au1x00 SDRAM controller keep four banks open simultaneously rank. take advantage this, software should align program code data SDRAM bank boundaries. With this Application Note
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SDRAM Performance Au1000TM, Au1100and Au1500Processors
approach, instructions data reside different banks allowing SDRAM controller keep banks open simultaneously, thus improving access time these items. Since controller maintain four open banks rank, software should consider partitioning instruction data sets further align many available SDRAM banks possible. (For example, program code, stack, heap, global data, network buffers, disk buffers candidates aligning SDRAM bank boundary). larger size, better likely utilization SDRAM open bank feature-a direct result locality reference phenomenon. Software should group commonly accessed items (such instructions, data sets stack) together, then align individual groups separate SDRAM boundaries. linker used place various program sections RAM. Most linkers accept directives indicating alignment various sections; changing alignments linker scripts, possible take advantage SDRAM open bank open features. Fortunately most software systems, memory managed pages result typical MMU/TLB page size), these pages always aligned boundaries. result, memory pages already properly aligned take advantage SDRAM open bank feature. locality reference phenomenon improves SDRAM throughput ways: permits caches initiate burst accesses, SDRAM open-bank policy permits reduced access time adjacent items same SDRAM bank. 3.4.3.2 Back Back Accesses interaction various SDRAM commands (ACTIVATE, PRECHARGE, AUTOREFRESH) with read write cycles also negatively impacts SDRAM open bank policy. Read write accesses rows currently open bank must first close (PRECHARGE command) before opening row. additional SDRAM clock cycles needed close row, thus reducing SDRAM throughput.
SDRAM Performance Checklist
following items serve guideline optimizing SDRAM interface Au1x00-based design. Example SDRAM configurations provided this application note. speed-rating Au1x00 processor determines SDRAM clock frequency. Ensure selected speed-rating provide anticipated SDRAM throughput intended application. Software must program sys_cpupll sys_powerctrl[SD] appropriately that both core SDRAM interface operate desired frequencies.
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Latency rating SDRAM impacts SDRAM throughput. Choose SDRAM device with small latency, preferably Software must program SDRAM refresh interval timer register mem_sdrefcfg register with optimal value SDRAM devices use. refresh interval that conservative (shorter than necessary) only reduces SDRAM throughput with additional benefit. Software must program SDRAM controller configuration registers with optimal values. exact values dependent upon SDRAM clock frequency devices use. Software must program SDRAM MODE register with appropriate information. Specifically burst type length, latency must match value SDRAM controller. Software should utilize cache-able memory take advantage SDRAM burst accesses. core initiates cache-able accesses KSEG0 region KUSEG, KSEG2 KSEG3 regions with encoding TLB. Software should take advantage write-buffer gathering coalesce single-beat writes into burst transfers. non-cacheable spaces, encoding enables write-buffer gathering. Cache-able write accesses that miss data cache automatically marked gatherable write-buffer. Software should utilize coherency model core. doing peripheral transfers serviced data cache; thus preventing from accessing SDRAM unnecessarily thus providing more SDRAM throughput core. Software should take advantage SDRAM open-bank policy locating code, data, etc. separate SDRAM bank boundaries.
SDRAM Controller Configuration
each Au1x00-based design, SDRAM controller configuration dependent upon SDRAM devices SDRAM clock. SDRAM configuration essentially unique each design must developed examining SDRAM data sheets. Table correlates SDRAM device data sheet values with SDRAM controller fields.
Table SDRAM Timing Parameters
Au1x00 SDRAM Controller Field Tras Tmrd SDRAM Data Sheet Interpretation ACTIVATE PRECHARGE time MODE Register write ACTIVATE time Last DATA-IN PRECHARGE time
Application Note
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SDRAM Performance Au1000TM, Au1100and Au1500Processors Table SDRAM Timing Parameters
Au1x00 SDRAM Controller Field Trcd
SDRAM Data Sheet Interpretation PRECHARGE ACTIVATE time ACTIVATE READ/WRITE time REFRESH ACTIVATE time
When examining timing values specified SDRAM data sheets, many values specified nanoseconds. thus important understand relationship between SDRAM clock (which SDRAM controller uses above mentioned fields) nanoseconds. SDRAM interface clock function core frequency. SDRAM clock frequency determined value written sys_cpupll sys_powerctrl[SD]. SDRAM clock frequency core frequency (sys_cpull 12MHz) divided system divisor (sys_powerctrl[SD]) divided again Table lists common operating frequencies resulting SDRAM clock frequency.
Table Core SDRAM frequencies
sys_cpupll sys_powerctrl[SD] Core Frequency Au1x00 System Frequency SDRAM Frequency SDRAM Clock Period 10.10 12.34 15.15 20.83
important value when establishing SDRAM controller value SDRAM clock period: values provided SDRAM controller specified multiples SDRAM clocks. example, system with 66MHz SDRAM clock, SDRAM device which 65ns timing requirement given timing parameter, then number SDRAM clocks needed meet this timing parameter (65ns 15.15ns 4.29 rounded next clock variety SDRAM devices work with Au1x00 SDRAM controller example configurations provided here reference.
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
uPD45128163G5-A80-9JF
uPD45128163G5-A80-9JF 16MB devices arranged 2Mbit banks with latency MHz. These devices featured Pb1000 evaluation platform (Au1000 processor).
Table uPD45128163G5-A80-9JF
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd LTMOD Trpm Tras Tmrd Trcd Name Value 0x00552229 0100 0x66000C24 0110 0xC24 0x00000023 Latency Sequential Wrap Type Burst (tRC1) data sheet specs 70ns from mem_sdmode Enable refresh (tREF) 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 48ns (tRSC) data sheet specs clocks (tDPL) data sheet specs (tRP) data sheet specs 20ns (tRCD) data sheet specs 20ns Latency Description
Application Note
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April 2003
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Micron 48LC8M16A2-7E
Micron 48LC8M16A2-7E 16MB devices arranged 2Mbit banks with latency MHz. These devices featured Pb1500 evaluation platform (Au1500 processor).
Table Micron 48LC8M16A2-7E
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd OpMode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x00551AA9 0011 0x66000C24 0110 0xC24 0x00000023 Bursts Normal Latency Sequential bursts Burst (tRFC) data sheet specs 66ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 37ns (tMRD) data sheet specs clocks (tWR) data sheet specs clock (tRP) data sheet specs 15ns (tRCD) data sheet specs 15ns Latency Description
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Samsung K4S28163LD-RF75
Samsung K4S28163LD-RF75 16MB devices arranged 2Mbit banks with latency MHz. These devices featured Pb1100 evaluation platform (Au1100 processor).
Table Samsung K4S28163LD-RF75
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd Test Mode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x00552229 0100 0x66000C24 0110 0xC24 0x00000023 Bursts Mode Register Latency Sequential bursts Burst (tRC) data sheet specs 65ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 45ns (MRS) data sheet specs clocks (tRDL) data sheet specs 10ns (tRP) data sheet specs 20ns (tRCD) data sheet specs 20ns Latency Description
Application Note
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April 2003
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Toshiba TC59SM816CFTL-70
Toshiba TC59SM816CFTL-70 32MB devices arranged 4Mbit banks with latency MHz. These devices featured Mobile Reference Design (Hydrogen).
Table Toshiba TC59SM816CFTL-70
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd Burst Mode Test Mode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x00591A29 0011 0x6600060A 0101 0x60A 0x00000023 Bursts Normal Latency Sequential bursts Burst (tRC) data sheet specs 56ns from mem_sdmode Enable Refresh (tREF) 64ms 8192rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 40ns (tRSC) data sheet specs 14ns (tWR) data sheet specs (tRP) data sheet specs 15ns (tRCD) data sheet specs 15ns Latency Description
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Samsung K4S281632D-TC/L75
Samsung K4S281632D-TC/L75 32MB devices arranged 2Mbit banks with latency MHz. These devices featured Au1x00/Db1x00 evaluation platforms.
Table Samsung K4S281632D-TC/L75
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd Test Mode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x005522AA 0100 0x66000C24 0110 0xC24 0x00000033 Bursts Mode Register Latency Sequential bursts Burst (tRC) data sheet specs 65ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 45ns (MRS) data sheet specs clocks (tRDL) data sheet specs clocks (tRP) data sheet specs 20ns (tRCD) data sheet specs 20ns Latency Description
Application Note
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April 2003
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Micron 48LC4M16A2-75
Micron 48LC4M16A2-75 devices arranged 1Mbit banks with latency MHz.
Table Micron 48LC4M16A2-75
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd OpMode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x0054A2AA 0100 0x66000C24 0110 0xC24 0x00000033 Bursts Normal Latency Sequential bursts Burst (tRFC) data sheet specs 66ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 44ns (tMRD) data sheet specs clocks (tWR) data sheet specs clock 7.5ns (tRP) data sheet specs 20ns (tRCD) data sheet specs 20ns Latency Description
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Micron 48LC8M16A2-75
Micron 48LC8M16A2-75 16MB devices arranged 2Mbit banks with latency MHz.
Table Micron 48LC8M16A2-75
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd OpMode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x005522A9 0100 0x66000C24 0110 0xC24 0x00000023 Bursts Normal Latency Sequential bursts Burst (tRFC) data sheet specs 66ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 44ns (tMRD) data sheet specs clocks (tWR) data sheet specs clock 7.5ns (tRP) data sheet specs 15ns (tRCD) data sheet specs 15ns Latency Description
Application Note
Rev.
April 2003
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Micron 48LC8M16A2-75
Micron 48LC8M16A2-75 16MB devices arranged 2Mbit banks with latency MHz.
Table Micron 48LC8M16A2-75
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd OpMode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x00551281 0010 0x42000818 0100 0x818 0x00000023 Bursts Normal Latency Sequential bursts Burst (tRFC) data sheet specs 66ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 44ns (tMRD) data sheet specs clocks (tWR) data sheet specs clock 7.5ns (tRP) data sheet specs 15ns (tRCD) data sheet specs 15ns Latency Description
Application Note
SDRAM Performance Au1000TM, Au1100and Au1500Processors
Rev. April 2003
Micron 48LC4M32B2TG-7
Micron 48LC4M32B2TG-7 16MB devices arranged 1Mbit banks with latency MHz.
Table Micron 48LC4M32B2TG-7
Field mem_sdmode 19:18 17:15 14:11 10:9 mem_sdrefcfg 31:28 27:26 24:0 mem_sdwrmd OpMode Latency Burst Type Burst Length Trpm Tras Tmrd Trcd Name Value 0x00549AA9 0011 0x560009EF 0101 0x9EF 0x00000023 Bursts Normal Latency Sequential bursts Burst (tRFC) data sheet specs 70ns from mem_sdmode Enable Refresh 64ms 4096 rows SDRAM operation core only caching master SDRAM operation banks address lines column address lines (tRAS) data sheet specs 42ns (tMRD) data sheet specs clocks (tWR) data sheet specs clock (tRP) data sheet specs 20ns (tRCD) data sheet specs 20ns Latency Description
Application Note

Revision: Issue Date: April 2003 Revision Issue Date October 2002

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