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AlchemySolutions Au1100Processor Performance
Revision: 30274A Issue Date: April 2003
2003 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Contacts www.amd.com pcs.support@amd.com Trademarks AMD, Arrow logo, Alchemy, combinations thereof, Au1100 trademarks Advanced Micro Devices, Inc. MIPS registered trademark MIPS32 trademark MIPS Technologies, Inc. Other product names used this publication identification purposes only trademarks their respective companies.
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Introduction
This document describes performance characteristics Au1100processor based design using integrated controller. This document assumes reader familiar with technology AlchemySolutions Au1100Processor Data Book (see "References"). This document also assumes reader familiar with applications note "Au1x00 SDRAM Performance" which outlines SDRAM performance typical system (see "References"). remainder this document uses numbers 396MHz system with 99MHz SDRAM interface, outlined SDRAM applications note.
Controller Overview
Au1100 processor features integrated controller connecting liquid crystal displays cathode tubes. controller supports common industry standard panel technologies able drive cathode tubes external digital-to-analog converter (DAC). discussion follow, term display reference either cathode tube with appropriate DAC. majority information presented this document applicable panel, calculations differ. Au1100 processor databook contains details additional information operation controller. general arrangement Au1100 processor controller depicted below.
Au1100Processor
Core Cntrlr Static Cntrlr
Flash/ PCMCIA/ Other
SDRAM
SDRAM Cntrlr
Figure Au1100Processor controller
SBUS
LCD_FCK LCD_LCK LCD_BIAS LCD_LEND LCD_D[15:0] LCD_PWM[1:0]
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performance input/output peripheral usually described terms maximum amount data that moved through interface given time period. example, 100Mbps Ethernet controller move maximum 12.5MB/s. actual performance less than maximum, data movement occurs slower pace. case output-only controller, performance essentially constant. Unlike many peripheral I/Os, controller fails satisfy constant performance requirement, display refresh fails, resulting visual artifacts (and just slower data movement). performance constant controller easily calculated given display type. However, controller only aspect performance Au1100 processor based design. remainder this document identifies influences system performance design using Au1100 processor LCD.
Unified Memory Architecture Fundamentals
Figure "Au1100Processor controller" depicts unified memory architecture (UMA) arrangement where memory used controller framebuffer shared with rest system. this arrangement, core performs drawing framebuffer, which resides SDRAM, controller continuously refreshes display fetching framebuffer contents sending pixel data display. non-unified memory architecture, graphics) controller dedicated memory pool that contains framebuffer. Furthermore, graphics) controller priority over processor-initiated accesses framebuffer memory order maintain refresh display. eliminating need dedicated framebuffer memory pool, more cost-effective graphics solution than non-unified memory architecture environment. However, since core, controller other peripherals share SDRAM, memory latency bandwidth affect system performance.
System (SBUS)
system (SBUS) main within Au1100 processor. such, access system necessary order access SDRAM, Static Bus, integrated peripherals. SBUS typically operates one-half core frequency, SDRAM controller operates one-half frequency SBUS. Au1100 processor SBUS four master slots handling system masters: core Ethernet controller controller Host controller IrDA controller controller
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arbitration scheme system round-robin; each master slot equal opportunity obtain access system bus. particular system master other system masters request bus, then master immediately wins system bus. contrast, other system masters request bus, then master must wait three other system master slots' transfers before wins system bus, depicted following figure.
SBUS
Figure System Arbitration
When system master wins arbitration system bus, performs transfers to/from integrated peripherals, SDRAM, Static bus.
Latency Bandwidth
Latency defined amount time between when request resource initiated when request that resource granted. scope this discussion, latency time between when system master (e.g. controller) requests access system (e.g. order access framebuffer memory) when system granted that master. Bandwidth amount data that moved across system time interval. Au1100, latency bandwidth inversely related such that increase latency results decrease bandwidth (since less time available move data), vice versa. factors influence latency bandwidth: system arbitration, transfer time. stated previously, access SDRAM requires access system bus. practical purposes, latency onto system latency SDRAM. Figure "System Latency Master" illustrates round-robin arbitration scheme with system masters requesting simultaneously, corresponding effect system latency master
SBUS
Latency System Master
Figure System Latency Master
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illustration also demonstrates impact transfer time latency, turn bandwidth. While transfer time integrated peripheral registers negligible, SDRAM, Static transfer times appreciable delay system latency. Note that from perspective system master increases system latency result fewer opportunities system master perform transfers to/from SDRAM given time interval. Thus increase system latency results decrease effective SDRAM bandwidth system master (the actual SDRAM bandwidth potential unchanged, outlined SDRAM applications note).
3.2.1 SDRAM Interface
396MHz Au1100 processor operating SDRAM controller 99MHz, SDRAM singlebeat access 60ns cycles 10.1ns), SDRAM burst access 121ns cycles 10.1ns). Accesses SDRAM upwards 121ns system latency other system masters. typical SDRAM configuration capable approximately 248.9MB/s throughput. SDRAM bandwidth important since main storage applications, data framebuffer. There must enough SDRAM bandwidth satisfy controller refresh demand well applications. SDRAM bandwidth needed controller product display resolution size, pixel depth refresh rate. following table lists some common resolutions resulting SDRAM bandwidth requirement.
Table Controller SDRAM Bandwidth
Horizontal (Pixels) QVGA QVGA Vertical (Pixels) Depth (Bits Pixel) Refresh Rate (Hz) Bandwidth (MB/s) 4.6MB/s 9.2MB/s 36.8MB/s 57.6MB/s 69.1MB/s
above values represent SDRAM bandwidth demand controller continuously refreshes display. With total SDRAM bandwidth 248.9MB/s, controller consumes relatively small percentage, leaving ample bandwidth core applications perform graphics operations. controller timing values should configured minimize SDRAM bandwidth demand. particular, refresh rate should lowest rate permitted display.
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3.2.2 Static Interface
Static permits wide variety external devices connect Au1100 processor. transfer time these peripherals tens hundreds nanoseconds. Flash memories typically range from 90ns 120ns, PCMCIA cards typically 150ns, 200ns 250ns. Furthermore, Static features EWAIT# signal, PWAIT# signal PCMCIA, which asserted external devices insert arbitrary number wait states into transfer. assertion these signals further increases latency other system masters. full impact static peripherals that assert EWAIT# PWAIT# discussed after outlining latency requirements controller.
Latency Bandwidth with Respect Controller
refresh display, controller must fetch pixels frame, refresh rate display. fetch frame, controller generates series burst accesses SDRAM. Since single SDRAM burst fetches only bytes, multiple SDRAM accesses needed fetch entire frame. controller implements 320-word buffers moving data from SDRAM pixel engine. buffers ping-pong buffers: pixel engine pulls data from buffer while other buffer filled from SDRAM. pixel engine consumes buffer, next buffer filled, pixel engine incurs under-flow repeats last pixel, resulting display artifacts. time empty 320-word buffer determines maximum time allowed fill 320word buffer order avoid buffer under-flow condition. pixel engine pulls pixel from buffer every pixel clock while rasterizing (for sake simplicity, horizontal non-display times ignored). Thus, pixel clock period multiplied size buffer divided number pixels buffer yields buffer empty/fill time given display configuration. pixel clock derived from values programmed into sys_clksrc, sys_freqctrl lcd_clkcontrol. Table provides example pixel clock settings common display types.
Table Pixel Clock Timing
Horizontal (Pixels) QVGA Vertical (Pixels) FREQn 48MHz 96MHz 96MHz lcd_clkcontrol[PCD] Pixel Clock 12MHz (83.3ns) 24MHz (41.6ns) 48MHz (20.8ns)
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number pixels buffer contains determined lcd_control[BPP] field. Table summarizes possible combinations:
Table Buffer Pixels
lcd_control[BPP] Bits Pixel Number Pixels Buffer 10240 5120 2560 1280
time needed empty 320-word buffer simply product pixel clock period number pixels contained buffer. Table summarizes buffer empty time example pixel clocks.
Table 320-Word Buffer Empty Time
Horizontal (Pixels) QVGA Vertical (Pixels) Bits Pixel Pixel Clock (ns) 83.3 83.3 83.3 83.3 83.3 83.3 41.6 41.6 41.6 41.6 41.6 41.6 Pixels Buffer 10240 5120 2560 1280 10240 5120 2560 1280 Buffer Time (ns) 852,992 426,496 213,248 106,624 53,312 53,312 425,984 212,992 106,496 53,248 26,624 26,624
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Table 320-Word Buffer Empty Time
Horizontal (Pixels) Vertical (Pixels) Bits Pixel Pixel Clock (ns) 20.8 20.8 20.8 20.8 20.8 20.8 Pixels Buffer 10240 5120 2560 1280 Buffer Time (ns) 212,992 106,496 53,248 26,624 13,312 13,312
avoid buffer under-flow condition, time needed fill other 320-word buffer must exceed time empty 320-word buffer. 320-word buffer permits tens, hundreds, even thousands microseconds time which fill next buffer. fill 320-word buffer requires SDRAM 8-word bursts, approximately 4,840ns (121ns bursts); significantly less than 320-word buffer empty time. design capability Au1100 processor controller permits ample time fetch buffers well perform other useful work system.
Latency Bandwidth Affect Controller
main points preceding discussion that 320-word ping-pong buffers permit adequate time retrieve framebuffer contents from SDRAM well establish upper-bound avoiding display artifacts. This section examines conditions that cause 320-word buffer fill time exceed empty time. 320-word buffer fill time effect creates hard real-time SDRAM bandwidth demand bursts buffer empty/fill time. Failure complete SDRAM burst this time interval causes pixel engine under-flow repeat pixels. during this time period that efficient accesses SDRAM extremely important. Consider situation where core transferring block data to/from PCMCIA card (e.g. network storage card). Only core controller actively requesting system bus. system arbitration scheme results core controller alternating transfers system bus. Thus each controller access, there core access PCMCIA. Table summarizes time required fill 320-word buffer when both core controller using system bus.
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Table PCMCIA Transfer Times
PCMCIA Transfer Time 150ns 200ns 250ns 300ns (PWAIT# asserted) 350ns (PWAIT# asserted) 400ns (PWAIT# asserted) 500ns (PWAIT# asserted) 600ns (PWAIT# asserted) PCMCIA Accesses 6,000ns 8,000ns 10,000ns 12,000ns 14,000ns 16,000ns 20,000ns 24,000ns SDRAM Accesses 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns PCMCIA +LCD Time 10,840ns 12,840ns 14,840ns 16,840ns 18,840ns 20,840ns 24,840ns 28,840ns
comparing time fill buffer from this table with that time empty buffer Table "LCD 320-Word Buffer Empty Time", apparent that number display configurations, especially 12bpp 16bpp configurations, susceptible display artifacts when accessing slow PCMCIA cards. example, 640x480x16bpp display refresh fails PCMCIA card accesses consistently need 600ns (buffer fill time 28,840ns exceeds buffer empty time 26,624ns). Also note that this example does take into consideration peripherals other than core controller which request system bus. System requests other peripherals simply more time actual time needed fill 320-word buffer. addition, observed some PCMCIA cards assert PWAIT# extend transfer time 1,000ns microsecond), even longer. Au1100 processor based product permits using PCMCIA cards with this type transfer time, ability fill 320-word buffer allotted time extremely difficult, will result display artifacts. number 320-word buffer fills needed refresh common configurations provided Table
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Table 320-Word Buffer Fills Refresh
Horizontal (Pixels) QVGA Vertical (Pixels) Framebuffer Size (Pixels) 76,800 76,800 76,800 76,800 76,800 76,800 307,200 307,200 307,200 307,200 307,200 307,200 480,000 480,000 480,000 480,000 480,000 480,000 Bits Pixel Pixels Buffer 10240 5120 2560 1280 10240 5120 2560 1280 10240 5120 2560 1280 Buffer Fills Refresh 46.8 93.7 197.5
number 320-word buffer fills refresh multiplied display refresh rate determines number opportunities second buffer under-flows occur. 320-word buffer under-flow does occur, display artifacts last only until start next refresh. controller under-flow problem direct result long latency, bandwidth short-coming. SDRAM adequate bandwidth supply controller; however, ability controller access SDRAM efficient manner impacted system latency introduced competing accesses static bus.
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4.1.1 Controller lcd_control[22:21] Setting
previously noted, increase system latency results decrease effective SDRAM bandwidth controller. combat effects long latency, Au1100 processor controller implements feature that determines many SDRAM burst accesses should perform system arbitration. increasing number SDRAM bursts controller access, controller effectively increases bandwidth SDRAM consequently increases likelihood controller filling 320-word buffers time, even with occurrence long latency static accesses. number SDRAM bursts system arbitration selected lcd_control[22:21].
Table lcd_control[22:21] Settings
lcd_control[22:21] Number SDRAM Bursts
setting lcd_control[22:21]=11, controller performs SDRAM bursts system arbitrations. Table expands upon previous example controller alternating system transfers with core, presenting change actual transfer time 320-word buffer fill.
Table PCMCIA Transfer Times with lcd_control[22:21]=11b
PCMCIA Transfer Time 150ns 200ns 250ns 300ns (PWAIT# asserted) 350ns (PWAIT# asserted) 400ns (PWAIT# asserted) 500ns (PWAIT# asserted) PCMCIA Accesses 1,500ns 2,000ns 2,500ns 3,000ns 3,500ns 4,000ns 5,000ns SDRAM Accesses 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns 4,840ns PCMCIA +LCD Time 5,340ns 6,840ns 7,340ns 7,840ns 8,340ns 8,840ns 9,840ns
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Table PCMCIA Transfer Times with lcd_control[22:21]=11b
PCMCIA Transfer Time 600ns (PWAIT# asserted) PCMCIA Accesses 6,000ns SDRAM Accesses 4,840ns PCMCIA +LCD Time 10,840ns
lcd_control[22:21]=11b SDRAM burst arbitration) significantly increases chances controller filling 320-word buffer allotted time. While this table indicates that possible avoid under-flow situations, keep mind that this does include system accesses other masters, PCMCIA static bus) transfers with transfer times greater than 600ns. presence more system requestors longer PCMCIA transfer times increases likelihood buffer under-flow, undesirable display artifacts.
4.1.2 Controller sys_powerctrl[17] Setting
further combat effects system latency, Au1100 processor (stepping newer) features setting sys_powerctrl[17] change system arbitration scheme favor controller. Setting sys_powerctrl[17] gives controller priority over other system requestors.
Figure System Arbitration with sys_powerctrl[17]=1
SBUS
change arbitration scheme permits shorter system latency controller, therefore more opportunities onto system which turn increases likelihood filling 320-word buffer time. Note that this setting does allow controller unconditional access system bus. controller must still wait another system master using system bus. does, however, reduce number arbitration cycles needed controller system bus. result that system latency controller decreases, while latency other masters slightly increases. This setting likely help display refresh system where many peripherals requesting system bus, help when core accessing slow PCMCIA cards during fill 320-word buffer.
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Performance Tuning
Au1100 processor design adequate SDRAM bandwidth latency requirements successfully drive display using integrated controller. following sections detail optimizations that made improve overall system performance.
Hardware Design Considerations
Since function controller fixed predictable, there only hardware design decisions made. These decisions are: display size refresh rate/timing Selection Au1100 processor operating frequency Selection SDRAM Appropriate setting lcd_control[22:21] Static peripheral timings
display single largest factor affecting overall system performance. display size, depth refresh rate determine SDRAM bandwidth core graphics performance. larger display, more SDRAM bandwidth that needed, more performance that needed from core graphics. choice display size must balance market/ customer requirements application functionality. refresh rate timing must optimized demand least possible bandwidth from Au1100 processor SDRAM. Aggressive refresh rates timing merely consumes SDRAM bandwidth increases chance under-flow condition display artifacts. operating frequency Au1100 processor ultimately determines overall system performance SDRAM clock frequency. design should Au1100 processor running appropriate frequency yield desired application graphics performance, well appropriate SDRAM bandwidth. SDRAMs selected design should provide necessary SDRAM bandwidth; prototyping profiling intended application recommended. "SDRAM Performance" application note provides insight into selection criteria expected bandwidth SDRAM Au1100 processor design. lcd_control[22:21] bits should according needs system. systems with long latency static accesses, necessary setting SDRAM bursts system arbitration improve ability controller fill 320-word buffer. This feature might also prove useful larger display panels that require aggressive refresh timings.
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Accesses static peripherals have unusually large transfer time, which directly translates into dramatic increase system latency. System designers must carefully consider timing peripherals static optimize timings consume least amount time possible. prime example PCMCIA interface, where card transfer times vary from 150ns 250ns depending upon card inserted. addition, card also assert PWAIT# extend cycle time indefinitely.
Software Design Considerations
controller merely fetches pixel data from framebuffer residing SDRAM; responsibility software executing core perform graphics operations. graphics driver Au1100 processor controller optimize framebuffer caching mapping improve overall system performance.
5.2.1 Framebuffer Caching
Generally speaking caching data improves overall performance. However, framebuffer presents unique challenge that large, infrequently referenced data structure. even small display panel with resolution 320x240 16bpp, resulting framebuffer 153,600 bytes easily exceeds 16KB data cache core. direct result, caching framebuffer displaces other useful, non-framebuffer data (such working variables, data-sets, stack, etc.) from cache. Furthermore, cache best utilized when memory referenced frequently; framebuffers pixels typically only written once graphics operations remain unchanged until subsequent graphics operation changes pixel. result that undesirable have framebuffer occupy entire cache since reduces overall cache rate turn reduces overall system performance. However, performance reasons, always desirable most efficient access possible framebuffer. Au1100 processor offers several options improving framebuffer accesses. using translation look-aside buffers (TLB) access framebuffer (that KSEG0 KSEG1spaces used exclusively access framebuffer), then framebuffer cache setting should following, order preference: CCA=6 (cached into with data cache locked CCA=6 (cached into without data cache locked CCA=7 (non-cached, write buffer merging gathering) CCA=2 (non-cached, write buffer merging gathering) CCA=3 (cached, uses entire data cache) CCA, cache coherency attributes, field MIPS® TLB. AlchemyAu1100Processor from Data Book "2.4 Virtual Memory" more information. values provided "Table Values" data book. Application Note
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5.2.2 Framebuffer CCA=6
Case CCA=6, which cached streaming. Furthermore software locks data cache. This configuration mutually beneficial effects: permits framebuffer cached confining framebuffer data cache, non-framebuffer data kept which prevents from being purged framebuffer contents. This configuration cache framebuffer, 12KB cache non-framebuffer items. following example code configures framebuffer cache locking cache. parameter this routine framebuffer address.
.global dcacheStreamInit .set noreorder dcacheStreamInit: t0,128 number dcache sets dcsiloop: cache 0x15,0(a0) address cache pref 0x4,0(a0) streaming prefetch into cache 0x1D,0(a0) dcache fetch lock addiu t0,t0,-1 decrement sets zero,t0,dcsiloop addiu a0,a0,32 increment address cacheline size .set reorder
When this setting used conjunction with lcd_control[C]=1, there need flush data cache SDRAM; data cache snoop mechanism returns current data cache lines that contain framebuffer data. This preferred configuration permits framebuffer caching, coherent updates, prevents non-framebuffer items from being purged from data cache. Case CCA=6, data cache locked. this configuration, most benefits just described realized, non-framebuffer data land doing framebuffer non-framebuffer data displace each other from degrading full benefits locking
5.2.3 Framebuffer CCA=7
Case CCA=7, which non-cached, with write buffer merging gathering. this configuration, framebuffer cached, writes (e.g. blits) framebuffer merged gathered more efficient burst accesses SDRAM. Burst accesses SDRAM result improved throughput increase overall system performance.
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lcd_control[C] setting should (non-coherent) framebuffer contents never data cache.
5.2.4 Framebuffer CCA=2
Case CCA=2 which non-cached write buffer merging gathering. this configuration, framebuffer accesses travel through writebuffer individually, thus consuming more SDRAM bandwidth than burst accesses with CCA=7. lcd_control[C] setting should (non-coherent) framebuffer contents never data cache.
5.2.5 Framebuffer CCA=3
Case CCA=3, which cached. Furthermore, CCA=3 permits framebuffer contents entire data cache. previously noted, framebuffer occupies entire data cache, overall system performance degrades. Therefore using CCA=3 recommended. this setting used, lcd_control[C] setting must (coherent); data cache snoop mechanism returns current data cache lines that contain framebuffer data.
5.2.6 Framebuffer Mapping
When using translation look-aside buffers (TLB) access framebuffer (that KSEG0 KSEG1spaces used exclusively access framebuffer), framebuffer mapping should attempt single TLB. Most software environments/operating systems page size. number pages required cover entire framebuffer various sizes provided Table "Number Framebuffer Pages".
Table Number Framebuffer Pages
Width (pixels) QVGA QVGA SVGA 1024 Height (pixels) Depth (bits pixel) Size (Bytes) 76,800 153,600 614,400 960,000 1,572,864 Pages
core dual-entry that maximum pages. framebuffer mapped using pages, then drawing takes place across display, performance limiting effects come into play: Application Note
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misses occur more frequently which degrades performance drawing routines, updates framebuffer pages displace other valid code data mappings from degrade overall system performance. larger display size, higher frequency misses longer takes graphics operations complete. graphics load/store instructions miss TLB, exception taken. Software optionally stores context, performs table walk, updates TLB, optionally restores context re-initiates load/ store operation that caused miss. Furthermore, MIPS contains mapping both code data, misses framebuffer accesses result displacing valid entries program instruction/code pages. effect, program code, data framebuffer compete limited number entries TLB. Avoiding misses therefore desirable, mapping entire framebuffer using single eliminates such performance limiting effects. handle page sizes 16MB (and reality 32MB dual-entry TLB). display sizes that Au1100 processor controller handle, page size covers entire framebuffer, covers surface flipping/ping-pong buffers. Thus, entire framebuffer mapped with single entry. order entire framebuffer with single TLB, following must occur: framebuffer memory must valid PageSize bytes size, PageSize*2 size. framebuffer memory must mapped exactly TLB, with either both entries valid. framebuffer memory must aligned PageSize, PageSize*2, boundary, e.g. PageSize, alignment physical address must boundary. process virtual address into which framebuffer mapped must also aligned same boundary, e.g. PageSize, alignment virtual address must boundary.
With single entry, misses associated performance degradation minimized. Depending upon software environment, additional performance improvement realized mapping framebuffer with static, wired, entry. MIPS32TLB permits certain entries participate random replacement algorithm (dynamic) thus remain indefinitely (static) until removed software. using static entry, misses caused framebuffer accesses completely eliminated. Combining optimizations framebuffer caching mapping, ideal framebuffer configuration uses single, static entry covering entire framebuffer with CCA=6 data cache locked.
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Conclusion
Au1100 processor controller provides cost-effective, flexible solution connecting variety displays. While performance controller constant, system design issues, particular long-latency static accesses, impact ability controller maintain display refresh. Several optimizations including choice panel, Au1100 processor operating frequency, software optimizations framebuffer caching mapping presented fine-tuning Au1100 processor based design.
References
AlchemyAu1100Processor from Data Book, AMD, 2002. Alchemy Solutions Au1000, Au1100 Au1500 Processors SDRAM Performance Application Note, AMD, 2003.
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