8-Bit Microcontroller Data Book Updates Changes Overview data she

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This document contains latest information about data book data sheets. references data book refers August 1999 version "AVR® RISC MICROCONTROLLER DATA BOOK". references data sheets refer latest version data sheets Atmel's page www.atmel.com. data sheets Atmel's page updated more frequently than printed data book. known errors each data sheet corrected when version released. This document contains known errors that have been corrected yet. designers using microcontrollers should this document together with data sheets. updated frequently, should contain complete list known documentation errors given time. Please note that this document only covers errors documentation. errors microcontrollers, errata sheet each device. find errors documentation that listed this document, please send email support line avr@atmel.com.
8-Bit Microcontroller Data Book Updates Changes
Overview data sheets
Part Number Data Sheet Revision August 1999 Data Book 0838E-04/99 0839E-04/99 1004B-04/99 1042D-04/99 0841E-04/99 1041E-04/99 1229A-04/99 1006A-04/99 1187A-06/99 1273A-04/99 1228A-05/99 0945D-06/99 0856B-06/99 Data Sheet Revision Atmel's site www.atmel.com 0838E-04/99 0839E-04/99 1004B-04/99 1042D-04/99 0841E-04/99 1041E-04/99 1229A-04/99 1006B-10/99 1187B-11/99 1273A-04/99 1228A-08/99 0945E-12/99 0856B-06/99 1062B-10/99
AT90S1200 AT90S2313 AT90S/LS2323 AT90S/LS2343 AT90S/LS2333 AT90S/LS4443 AT90S4414/8515 AT90S/LS4434 AT90S/LS8535 AT90C8534 ATtiny10/11/12 ATtiny15 ATtiny22/22L ATmega161/161L ATmega603/603L ATmega103/103L Instruction ATtiny28
Rev. 12/99A
AT90S1200
latest data sheet rev. 0838E-04/99. data sheet printed data book rev. 0838E-04/99.
Changes AT90S1200 Data Sheet:
Page: Change Add: 2-20 2-25 feature list under packages, replace "20-pin PDIP SOIC" "20-pin PDIP, SOIC SSOP". Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." EEPROM Read/Write Access description, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." 2-26 EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed." Analog Comparator Control Status Register description, change initial value from "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values bits from "Hi-Z" "N/A". Replace figure below:
2-27 2-29 2-33 2-44
Figure Serial Programming Verify
AT90S1200 RESET
MISO MOSI
CLOCK INPUT
XTAL1
Data Book Updates Changes
Data Book Updates Changes
2-49: Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
2-50 2-62
first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". Register Summary, replace "2-2-xx" "2-xx".
AT90S2313
latest data sheet rev. 0839E-04/99. data sheet printed data book rev. 0839E-04/99.
Changes AT90S2313 Data Sheet:
Page: Change Add: 3-28 3-29 3-38 Table remove this note: "Note: When changing ISC11/ISC10 bits, INT1 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." page, paragraph "Note: compare register contains value prescaler (CS12.CS10 001), output will produce pulse all, because up-counting down-counting values reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches TOP-value, making period pulse." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." EEPROM Read/Write Access description, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." 3-40 Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed." Analog Comparator Control Status Register description, change initial value from "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values bits from "Hi-Z" "N/A". Replace figure below:
3-39
3-41
3-47 3-49 3-54 3-67
Data Book Updates Changes
Data Book Updates Changes
Figure Serial Programming Verify
AT90S2313 RESET
MISO MOSI
CLOCK INPUT
XTAL1
3-72:
Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
3-73 3-84
first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". Register Summary, replace "3-3-xx" "3-3-3-xx" "3-xx".
AT90S/LS2323 AT90S/LS2343
latest data sheet rev. 1004B-04/99. data sheet printed data book rev. 1004B-04/99.
Changes AT90S/LS2323 AT90S/LS2343 Data Sheet:
Page: Change Add: Descriptions AT90S/LS2323 replace description Port (PB2.PB0) "Port 3-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port pins provide internal pull-up resistors (selected each bit). port pins tri-stated when reset condition becomes active." Descriptions AT90S/LS2343 replace description Port (PB4.PB0) "Port 5-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port pins provide internal pull-up resistors (selected each bit). port pins tri-stated when reset condition becomes active." 4-19 4-25 Figure containing "+1" input summation operator. first paragraph Watchdog Reset, replace "When Watchdog times out, will generate short reset pulse XTAL cycle duration." "When Watchdog times out, will generate short reset pulse clock cycle duration." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." EEPROM Read/Write Access, replace line "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When read, halted clock cycles.". 4-35 Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed." 4-37 Port Input Pins Address PINB description, change Initial Values bits from "Hi-Z" "N/A".
4-29 4-34
Data Book Updates Changes
Data Book Updates Changes
4-38 4-40 Replace section name "MISO Port "MISO/INT0 Port High-Voltage Serial Programming, replace item "Power-up sequence: Apply 5.5V between GND. RESET wait least Then, RCEN Fuse programmed; Toggle XTAL1/PB3 least times with minimum 100ns pulse-width. "0". Wait least 100ns. RCEN Fuse programmed; "0". Wait least 4µs. both cases; Then apply RESET wait least before changing PB0. Wait before giving instructions." 4-40 4-42 High-Voltage Serial Programming, replace item "Set "1"." "Set RESET "0"." table replace entries
0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 Reading means Fuse/Lock programmed.
Read Fuse Lock bits (AT90S/ LS2323) Read Fuse Lock bits (AT90S/ LS2343)
1_2Sxx_xxFx_xx
0_0000_0000_00 0_0110_1100_00 1_2Sxx_xxRx_xx Reading means Fuse/Lock programmed.
entries (Note: 4'th 5'th column been inverted compared original data book)
Read Fuse Lock bits (AT90S/ LS2323) Read Fuse Lock bits (AT90S/ LS2343)
0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx
0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx
0_0000_0000_00 0_0111_1100_00
Reading means Fuse/Lock programmed.
1_2Sxx_xxFx_xx
0_0000_0000_00 0_0111_1100_00 1_2Sxx_xxRx_xx Reading means Fuse/Lock programmed.
4-43 4-49 4-59
figure remove "CLOCK INPUT", "XTAL1/PB3" arrow connecting them. first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". Register Summary, replace "4-page" "page". addition, TIMSK; replace "page -15" "page 4-28", TIFR; replace "page 4-16" "page 4-28", MCUCR; replace "page 4-16" "page 4-29", MCUSR; replace "page 4-14" "page 4-26". Instruction Summary under BRANCH INSTRUCTIONS, replace
Rd,Rr Compare, Skip Equal Skip Register Cleared Skip Register Skip Register Cleared Skip Register (Rr(b)=0) (Rr(b)=1) (P(b)=0) (R(b)=1) None None None None None
4-60
CPSE SBRC SBRS SBIC SBIS
CPSE SBRC Rd,Rr Compare, Skip Equal Skip Register Cleared (Rr(b)=0) None None 1/2/3 1/2/3
SBRS SBIC SBIS
Skip Register Skip Register Cleared Skip Register
(Rr(b)=1) (P(b)=0) (R(b)=1)
None None None
1/2/3 1/2/3 1/2/3
Data Book Updates Changes
Data Book Updates Changes
AT90S/LS2333 AT90S/LS4433
latest data sheet rev. 1042D-04/99. data sheet printed data book rev. 1042D-04/99.
Changes AT90S/LS2333 AT90S/LS4433 Data Sheet:
Page: Change Add: "Pin Descriptions", AVCC, change "This supply voltage Converter. should externally connected low-pass filter." "This supply voltage Port Converter. used, this must connected Vcc. used, this should connected low-pass filter." Figure containing "+1" input summation operator. Table remove this note: "Note: When changing ISC11/ISC10 bits, INT1 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." 5-34 5-37 "Timer/Counter Control Register TCCR1B", bit3 CTC1, change count sequence when prescaler divide from ".C-1 ".C-1 Before table paragraph "Note: compare register contains value prescaler (CS12.CS10 001), output will produce pulse all, because up-counting downcounting values reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches TOP-value, making one- period pulse." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)."
5-15 5-28
5-39 5-41
5-47.50 UART description, replace "USR" "UCSRA" "UCR" "UCSRB" everywhere. 5-50 5-52 5-59 5-60 5-61 5-66 5-68 5-80 last line, replace "UBRRH" "UBRRHI". "Analog Comparator Control Status Register ACSR", initial value "N/A". "ADC Noise Canceling Techniques" item replace "Figure "Figure 49". Figure replace resistor inductor. Change capacitor value from Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINC description, change Initial Values from "Hi-Z" "N/A". Change Initial Values (zero). Port Input Pins Address PIND description, change Initial Values from "Hi-Z" "N/A". "Serial Downloading", replace Figure figure below.
Figure Serial Programming Verify
AT90S2333/4433
6.0V MISO MOSI
RESET
CLOCK INPUT
XTAL1
5-86
Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
5-86 5-88
Characteristics", footnote replace "IOL" "IOH" everywhere. first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.".
Data Book Updates Changes
Data Book Updates Changes
AT90S4414/8515
latest data sheet rev. 0841E-04/99. data sheet printed data book rev. 0841E-04/99.
Changes AT90S4414/8515 Data Sheet:
Page: Change Add: 6-17 6-29 6-30 6-39 Figure containing "+1" input summation operator. Table remove this note: "Note: When changing ISC11/ISC10 bits, INT1 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Before table paragraph "Note: compare register contains value prescaler (CS12.CS10 001), output will produce pulse all, because up-counting downcounting values reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches TOP-value, making one- period pulse." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." EEPROM Read/Write Access description, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." 6-42 Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed." Analog Comparator Control Status Register description, change initial value from "N/A". Port Input Pins Address PINA description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINC description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values from "Hi-Z" "N/A". Replace figure below:
6-41
6-43
6-54 6-57 6-59 6-64 6-66 6-79
Figure Serial Programming Verify
AT90S4414/8515 RESET
MISO MOSI
CLOCK INPUT
XTAL1
6-84:
Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
6-88 6-98
first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". Register Summary, replace "6-6-xx" "6-xx".
Data Book Updates Changes
Data Book Updates Changes
AT90S/LS4434 AT90S/LS8535
latest data sheet rev. 1041E-04/99. data sheet printed data book rev. 1041E-04/99.
Changes AT90S/LS4434 AT90S/LS8535 Data Sheet:
Page: Change Add: "Pin Descriptions", AVCC, change "This supply voltage Converter. should externally connected low-pass filter." "This supply voltage Port Converter. used, this must connected Vcc. used, this should connected low-pass filter." Figure containing "+1" input summation operator. "Timer/Counter Interrupt Flag Register TIFR", change heading "Bit TOV2: Timer/Counter0 Overflow Flag" "Bit TOV2: Timer/Counter2 Overflow Flag". Table remove this note: "Note: When changing ISC11/ISC10 bits, INT1 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." 7-30 Power Down Mode section, replace paragraph ("Note that level triggered interrupt. page 7-98.") "Note that when level triggered interrupt used wake-up from power down, level must held time longer than reset delay time-out period tTOUT." Power Save Mode section, paragraph asynchronous timer clocked asynchronously, Power Down Mode recommended instead Power Save Mode because contents registers asynchronous timer should considered undefined after wake Power Save Mode, even "Timer/Counter Control Register TCCR1B", bit3 CTC1, change count sequence when prescaler divide from ".C-1 ".C-1 Before table paragraph "Note: compare register contains value prescaler (CS12.CS10 001), output will produce pulse all, because up-counting downcounting values reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches TOP-value, making one- period pulse." Replace last paragraph page: "When asynchronous operation selected, oscillator Timer/Counter2 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. Therefore, content Timer/Counter2 registers must considered lost after wake-up from power down, unstable clock signal. user advised wait least second before using Timer/Counter2 after power-up wake-up from power down." "When asynchronous operation selected, 32kHZ oscillator Timer/Counter2 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. user advised wait least second before using Timer/Counter2 after power-up wake-up from power down. contents Timer/Counter2 reg-
7-15 7-27 7-29
7-30
7-36 7-39
7-45
isters must considered lost after wake-up from power down unstable clock signal upon start-up, regardless whether oscillator clock signal applied TOSC pin." 7-47 7-49 note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed." 7-52 Change Figure figure below. Figure Transfer Format with CPHA DORD
7-60 7-67 7-69 7-71 7-76 7-79 7-91
"Analog Comparator Control Status Register ACSR", initial value "N/A". Figure replace resistor inductor. Change capacitor value from Port Input Pins Address PINA description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINC description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values from "Hi-Z" "N/A". "Serial Downloading", replace Figure figure below. Figure Serial Programming Verify
AT90S4434/8535
6.0V MISO MOSI
RESET
CLOCK INPUT
XTAL1
Data Book Updates Changes
Data Book Updates Changes
7-96 Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
7-98 7-109
first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". Register Summary, replace "7-page" "page". addition, replace "page 7-337-" "page 7-33", "page 7377-" "page 7-37", "page 7-387-" "page 7-38", "page 7-467-" "page 7-46", "page 7-487-" "page 7-48".
AT90C8534
latest data sheet rev. 1229A-04/99. data sheet printed data book rev. 1229A-04/99.
Changes AT90C8534 Data Sheet:
Page: Change Add: "Pin Descriptions", AVCC, change "This supply voltage Converter. should externally connected low-pass filter." "This supply voltage Converter. used, this must connected Vcc. used, this should connected low-pass filter." Figure containing "+1" input summation operator. Interrupt Sense Control description this text: "When changing ISC1 bit, interrupt occur. Therefore, recommended first disable INT1 clearing Interrupt Enable GIMSK register. Then, ISC1 changed. Finally, INT1 interrupt flag should cleared writing logical Interrupt Flag GIFR register before interrupt re-enabled." Interrupt Sense Control description this text: "When changing ISC0 bit, interrupt occur. Therefore, recommended first disable INT0 clearing Interrupt Enable GIMSK register. Then, ISC0 changed. Finally, INT0 interrupt flag should cleared writing logical Interrupt Flag GIFR register before interrupt re-enabled." 8-31 EEPROM Read/Write Access description, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed."
8-16 8-26
8-32
Data Book Updates Changes
Data Book Updates Changes
ATtiny10/11/12
latest data sheet rev. 1006B-10/99. data sheet printed data book rev. 1006A-04/99.
Changes ATtiny10/11/12 Data Sheet web:
Page: Change Add: Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." first paragraph Sleep modes ATtiny10/11 section, replace sentence wake-up from Power Down Mode change, instructions following SLEEP executed before change interrupt routine. wake-up from Power Down Mode change, instruction cycles executed before change interrupt flag updated. During these cycles, processor executes instructions, interrupt condition readable, interrupt routine started yet. note Table avoid unintentional resets, Watchdog Timer should disabled reset last sentence first paragraph, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." EEPROM Control Register description, change initial value EEWE from "X". EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed."
Changes ATtiny10/11/12 section data book
Page: Change Add: 9-14 9-24 both Configuration figures, replace RESET with RESET. Figure containing "+1" input summation operator. first line Watchdog Reset section, change XTAL cycle" cycle". Figure change XTAL Cycle" Cycle". 9-29 Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." first paragraph Sleep modes ATtiny10/11 section, replace sentence
wake-up from Power Down Mode change, instructions following SLEEP executed before change interrupt routine. wake-up from Power Down Mode change, instruction cycles executed before change interrupt flag updated. During these cycles, processor executes instructions, interrupt condition readable, interrupt routine started yet. 9-34 note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." first paragraph ATtiny12 Calibrated Internal Oscillator section, "For details pre-programmed calibration value, section `Calibration Byte ATtiny12' page 9-42. second paragraph, "The calibrated oscillator used time EEPROM access. EEPROM written, calibrate more than above nominal frequency. Otherwise, EEPROM write fail. Table shows range OSCCAL. Note that Oscillator intended calibration 1.0MHz, thus tuning other values guaranteed. Table Internal Oscillator Frequency Range.
OSCCAL value Min. Frequency 0.5MHz 0.7MHz 1.0MHz Frequency 1.0MHz 1.5MHz 2.0MHz
9-35
second line, change "The write access time range 4ms, depending VCC." "The write access time range 3.4ms, depending frequency calibrated oscillator." last sentence first paragraph, change "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." EEPROM Control Register description, change initial value EEWE from "X".
9-36
14th line, remove "(typically 2.5ms 2.7V)" Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed."
9-37 9-39 9-40
Analog Comparator Control Status Register description, change initial value from "N/A". Port Input Pins Address PINB description, change Initial Value bits from "Hi-Z" "N/A". first line section Alternate Functions Port change "The alternate functions Port are:" "All Port pins connected change detector that trigger change interrupt. `Pin Change Interrupt' page 9-28 details. addition, Port following alternate functions:".
Data Book Updates Changes
Data Book Updates Changes
9-42 section Calibration Byte ATtiny12, start-up, user software must read this flash location write value OSCCAL register." section ATtiny10/11, change "The +12V used programming enable only, current significance drawn this pin." "Only minor currents (<1mA) drawn from +12V during programming.". 9-44 9-45 9-46 Table remove entire first row. first cell second row, remove "(ATtiny12)". note bottom page, change RSTISBL Fuse" RSTDISBL Fuse". Table remove "tWLWH_CE "row. Figure remove "CLOCK INPUT", "PB3 (XTAL1)" arrow connecting them. 9-47 sixth line, change "Either external clock supplied XTAL1 crystal needs connected across pins XTAL1 XTAL2" "The device clocked clock option during Low-Voltage Serial Programming.". last lines first paragraph, change XTAL clock cycles" clock cycles". first entry Low-Voltage Serial Programming Algorithm, change crystal connected across pins XTAL1 XTAL2, apply clock signal XTAL1 pin." accordance with setting CKSEL fuses, apply crystal/resonator, external clock network, device internal oscillator.". fifth entry, change first "tWD_PROG" "tWD_FLASH tWD_EEPROM". Change second "tWD_PROG" "tWD_FLASH tWD_EEPROM". 9-48 9-50 Data Polling section, change first "tWD_PROG" "tWD_FLASH tWD_EEPROM". Change second third "tWD_PROG" "tWD_EEPROM". Replace Table Table with these tables:
Symbol tWD_ERASE Symbol tWD_FLASH tWD_EEPROM Minimum Wait Delay Minimum Wait Delay
9-52
Characteristics table, replace
Symbol Parameter Condition Active 4MHz, Idle 4MHz, Power Supply Current Power Down(5), enabled Power Down(5), disabled Units
Symbol Vacio Iaclk Tacpd
Parameter Analog Comp Input Offset Analog Comp Input leakage Analog Comp Propagation Del.
Condition VCC/2 2.7V 4.0V
Units
with
Symbol Parameter Condition Active 1MHz, (ATtiny12V) Active 2MHz, (ATtiny10/11L) Active 4MHz, (ATtiny12L) Active 6MHz, (ATtiny10/11) Active 8MHz, (ATtiny12) Idle 1MHz, (ATtiny12V) Power Supply Current Idle 2MHz, (ATtiny10/11L) Idle 4MHz, (ATtiny12L) Idle 6MHz, (ATtiny10/11) Idle 8MHz, (ATtiny12) Power Down(5), enabled Power Down(5), disabled VACIO IACLK TACPD Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay VCC/2 VCC/2 2.7V 4.0V Units
Data Book Updates Changes
Data Book Updates Changes
9-53 first table, change title from "External Clock Drive" "External Clock Drive ATtiny12" this table:
External Clock Drive ATtiny10/11
2.7V 4.0V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Time Rise Time Fall Time 4.0V 5.5V Units
9-54 9-72
first line, change "These data characterized, tested." "These figures tested during manufacturing.". (MCUSR) table, change "WDTR" "WDRF" "BODR" "BORF".
ATtiny15L
latest data sheet rev. 1187B-11/99. data sheet printed data book rev. 1187A-06/99.
Changes ATtiny15L Data Sheet web:
None.
Changes ATtiny15L section data book:
data sheet ATtiny15 gone through serious improvements corrections since printing "AVR RISC MICROCONTROLLER DATA BOOK AUGUST 1999". user advised download complete ATtiny15 data sheet from Web, since correcting present data book would give user friendly result.
Data Book Updates Changes
Data Book Updates Changes
ATtiny22/22L
latest data sheet rev. 1273A-04/99. data sheet printed data book rev. 1273A-04/99.
Changes ATtiny22/22L Data Sheet:
Generally: external clock option does exist ATtiny22/L. Therefore, references RCEN fuse external clock wrong, part comes ATtiny22L only, ATtiny22. Page: Change Add: 11-3 "ATtiny22/L" read "ATtiny22L". feature list, replace following lines
Special Microcontroller Features
Selectable On-chip Oscillator Power Consumption MHz, 25°C Active: Idle Mode: Power Down Mode: Operating Voltages 6.0V (ATtiny22L) 6.0V (ATtiny22) Speed Grades (ATtiny22L) (ATtiny22)
following description; Special Microcontroller Features
On-chip Oscillator Power Consumption 25°C Active: Idle Mode: 100µA Power Down Mode: Operating Voltages 6.0V Speed Grade Internal Oscillator ~1MHz@5.0V
11-3
Replace Configuration figure shown below.
RESET
(SCK/T0) (MISO/INT0) (MOSI)
11-5
Descriptions ATtiny22/L replace description Port (PB4.PB0) "Port 5-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port pins provide internal pull-up resistors (selected each bit). port pins tri-stated when reset condition becomes active."
11-5 11-5
Remove description "CLOCK" under Descriptions ATtiny22/L. whole section "Clock options" including Figure should replaced "Clock Source ATtiny22L clocked on-chip oscillator. This oscillator runs nominal frequency (VCC 5V)." Figure containing "+1" input summation operator. Replace second paragraph under Memory Access Instruction Execution Timing, "The driven System Clock directly generated from external clock signal applied CLOCK pin." "The driven System Clock directly generated from internal oscillator." Power-On Reset, replace first paragraph; "The ATtiny22/L designed systems where operate from internal oscillator applications where clock signal provided external clock source. After reached VPOT, device will start after time tTOUT (see Figure 23). clock signal provided external clock source, clock must applied until reached minimum voltage defined applied frequency. "The ATtiny22L designed systems where operate from internal oscillator. After reached VPOT, device will start after time tTOUT (see Figure 23)." first paragraph Watchdog Reset, replace "When Watchdog times out, will generate short reset pulse cycle duration." "When Watchdog times out, will generate short reset pulse clock cycle duration." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." line number replace "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When read, halted clock cycles.". Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." EERE: EEPROM Read Enable description, change "When EERE been set, halted clock cycles before next instruction executed." "When EERE been set, halted four clock cycles before next instruction executed."
11-16 11-16
11-21
11-23
11-27 11-31 11-32
11-33
11-34 11-34 11-35
Table remove entry PB3. Port Input Pins Address PINB description, change Initial Values bits from "Hi-Z" "N/A". Remove section, CLOCK Port
Data Book Updates Changes
Data Book Updates Changes
11-35 11-36 11-37 Replace section name "MISO Port "MISO/INT0 Port section Fuse Bits, replace first sentence; "The ATtiny22/L Fuse bits, SPIEN RCEN." "The ATtiny22L Fuse bit, SPIEN.", remove second bullet item which description RCEN fuse. Table delete rows saying
6.0V 5.5V
ATtiny22/L
11-37
High-Voltage Serial Programming Algorithm, replace item "Power-up sequence: Apply 5.5V between GND. RESET wait least "0". Wait least 4µs. Apply RESET wait least before changing PB0. Wait before giving instructions." High-Voltage Serial Programming Algorithm, replace item "Set "1"." "Set RESET "0"." Figure replace "XTAL1/PB3" "PB3". table replace entries
0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_11S1_111R_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 1_2Sxx_xxRx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait tWLWH_PFB after Instr.3 Write Fuse bits cycle finish. program, unprogram. Reading means Fuse/Lock programmed.
11-37 11-38 11-38
Write Fuse bits
Read Fuse Lock bits
entries (Note: Read Fuse Lock bits; 4'th 5'th column have been inverted compared original data book.
Write Fuse Read Fuse Lock bits 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_11S1_1110_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 1_2Sxx_xx0x_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait tWLWH_PFB after Instr.3 Write Fuse cycle finish. program, unprogram. Reading means Fuse/Lock programmed.
delete note RCEN Fuse" this table. 11-40 11-40 11-41 figure remove "CLOCK INPUT", "XTAL1/PB3" arrow connecting them. last paragraph, replace "Either external clock applied XTAL1/PB3 device must clocked from internal RC-oscillator." "The device clocked from internal RC-oscillator." item Power-up sequence", replace "RESET" "RESET" (two occurrences) delete device programmed external clocking, apply clock pin. internal oscillator selected clock source, external clock source needs applied." table replace entries
0101 1000 1010 1100 xxxx xxxx 1011 111R xxxx xxxx xxxx xxxx
11-43
Read Lock Fuse Bits Write RCEN
12Sx xxxR
xxxx xxxx
Read Lock Fuse bits. programmed, unprogrammed. Write RCEN Fuse. program, unprogram.(1)
entry (Remove entry "Write RCEN Bit"):
Read Lock Fuse 0101 1000 xxxx xxxx xxxx xxxx
12Sx xxx0
Read Lock Fuse bit. programmed, unprogrammed.
remove notes RCEN Fuse" "When state RCEN changed, device must power cycled changes have effect." 11-44 Above Table "The period internal oscillator tCLCL voltage dependent shown "Typical characteristics", delete entries 1/tCLCL(VCC 4.0V), tCLCL(VCC 4.0V), 1/tCLCL(VCC 6.0V), tCLCL (VCC 6.0V),. Characteristics, replace entries:
11-45
Power Supply Current
Active MHz, Idle MHz, Power Down Enabled Power Down MHz(2), Disabled
25.0 20.0
entries
Power Supply Current
Active, Idle, Power Down, Enabled Power Down, Disabled
25.0 20.0
11-46 11-46 11-46
Remove sections External Clock Drive Waveforms External Clock Drive. first line Typical Characteristics, change "These data characterized, tested." "These figures tested during manufacturing.". last sentence second paragraph section Typical Characteristics, replace "The dominating factors operating voltage frequency" "The dominating factor operating voltage, frequency ATtiny22L also function operating voltage." Remove Figure Figure Remove Figure Remove Figure Register Summary, replace "11-page" "page". addition, TIMSK; replace "page 11-15" "page 1125", TIFR; replace "page 11-16" "page 11-26", MCUCR; replace "page 11-16" "page 11-26", MCUSR; replace "page 11-14" "page 11-24"
11-47 11-48 11-49 11-56
Data Book Updates Changes
Data Book Updates Changes
11-56 Register Summary, replace
WDTCR WDTO
($41)
WDP2
WDP1
WDP0
Page 11-30
($41) WDTCR WDTOE
WDP2
WDP1
WDP0
Page 11-30
11-57
CPSE SBRC SBRS SBIC SBIS
Instruction Summary under BRANCH INSTRUCTIONS, replace
Rd,Rr Compare, Skip Equal Skip Register Cleared Skip Register Skip Register Cleared Skip Register (Rr(b)=0) (Rr(b)=1) (P(b)=0) (R(b)=1) None None None None None
CPSE SBRC SBRS SBIC SBIS Rd,Rr Compare, Skip Equal Skip Register Cleared Skip Register Skip Register Cleared Skip Register (Rr(b)=0) (Rr(b)=1) (P(b)=0) (R(b)=1) None None None None None 1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
11-59
Replace Ordering Information
Power Supply 6.0V Speed (MHz) Ordering Code ATtiny22L-4PC ATtiny22L-4SC ATtiny22L-4PI ATtiny22L-4SI 6.0V ATtiny22-8PC ATtiny22-8SC ATtiny22-8PI ATtiny22-8SI Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Note:
speed grade refers maximum clock rate when using external clock drive. internal oscillator same nominal clock frequency speed grades."
following Ordering Information
Power Supply 6.0V Speed (MHz) Internal Osc. ~1MHz@5.0V Ordering Code ATtiny22L-1PC ATtiny22L-1SC ATtiny22L-1PI ATtiny22L-1SI Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C)
ATtiny28L/V
latest data sheet rev. 1062B-10/99. This data sheet printed data book.
Changes ATtinyL Data Sheet web:
None.
Data Book Updates Changes
Data Book Updates Changes
ATmega161/161L
latest data sheet rev. 1228A-08/99. data sheet printed data book rev. 1228A-05/99.
Changes ATmega161/161L data sheet:
Page: Change Add: 12-25 following note below table "note: BOOTRST fuse programmed, reset vector located program address $1e00, table page 12-98 details".
this code example below existing code example: When BOOTRST fuse programmed, most typical general program setup Reset Interrupt Vector Addresses are:
Address .org $002 $002 $004 $006 $008 $00a $00c $00e $010 $012 $014 $016 $018 $01a $01c $01e $020 $022 $024 $026 $028 $02a $02b $02c $02d $02e .org $1e00 $1e00 RESET Reset handler MAIN: r16,high(RAMEND); Main program start SPH,r16 r16,low(RAMEND) SPL,r16 <instr> EXT_INT0 EXT_INT1 EXT_INT2 TIM2_COMP TIM2_OVF TIM1_CAPT Labels Code Comments Reset located $1e000 IRQ0 Handler IRQ1 Handler IRQ2 Handler Timer2 Compare Handler Timer2 Overflow Handler Timer1 Capture Handler
TIM1_COMPA Timer1 CompareA Handler TIM1_COMPB Timer1 CompareB Handler TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC; UART_RXC0 UART_RXC1 UART_DRE0 UART_DRE1 UART_TXC0 UART_TXC1 EE_RDY ANA_COMP Timer1 Overflow Handler Timer0 Compare Handler Timer0 Overflow Handler Transfer Complete Handler UART0 Complete Handler UART1 Complete Handler UDR0 Empty Handler UDR1 Empty Handler UART0 Complete Handler UART1 Complete Handler EEPROM Ready Handler Analog Comparator Handler
12-35
Table remove this note: "Note: When changing ISC11/ISC10 bits, INT1 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Table remove this note: "Note: When changing ISC01/ISC00 bits, INT0 must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Interrupt Sense Control description this text: "When changing ISC2 bit, interrupt occur. Therefore, recommended first disable INT2 clearing Interrupt Enable GIMSK register. Then, ISC2 changed. Finally, INT2 interrupt flag should cleared writing logical Interrupt Flag GIFR register before interrupt re-enabled."
12-36
Power Save Mode section, paragraph asynchronous timer clocked asynchronously, Power Down Mode recommended instead Power Save Mode because contents registers asynchronous timer should considered undefined after wake Power Save Mode even Replace last paragraph page, "When asynchronous operation selected, oscillator Timer/Counter2 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. Therefore, content Timer/Counter2 registers must considered lost after wakeup from power down, unstable clock signal. user advised wait least second before using Timer/Counter2 after power-up wake-up from power down." "When asynchronous operation selected, oscillator Timer/Counter2 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. user advised wait least second before using Timer/Counter2 after power-up wake-up from power down. contents Timer/Counter2 registers must considered lost after wake-up from power down unstable clock signal upon start-up, regardless whether oscillator clock signal applied TOSC pin."
12-46
12-55 12-56
note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." EEPROM Read/Write Access description, replace second sentence "The write access time range depending voltages" "The write access time range depending frequency oscillator used time EEPROM access time. table details." last sentence EEPROM Read/Write Access description, replace "When EEPROM read written, halted clock cycles before next instruction executed." "When EEPROM written, halted clock cycles before next instruction executed. When EEPROM read, halted four clock cycles before next instruction executed." EEPROM Control Register description, change initial value EEWE from "X".
12-57
description EEWE: EEPROM write Enable, replace "When write access time (typically 2.7V) elapsed, "When write access time elapsed, Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." Under "Prevent EEPROM corruption", note replace text: "Flash memory updated CPU, will subject corruption." "Flash memory updated unless boot loader software supports writing FLASH Boot Lock bits configured that writing FLASH memory from allowed. Boot Loader Support page 12-98 details."
Data Book Updates Changes
Data Book Updates Changes
text table below EEPROM Read/Write section: RC-oscillator used time EEPROM write access. table typical programming time listed EEPROM access from CPU."
Table
Symbol EEPROM write (from CPU) Note: Number RCosc. cycles 2048 programming time programming time
2.0ms
3.4ms
"Typical characteristics" find typical RC-osc. frequency.
12-72 12-79 12-81 12-87 12-89 12-94 12-98
Analog Comparator Control Status Register description, change initial value from "N/A". Also change Read/Write status AINBG from "R/W". Port Input Pins Address PINA description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINC description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINE description, change Initial Values from "Hi-Z" "N/A". Replace table
BLB02 BLB01 Protection restrictions SPM, accessing Application section allowed write Application section allowed write Application section, executing from Boot Loader section allowed read from Application section executing from Boot Loader section allowed read from Application section
BLB0 mode
12-98
Replace table
BLB12 BLB11 Protection restrictions SPM, accessing Boot Loader section allowed write Boot Loader section allowed write Boot Loader section, executing from Application section allowed read from Boot Loader section executing from Application section allowed read from Boot Loader section
BLB1 mode
12-99
section describing "Self-programming Flash", replace "The halted both during page erase during page write" "The halted both during page erase during page write SPMEN SPMCR register will auto-cleared. future compatibility, however, recommended that user software verifies that SPMEN cleared before starting page-erase, page-write, writing lock-bits com-
mand. code example below. essential that page address used both page erase page write operation addressing same page." 12-99 this text bottom "Perform page write" sub-section: "When page write operation completed, pointer will point first word successive page."
sbrc rjmp r16,SPMCR read SPMCR register r16,SPMEN Wait SPMEN cleared (indicates that previous write operation completed) Wait cleared, keep waiting r16,(1<<PGWRT) (1<<SPMEN) previous writing completed, next erase SPMCR,r16 output register start erase operation
Code example:
Wait:
12-102 Replace table
Memory Lock Bits mode BLB0 mode BLB1 mode BLB02 BLB12 BLB01 BLB11 restrictions SPM, accessing Boot Loader section allowed write Boot Loader section allowed write Boot Loader section, executing from Application section allowed read from Boot Loader section executing from Application section allowed read from Boot Loader section restrictions SPM, accessing Application section allowed write Application section allowed write Application section, executing from Boot Loader section allowed read from Application section executing from Boot Loader section allowed read from Application section memory lock features enabled Further programming Flash EEPROM disabled parallel serial programming mode. Fuse bits locked both serial parallel programming mode.(1) Further programming verification Flash EEPROM disabled parallel serial programming mode. Fuse bits locked both serial parallel programming mode.(1) Protection Type
12-111 Replace following parameters table these values:
tWLRH tWLRH_CE tWLRH_FLASH
RDY/BSY High RDY/BSY High Chip Erase RDY/BSY High Write Flash
Data Book Updates Changes
Data Book Updates Changes
12-113 Replace table
Symbol tWD_FLASH tWD_EEPROM Minimum Wait Delay
this table: Table Minimum wait delay after chip erase command
Symbol tWD_ERASE Minimum Wait Delay
12-114 Replace "Write Fuse Bits" table
Write Fuse Bits 1010 1100 101x xxxx xxxx xxxx 1D1B A987 bits program, unprogram
12-116: Replace below characteristics:
VACIO
Analog Comparator Input Offset Voltage
VACIO
Analog Comparator Input Offset Voltage
12-123 this text: "The characterization data tested during manufacturing.". 12-129 Register summary, replace rows TIMSK TIFR
($59) ($58) TIMSK TIFR TOIE1 TOV1 OCIE1A OCF1A OCIE1B OCF1B TOIE2 TOV2 TICIE1 ICF1 OCIE2 OCFI2 TOIE0 TOV0 OCIE0 OCIF0 page 12-32 page 12-33
12-129 Register summary, replace "12-12-xx" "12-xx".
ATmega603/603/L ATmega103/103L
latest data sheet rev. 0945E-12/99. data sheet printed data book rev. 0945D-06/99.
Changes ATmega103/103L data sheet
None.
Changes ATmega103/103L section data book
Page: Change Add: 13-5 Some text symbols outside visible figure frame. complete figure given below.
Figure ATmega603/103 Block Diagram
PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA PORTA DRIVER/BUFFERS PORTC DRIVERS
ANALOG
AGND AREF INTERNAL OSCILLATOR OSCILLATOR
XTAL1
XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TOSC2
OSCILLATOR
PROGRAM FLASH
SRAM
CONTROL REGISTER
TIMING CONTROL
TOSC1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
RESET
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
UART
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS
Data Book Updates Changes
Data Book Updates Changes
13-7 Replace description AVCC, "This supply voltage Converter. should externally connected low-pass filter. page 13-68 details operation ADC" "Supply voltage PortF, including ADC. must connected when used ADC. Noise Canceling Techniques page 13-78 details when using ADC" description PEN, delete "low-voltage". Figure containing "+1" input summation operator. Table remove this note: "Note: X=7, When changing ISCX1/ISCX0 bits, interrupt must disabled clearing Interrupt Enable GIMSK register. Otherwise interrupt occur when bits changed." Power Save Mode section, paragraph asynchronous timer clocked asynchronously, Power Down Mode recommended instead Power Save Mode because contents registers asynchronous timer should considered undefined after wake Power Save Mode even 0.". line number from bottom, delete from 0|". Replace last paragraph page, "When asynchronous operation selected, oscillator Timer/Counter0 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. Therefore, content Timer/Counter0 registers must considered lost after wake-up from power down, unstable clock signal. user advised wait least second before using Timer/Counter0 after power-up wake-up from power down." "When asynchronous operation selected, 32kHz oscillator Timer/Counter0 always running, except power down mode. After power reset wake-up from power down, user should aware fact that this oscillator might take long second stabilize. user advised wait least second before using Timer/Counter0 after power-up wake-up from power down. contents Timer/Counter0 registers must considered lost after wake-up from power down unstable clock signal upon start-up, regardless whether oscillator clock signal applied TOSC pin." 13-52 After "This shown Table 21", paragraph "Note: compare register contains value prescaler (CS12.CS10 001), output will produce pulse all, because upcounting down-counting values reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches TOP-value, making oneperiod pulse." note Table avoid unintentional resets, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select." Bit1 EEWE: EEPROM Write Enable description, change Write logical EEMWE EECR" Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle)." Replace figure
13-7 13-19 13-33
13-36
13-40 13-44
13-54 13-55
13-59
Figure Transfer Format with CPHA DORD
CYCLE (FOR REFERENCE) (CPOL=0) (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SLAVE) SAMPLE
defined normally character just received.
Figure Transfer Format with CPHA DORD
CYCLE (FOR REFERENCE) (CPOL=0) (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SLAVE)
SAMPLE
defined normally previously transmitted character.
13-67 13-74
Analog Comparator Control Status Register ACSR, change initial value from "X". page, note "Note: read followed write, opposite, there extra insertion waitstates in-between. Since such short time releasing difficult obtain without making contention, user might insert between consecutive read write operation external RAM. Port Input Pins Address PINA description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINB description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PIND description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINE description, change Initial Values from "Hi-Z" "N/A". Port Input Pins Address PINF description, change Initial Values from "Hi-Z" "N/A". Replace table Supply voltage during programming with following:
13-77 13-79 13-86 13-89 13-93 13-95 Table
Part
Serial programming 5.0V 3.6V
Parallel programming 5.0V 5.0V
ATmega103 ATmega103L
13-108 Table Characteristics, replace entry
Data Book Updates Changes
Data Book Updates Changes
VACIO
Analog Comp Input Offset
Analog Comp Input Offset VCC/2
VACIO
13-110 table "Data Memory Charactheristics, 2.7-3.6 Volts, Wait State" replace entry:
tAVLLC Address Valid 75.0 0.5tCLCL-50.0(1)
tAVLLC Address Valid 60.0 0.5tCLCL-65.0(1)
13-112 first line, change "These data characterized, tested." "These figures tested during manufacturing.". 13-123 Register Summary, replace entry
($26) ADCSR ADES ABSY ADRF ADIF ADIE ADPS2 ADPS1 ADPS0 page 13-72
entry
($26) ADCSR ADEN ADSC ADIF ADIE ADPS2 ADPS1 ADPS0 page 13-72
Instruction
latest instruction manual rev. 0856B-06/99. instruction manual printed data book rev. 0856B-06/99.
Changes Instruction Manual:
Page: Change Add: 14-. MUL, MULS, MULSU, FMUL, FMULS, FMULSU, EIJMP, JMP, EICALL, CALL, MOVW, LDD, STD, LDS, STS, ELPM, SPM, PUSH, instructions implemented devices. following note last column their respective rows instruction summary, last paragraph before Operation description each instruction description: "This instruction available devices. Refer device specific instruction summary." Some variants instructions implemented devices. following note last column their respective rows instruction summary, last paragraph before Operation description each instruction description: "Not variants this instruction available devices. Refer device specific instruction summary."
14-.
14-11, 14-83 Some variants instruction implemented devices. Furthermore, instruction implemented AT90S1200 device. following note last column instruction summary, last paragraph before Operation description instruction description: "Not variants instruction available devices. Refer device specific instruction summary. instruction implemented AT90S1200 device." 14-10 Operation column row, change (k)" "(k)
14-11, 14-65, 14-66 ESPM instruction required implemented, instruction access entire program memory (see below). Remove ESPM description. 14-63 ELPM description, this paragraph after first paragraph: "Devices with Self-Programming capability ELPM instruction read fuse lock values. Refer device documentation detailed description." FMUL description, insert following paragraph after paragraph starting with "Let (N.Q) denote fractional number": "The (1.7) format most commonly used with signed numbers, while FMUL performs unsigned multiplication. This instruction therefore most useful calculating partial products when performing signed multiplication with 16-bit inputs (1.15) format, yielding result (1.31) format. Note: result FMUL operation suffer from complement overflow interpreted number (1.15) format. multiplication before shifting must taken into account, found carry bit. following example." Replace example with following example (which illustrates intended usage):
DESCRIPTION Signed fractional multiply 16-bit numbers with 32-bit result. r19:r18:r17:r16 r23:r22 r21:r20 USAGE fmuls16x16_32: fmuls movw r23, r19:r18, r1:r0 ;((signed)ah (signed)bh)
14-67
Data Book Updates Changes
Data Book Updates Changes
fmul movw fmulsu fmulsu r22, r18, r17:r16, r1:r0 r23, r19, r17, r18, r19, r21, r19, r17, r18, r19, ;((signed)bh ;((signed)ah ;(al
14-68
FMULS description, insert following paragraph before Operation description: "Note that when multiplying 0x80 (-1) with 0x80 (-1), result shift operation 0x8000 (-1). shift operation thus gives two's complement overflow. This must checked handled software." Change "FMUL" Syntax description "FMULS".
14-69
FMULSU description, insert following paragraph after paragraph starting with "Let (N.Q) denote fractional number": "The (1.7) format most commonly used with signed numbers, while FMULSU performs multiplication with unsigned signed input. This instruction therefore most useful calculating partial products when performing signed multiplication with 16-bit inputs (1.15) format, yielding result (1.31) format. Note: result FMULSU operation suffer from complement overflow interpreted number (1.15) format. multiplication before shifting must taken into account, found carry bit. following example." Replace example with following example (which illustrates intended usage):
DESCRIPTION Signed fractional multiply 16-bit numbers with 32-bit result. USAGE r19:r18:r17:r16 r23:r22 r21:r20
fmuls16x16_32: fmuls movw fmul movw fmulsu fmulsu r23, r19:r18, r1:r0 r22, r18, r17:r16, r1:r0 r23, r19, r17, r18, r19, r21, r19, r17, r18, r19, ;((signed)bh ;((signed)ah ;(al ;((signed)ah (signed)bh)
14-75
LD(X) description, change last sentence third paragraph from "The RAMPX register area updated parts with more than bytes data space." "The RAMPX register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices." LD(Y) description, change last sentence third paragraph from "The RAMPY register area updated parts with more than bytes data space." "The RAMPY register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices." LD(Z) description, last three sentences third paragraph incorrect, starting with "The RAMPZ register area updated parts with more than bytes data space, that displacement.". Change these sentences "The RAMPY register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices." description, this paragraph after first paragraph: "Devices with Self-Programming capability instruction read fuse lock values. Refer device documentation detailed description." MULSU description, replace example with following example:
14-77
14-79
14-83
14-90
DESCRIPTION Signed multiply 16-bit numbers with 32-bit result. r19:r18:r17:r16 r23:r22 r21:r20 USAGE
muls16x16_32: muls movw movw mulsu mulsu r23, r19:r18, r1:r0 r22, r17:r16, r1:r0 r23, r19, r17, r18, r19, r21, r19, r17, r18, r19, (signed)bh (signed)ah (signed)ah (signed)bh
14-124 description, sentence "When writing program memory, register used page word address, R1:R0 register pair used data", footnote determines instruction high byte, determines instruction byte." 14-124 description, limited first program memory. This correct, access entire program memory, uses RAMPZ register together with register. Consequently: first paragraph, change last sentence "This instruction address entire program memory." first paragraph, change "the register" "the RAMPZ registers". Operation description, change "(Z) "(RAMPZ:Z)".
Data Book Updates Changes
Data Book Updates Changes
compatibility with future devices, recommended poll SPMEN SPMCR register before executing instruction. Replace code example with following (which shows code parts with page write, includes verify-loop):
;This example shows write page devices with page write routine writes page data from Flash first data location pointed pointer first data location Flash pointed pointer
error handling included routine must placed inside boot space ;.equ write_page: ;page erase call spmcrval, (1<<PGERS) (1<<SPMEN) do_spm least do_spm routine) storing restoring registers included routine register usage optimized expense code size registers used: temp1, temp2, looplo, loophi, spmcrval
PAGESIZEB PAGESIZE*2;PAGESIZEB page size BYTES, words
.org SMALLBOOTSTART
;transfer data from Flash page buffer wrloop: call adiw sbiw brne looplo, low(PAGESIZEB) loophi, high(PAGESIZEB) spmcrval, (1<<SPMEN) do_spm ZH:ZL, loophi:looplo, wrloop ;use subi PAGESIZEB<=256 ;init loop variable ;not required PAGESIZEB<=256
;execute page write subi sbci call low(PAGESIZEB);restore pointer high(PAGESIZEB) spmcrval, (1<<PGWRT) (1<<SPMEN) do_spm ;not required PAGESIZEB<=256
;read back check, optional subi sbci rdloop: cpse sbiw brne looplo, low(PAGESIZEB) loophi, high(PAGESIZEB) low(PAGESIZEB) high(PAGESIZEB) error loophi:looplo, rdloop ;use subi PAGESIZEB<=256 ;init loop variable ;not required PAGESIZEB<=256 ;restore pointer
;return do_spm: ;input: spmcrval determines action ;disable interrupts enabled, store status ;check previous complete wait: sbrc rjmp ;restore SREG enable interrupts originally enabled) SREG, temp2 temp1, SPMCR temp1, SPMEN wait SPMCR, spmcrval temp2, SREG
;SPM timed sequence
14-125 ST(X) description, change last sentence third paragraph from "The RAMPX register area updated parts with more than bytes data space." "The RAMPX register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices." 14-127 ST(Y) description, change last sentence third paragraph from "The RAMPY register area updated parts with more than bytes data space." "The RAMPY register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices." 14-129 ST(Z) description, last three sentences third paragraph incorrect, starting with "The RAMPZ register area updated parts with more than bytes data space, displacement.". Change these sentences "The RAMPY register area updated parts with more than bytes data space more than bytes program memory, displacement added entire 24-bit address such devices."
Data Book Updates Changes

8-Bit Microcontroller Data Book Updates Changes Overview data she

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