bytes In-System Reprogrammable Falsh (ATmega603/L) Serial Interface Pr

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bytes In-System Reprogrammable Falsh (ATmega603/L) Serial Interface Pr

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Utilizes AVR® Enhanced RISC Architecture Powerful Instructions Most Single Clock Cycle Execution 128K bytes In-System Reprogrammable Flash (ATmega103/L)
bytes In-System Reprogrammable Falsh (ATmega603/L) Serial Interface Program Downloading Endurance: 1,000 Write/Erase Cycles bytes EEPROM (ATmega103/L) bytes EEPROM (ATmega603/L) Endurance: 100,000 Write/Erase Cycles bytes Internal SRAM General Purpose Working Registers Peripheral Control Registers Programmable Lines, Output Lines, Input Lines Programmable Serial UART Serial Interface Supply 6.0V (ATmega603L/ATmega103L) 6.0V (ATmega603/ATmega103) Fully Static Operation (ATmega603/ATmega103) (ATmega603L/ATmega103L) MIPS Throughput with Separate Oscillator 8-Bit Timer/Counters with Separate Prescaler 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes Dual 10-Bit Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator 8-Channel, 10-Bit Power Idle, Power Save Power Down Modes Software Selectable Clock Frequency Programming Lock Software Security
8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash ATmega603 ATmega603L ATmega103 ATmega103L Preliminary ATmega103/L ATmega103/L
Configuration
TQFP
Rev. 0945AS-05/98
Block Diagram
Figure ATmega603/103 Block Diagram
PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA PORTA DRIVER/BUFFERS PORTC DRIVERS
ANALOG
AGND AREF INTERNAL OSCILLATOR OSCILLATOR
XTAL1
XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TOSC2
OSCILLATOR
PROGRAM FLASH
SRAM
CONTROL REGISTER
TIMING CONTROL
TOSC1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
RESET
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
UART
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS
Description
ATmega603/103 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega603/103 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed. core based enhanced RISC architecture that combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture
more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega603/103 provides following features: 64K/128K bytes In-system Programmable Flash, 2K/4K bytes EEPROM, bytes SRAM, general purpose lines, Input lines, Output lines, general purpose working registers, flexible timer/counters with compare modes PWM, UART, programmable Watchdog Timer with internal oscillator, serial port three software selectable power saving modes. Idle Mode stops while allowing SRAM, timer/counters, port interrupt system continue functioning. Power Down mode saves register contents freezes oscillator, disabling other chip functions until next
ATmega603/L ATmega103/L
ATmega603/L ATmega103/L
interrupt hardware reset. Power Save mode, timer oscillator continues run, allowing user maintain timer base while rest device sleeping. device manufactured using Atmel's high-density non-volatile memory technology. on-chip Flash allows program memory reprogrammed in-system through serial interface conventional nonvolatile memory programmer. combining 8-bit RISC with large array Flash monolithic chip, Atmel ATmega603/103 powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATmega603/103 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, in-circuit emulators, evaluation kits. Port (PB7.PB0) Port 8-bit bi-directional pins with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port (PC7.PC0) Port 8-bit Output port. Port output buffers sink Port also serves Address output when using external SRAM. Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port (PF7.PF0) Port 8-bit Input port. Port also serves analog inputs ADC. RESET input. this machine cycles while oscillator running resets device. XTAL1 Input inverting oscillator amplifier input internal clock operating circuit. XTAL2 Output from inverting oscillator amplifier TOSC1 Input inverting Timer/Counter oscillator amplifier TOSC2 Output from inverting Timer/Counter oscillator amplifier External SRAM Write Strobe. External SRAM Read Strobe. Address Latch Enable used when External Memory enabled. strobe used latch low-order address bits) into address latch during first access cycle, AD0-7 pins used data during second access cycle.
Comparison Between ATmega ATmega
ATmega603 bytes Downloadable Flash, bytes EEPROM, bytes internal SRAM. ATmega603 does have ELPM instruction. ATmega103 128K bytes Downloadable Flash, bytes EEPROM, bytes internal SRAM. ATmega103 ELPM instruction, necessary reach upper half Flash memory constant table lookup. Table summarizes different memory sizes devices. Table Memory Size Summary
Part ATmega603 ATmega103 Flash bytes 128K bytes EEPROM bytes bytes SRAM bytes bytes
Descriptions
Supply voltage Ground Port (PA7.PA0) Port 8-bit bi-directional port. Port pins provide internal pull-up resistors (selected each bit). Port output buffers sink drive displays directly. When pins used inputs externally pulled low, they will source current internal pull-up resistors activated. Port serves Multiplexed Address/Data when using external SRAM.
AVCC This supply voltage Converter. should externally connected low-pass filter. page details operation ADC. AREF This analog reference input converter. operations, voltage range AGND AVCC must applied this pin. AGND board separate analog ground plane, this should connected this ground plane. Otherwise, connect GND. This programming enable low-voltage serial programming mode. holding this during poweron reset, device will enter serial programming mode.
Figure External Clock Drive Configuration
XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
ATmega603/103 Architectural Overview
fast-access register file contains 8-bit general purpose working registers with single clock cycle access time. This means that during single clock cycle, (Arithmetic Logic Unit) operation executed. operands output from register file, operation executed, result stored back register file clock cycle. registers used three 16-bit indirect address register pointers Data Space addressing enabling efficient address calculations. three address pointers also used address pointer constant table look function. These added function registers 16-bit X-register, Y-register Z-register. supports arithmetic logic functions between registers between constant register. Single register operations also executed ALU. Figure shows ATmega603/103 Enhanced RISC microcontroller architecture. addition register operation, conventional memory addressing modes used register file well. This enabled fact that register file assigned lowermost Data Space addresses, allowing them accessed though they were ordinary memory locations. memory space contains addresses peripheral functions Control Registers, Timer/Counters, A/D-converters, other functions. Memory accessed directly, Data Space locations following those register file, $5F.
Crystal Oscillator
XTAL1 XTAL2 input output, respectively, inverting amplifier which configured on-chip oscillator, shown Figure Either quartz crystal ceramic resonator used. drive device from external clock source, XTAL2 should left unconnected while XTAL1 driven shown Figure Timer Oscillator pins, OSC1 OSC2, crystal connected directly between pins. external capacitors needed. oscillator optimized with 32,768Hz watch crystal. external clock signal applied this goes through same amplifier having bandwidth 256kHz. external clock signal should therefore interval 256kHz. Figure Oscillator Connections
XTAL2
XTAL1
ATmega603/L ATmega103/L
ATmega603/L ATmega103/L
Figure ATmega603/103 Enhanced RISC Architecture
ATmega103 Architecture
Data 8-bit
32K/64K Program Memory
Program Counter
Status Test
Instruction Register
General Purpose Registers Peripherals
Instruction Decoder
IndirectAddressing
DirectAddressing
Control Lines
Data SRAM
2K/4K EEPROM
uses Harvard architecture concept with separate memories buses program data. program memory executed with single level pipelining. While instruction being executed, next instruction pre-fetched from program memory. This concept enables instructions executed every clock cycle. program memory in-system programmable Flash memory. With exceptions, instructions have single 16-bit word format, meaning that every program memory address contains single 16-bit instruction. During interrupts subroutine calls, return address program counter (PC) stored stack. stack effectively allocated general data SRAM, consequently stack size only limited total SRAM size usage SRAM. user programs must initialize reset routine (before subroutines interrupts executed). 16-bit stack pointer read/write accessible space. 4000 bytes data SRAM easily accessed through five different addressing modes supported architecture.
flexible interrupt module control registers space with additional global interrupt enable status register. different interrupts have separate interrupt vector interrupt vector table beginning program memory. different interrupts have priority accordance with their interrupt vector position. lower interrupt vector address, higher priority. memory spaces architecture linear regular memory maps.
ATmega603.
ATmega603/103 Register Summary
Address ($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($47) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2B) ($2A) ($29) ($28) ($27) ($26) ($25) ($24) ($23) ($22) ($21) ($20) Name SREG XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UBRR ACSR ADMUX ADCSR ADCH ADCL PORTE DDRE PINE PINF Bit7 SP15 XDIVEN ISC71 INT7 INTF7 OCIE2 OCF2 Bit6 SP14 XDIV6 ISC70 INT6 INTF6 TOIE2 TOV2 PWM0 Bit5 SP13 XDIV5 ISC61 INT5 INTF5 TICIE1 ICF1 COM01 Bit4 SP12 XDIV4 ISC60 INT4 INTF4 OCIE1A OCF1A COM00 Bit3 SP11 XDIV3 ISC51 INT3 OCIE1B OCF1B CTC0 Bit2 SP10 XDIV2 ISC50 INT2 TOIE1 TOV1 CS02 Bit1 XDIV1 ISC41 INT1 OCIE0 OCF0 EXTRF CS01 Bit0 XDIV0 RAMPZ0 ISC40 INT0 TOIE0 TOV0 PORF CS00 Page page page page page page page page page page page page page page page page COM1B0 CTC1 TCN0UB CS12 OCR0UB PWM11 CS11 TCR0UB PWM10 CS10 page page page page page page page page page page page COM20 CTC2 CS22 CS21 CS20 page page page WDTOE EEAR11 WDP2 EEAR10 WDP1 EEAR9 WDP0 EEAR8 page page page page PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ADRF ADC5 PORTE5 DDE5 PINE5 PINF5 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 PORTD4 DDD4 PIND4 MSTR RXEN ADIF ADC4 PORTE4 DDE4 PINE4 PINF4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 PORTD3 DDD3 PIND3 CPOL TXEN ACIE ADIE ADC3 PORTE3 DDE3 PINE3 PINF3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 PORTD2 DDD2 PIND2 CPHA CHR9 ACIC MUX2 ADPS2 ADC2 PORTE2 DDE2 PINE2 PINF2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1 PORTE1 DDE1 PINE1 PINF1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 PORTD0 DDD0 PIND0 SPR0 TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0 PORTE0 DDE0 PINE0 PINF0 page page page page page page page page page page page page WCOL TXCIE ABSY ADC6 PORTE6 DDE6 PINE6 PINF6 page page page page page page page page page page page page page page page COM1B1
Timer/Counter0 Bit) Timer/Counter0 Output Compare Register COM1A1 ICNC1 COM1A0 ICES1
Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte PWM2 COM21 Timer/Counter2 Bit) Timer/Counter2 Output Compare Register EEPROM Address Register EEPROM Data Register PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 PORTD7 DDD7 PIND7 Data Register SPIF SPIE RXCIE ADES ADC7 PORTE7 DDE7 PINE7 PINF7 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 PORTD6 DDD6 PIND6
UART Data Register
UART Baud Rate Register
ATmega603/L ATmega103/L
ATmega603/L ATmega103/L
ATmega603/103 Instruction Summary
Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC LOGIC INSTRUCTIONS ADIW SUBI SBCI SBIW ANDI RJMP IJMP RCALL ICALL CALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rdl,K Rdl,K Rd,K Rd,K Registers with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Relative Jump Indirect Jump Direct Jump Relative Subroutine Call Indirect Call Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None
Rdh:Rdl Rdh:Rdl
Rdh:Rdl Rdh:Rdl
($FF
BRANCH INSTRUCTIONS
STACK
STACK
(Rr(b)=1) (P(b)=1) (P(b)=0)
(Rr(b)=0)
(SREG(s) then PCPC+k then then
(SREG(s) then PCPC+k
then then then then
then
then then then then
then then
then
then then then
then
ATmega603/103 Instruction Summary (Continued)
DATA TRANSFER INSTRUCTIONS ELPM() PUSH SWAP BSET BCLR SLEEP Rd,Y+q Y+q,Rr Z+q,Rr Extended Load Program Memory Move Between Registers Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Port Port Push Register Stack Register from Stack Register Clear Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG Clear Half Carry Flag SREG Operation Sleep Watchdog Reset (see specific descr. Sleep function) (see specific descr. timer) (Z+RAMPZ) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None None None None
(X), (Y), (Z), STACK STACK
I/O(P Rd(n+1) Rd(n), Rd(0) I/O(P
BIT-TEST INSTRUCTIONS
Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(n) Rd(n+1), n=0.6 SREG(s) Rr(b) SREG(s) Rd(b) Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Rd(n) Rd(n+1), Rd(7)
Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0)
ATmega603/L ATmega103/L
ATmega603/L ATmega103/L
Ordering Information
Speed (MHz) Power Supply 6.0V Ordering Code ATmega603L-4AC Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
ATmega603L-4AI
6.0V
ATmega603-6AC
ATmega603-6AI
6.0V
ATmega103L-4AC
ATmega103L-4AI
6.0V
ATmega103-6AC
ATmega103-6AI
Package Type 64-Lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP)
ATmega603/L ATmega103/L
Packaging Information
64A, 64-Lead, Very Thin (1.0 Plastic Gull Wing Quad Flat Package (VQFP) Dimensions Millimeters (Inches)*
16.25(0.640) 15.75(0.620)
0.45(0.018) 0.30(0.012) 0.80(0.031)
14.10(0.555) 13.90(0.547) 0.20(0.008) 0.10(0.004) 0.45(0.018) 0.75(0.030) 0.05(0.002) 0.15(0.006)
1.20 (.047)
*Controlling dimension: millimeters

bytes In-System Reprogrammable Falsh (ATmega603/L) Serial Interface Pr

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