1992 1992 Advanced Micro Devices, Inc. Advanced Micro Devices res
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Am79C960 PCnet-ISA
1992
1992 Advanced Micro Devices, Inc. Advanced Micro Devices reserves right make changes products without notice order improve design performance characteristics.
This publication neither states implies warranty kind, including limited implied warrants merchantability fitness particular application. assumes responsibility circuitry other than circuitry product. information this publication believed accurate respects time publication, subject change without notice. assumes responsibility errors omissions, disclaims responsibility consequences resulting from information included herein. Additionally, assumes responsibility functioning undescribed features parameters. Product names used this publication identification purposes only trademarks their respective companies.
Trademarks trademark Advanced Micro Devices, Inc. ILACC, PAL, PCnet-ISA, TPEX trademarks Advanced Micro Devices, Inc.
CHAPTER
Table Contents
INTRODUCTION Chapter SYSTEM CONSIDERATIONS Master Mode 1.1.1 Hardware Considerations 1.1.2 Register Addressing 1.1.3 Boot PROM 1.1.4 Hardware Compatibility Issues 1.1.5 Bandwidth Latency Requirements Shared-Memory Mode 1.2.1 Hardware Considerations 1.2.2 Register Addressing 1.2.3 Boot PROM 1.2.4 Shared Memory SRAM 1.2.5 Hardware Compatibility Issues Chapter NETWORK CHARACTERISTICS Network Operation 2.1.1 Collision Fragment Runt Packet Rejection 2.1.2 Auto Retransmit Deletion Collision 2.1.3 Programmable Transmit Start Threshold 2.1.4 Programmable Burst Size 2.1.5 DMAPLUS 2.1.6 Activity Timer 2.1.7 Programmable Transmit Request 2.1.8 Programmable Receive Request 2.1.9 Programmable Memory Read Write Active Time 2.1.10 Pin-selectable 16-bit 2.1.11 Transmit Padding 2.1.12 Receive Frame Stripping Network Interfaces 2.2.1 Twisted-Pair (10BASE-T) Interface 2.2.2 Attachment Unit Interface 2.2.3 Embedded 10BASE2 Medium Attachment Unit (MAU) 2.2.4 Automatic Selection Chapter POWER SAVING SECURITY FEATURES Power Saving 3.1.1 Sleep 3.1.2 Auto-Wake Remote Wake (Security) 3.2.1 EADI Standard Operation 3.2.2 EADI Security Operation Chapter CONSIDERATIONS MOTHERBOARD LAYOUT Signal Routing Ethernet Placement Ground Power Planes Dedicated Ethernet Components 4.3.1 Crystal Oscillator 4.3.2 Ethernet Address PROM Table Contents
Bypass Capacitors Other Considerations Chapter SOFTWARE CONSIDERATIONS NE2100 Compatibility PCnet-ISA Changes 5.2.1 Loopback 5.2.2 Register Differences 5.2.2.1 CSR3 5.2.2.2 Reserved Bits 5.2.3 Stopping PCnet-ISA 5.2.3.1 Register Access Port 5.2.4 Errors 5.2.5 Software Reset PCnet-ISA Enhancements 5.3.1 General 5.3.1.1 Accessing Internal Registers 5.3.1.2 Buffer Sizes 5.3.1.3 Masking Interrupt Bits 5.3.1.4 Dynamic Generation 5.3.1.5 Automatic Generation Stripping 5.3.1.6 Missed Packet Count 5.3.1.7 Receive Collision Count 5.3.1.8 Accepting Runt Packets 5.3.1.9 Chip 5.3.2 Interface 5.3.2.1 Timing 5.3.2.2 Base Address Programming 5.3.2.3 Automatic Wake-Up Support 5.3.3 Network Interface 5.3.3.1 TSEL 5.3.3.2 T-MAU 5.3.3.3 T-MAU Control 5.3.3.4 Programmable LEDs 5.3.3.5 External Address Detection 5.3.4 Network Software Procedures 5.3.4.1 Initialization 5.3.4.2 Transmission Reception 5.3.4.3 Changing Modes 5.3.4.4 Loopback 5.3.5 Network Performance Tuning 5.3.5.1 FIFO Watermark Selection 5.3.5.2 Burst Length Control 5.3.5.3 Disabling Descriptor Polling 5.3.5.4 Disabling Transmission Two-part Deferral 5.3.5.5 Alternate Backoff Algorithm Programmable Registers Chapter JUMPERLESS SOLUTION Description Logic Equations Code Examples GLOSSARY APPENDIX PCnet-ISA COMPATIBLE MEDIA INTERFACE MODULES
Table Contents
INTRODUCTION
Introduction
This section provided overview IEEE 802.3/Ethernet. intended exhaustive study technology, rather primer anyone familiar with concepts Ethernet IEEE 802.3-compatible network. Those already familiar with 802.3/Ethernet will probably want skip this section. This tutorial information included within technical manual PCnet-ISAchip because nature device itself. PCnet-ISA chip effectively integrated Ethernet adapter card intended primarily PC/AT-compatible Industry Standard Architecture (ISA) systems. Because integrates fixed logic entire adapter, PCnet-ISA chip offers extremely simple solution Ethernet connectivity personal computer motherboard, well very-low-cost adapter. currently shipped with Ethernet installed motherboard, this section will assist designers gaining understanding this network technology. section also provides brief historical perspective Ethernet, clarifies terminology used, identifies advantages 10BASE-T.
Introduction
10BASE-T TECHNOLOGY BENEFITS Topology
Traditional Ethernet (802.3, 10BASE5)1 Cheapernet (802.3, 10BASE2)2 coaxial-wired systems. Coaxial cable provides linear which nodes connected. Signaling uses current sink technique, with center conductor used signal shield ground reference. Figures
maximum Coaxial maximum
Cable Node
16850A-001A
Figure 10BASE5 Coaxial Topology
maximum Coaxial Cable Node
Node with Integral 10BASE2
16850A-002A
Figure 10BASE2 Coaxial Topology Twisted-Pair Ethernet (802.3 10BASE-T)3 uses standard voice-grade telephone cable (22-26 gauge) that employs separate transmit receive pairs wires). system uses star topology. center star (Figure repeater. repeater hub) performs signal amplitude timing restoration. takes incoming stream repeats other ports connected (but back originating port). this sense, repeater acts "logical coax," that node connected network will another's transmission. Differential signaling employed, with pair acting transmit path other receive.
ISO/IEC 8802-3 :1990 (E); ANSI/IEEE 802.3-1990 Edition, Section ISO/IEC 8802-3 :1990 (E); ANSI/IEEE 802.3-1990 Edition, Section ISO/IEC 8802-3 :1990 (E); ANSI/IEEE 802.3-1990 Edition, Section 13/14.
Introduction
Repeater Logic Repeater 10BASE-T Cable Cable Node Node with Integral 10BASE-T
16850A-003A
Figure 10BASE-T Twisted-Pair Star Topology Collision Detection 802.3-based networks, devices permitted listen channel, only transmit given time. more devices transmit simultaneously, "collision" sensed, nodes involved forced reschedule their transmissions after random interval. Medium Attachment Unit (MAU) responsible detection collisions. Current implementations consist largely transceiver, with additional passive components, power supply, connectors (see Figures Serial data originating from controller Data Terminal Equipment (DTE) passed using Attachment Unit Interface (AUI). detects collision, reports back controller using AUI. With coaxial topology, nodes connected center cable conductor. transceiver detect more devices transmitting network because voltage center conductor will exceed collision threshold (-1.6 nominally). drive coax cable, transceiver requires relatively high negative supply voltage (typically making unsuitable candidate most mainstream CMOS silicon processes currently available.
Connector Isolation Barrier
Ethernet Coax Am7996/7 Transceiver Connector
Power Supply
16850A-004A
Figure 10BASE5
Introduction
Connector Isolation Barrier
Power Supply Cheapernet Coax Am7996/7 Transceiver RG58
16850A-005A
Figure 10BASE2 Because 10BASE-T uses separate transmit receive signal paths, "logical" collision detection implemented. While data transmitted from node repeater over transmit wire pair, receive pair should remain idle. both transmit receive pairs become active simultaneously, 10BASE-T transceiver detects collision. voltage levels required 10BASE-T (5.0 ±0.6 peak-to-peak) using standard CMOS logic levels.
RFI/EMI Filters Isolation Barrier RJ45 Regulator LEDs
16850A-006A
Connector
Optional
Am79C98 Transceiver
Unshielded Twisted-Pair
Figure 10BASE-T Isolation isolation barrier required long-distance network topologies protect from potentially hazardous voltages that present during fault conditions medium. coax-based network, this direct current (DC) isolation located path because coax transceiver must DC-coupled center conductor permit collision detection. With 10BASE-T logical collision detection scheme eliminates need path medium (see Figures isolation barrier relocated medium side 10BASE-T transceiver. Removing requirement isolation path allows 10BASE-T transceiver integrated with remainder 802.3 node components, i.e., Medium Access Controller (MAC) Physical Layer Signaling (PLS), single piece silicon (see Figure
Introduction
802.3 (Media Access Control) (Physical Layer Signaling)
16850A-007A
LANCE Host Master Interface Unit
TPEX Network
Figure Ethernet Node Silicon Link Integrity Separation transmit receive paths 10BASE-T potential drawbacks. When node transmits coax system, simultaneously receives transmission (because both transmitter receiver connected coax center tap) returns controller indication transmit-to-receive path integrity. 10BASE-T system, separation transmit receive cable pairs combined with logical collision detection means that when driving transmit twisted-pair, transceiver does activity receive pair unless collision occurs. Unlike coax system, transceiver longer observe signal transmission, loopback path controller implemented internally MAU. controller made believe that transmit-to-receive integrity present, difference detected between coax twisted-pair medium. However, mechanism necessary ensure that failure transmit receive path detected. case broken transmit path, node unable send data over network. However, broken receiver receive cable) more serious implications. node loses ability monitor network activity collisions. node with data transmit would regardless current network activity, possibly causing collision with existing message. Because recovery from collision fundamental 802.3 Medium Access Control function, appears that this serious problem. However, correctly configured network, collisions guaranteed occur within defined window (known "slot time") after transmission commences. transmission that experiences collision within slot time automatically retried sending node. re-tries total attempts) permitted before node aborts transmission. other hand collision that occurs after slot time (512 bits 51.2 results late collision, node abandons transmission attempt immediately. Most 802.3 controllers incorporate late collision indicator advise host processor this condition. Upperlayer software then responsibility recognize late collision indicator reschedule transmission. feature referred "link test" ensures network integrity. absence network traffic, simple heartbeat pulse sent transmitter 10BASE-T repeater DTE). receiver does either packet data link test pulse within defined time window ms), enters "link fail" condition, thus disabling data transmit, data receive, loopback functions (see Figure Disabling transmit function prevents disturbance existing network traffic. Disabling loopback path warns node that there failure (the transmit-to-receive path interrupted). receive pair disconnected, enters link fail state, further transmission disabled. During link fail, transmission reception link test pulses continues. reestablish link, least consecutive link test pulses single receive packet must received.
Introduction
Link Test Pulses 10BASE-T XCVR Twisted-Pair Link Segment
Link Test Pulses
16850A-008A
Figure Link Test Transmission/Reception Status Indicators Most 10BASE-T transceivers incorporate additional status features allow simple diagnoses network node state. external link status indicator mandated 10BASE-T standard. Transmit, receive, collision activity separately indicated coax MAU, receive always active during transmit) provide simple network activity display. addition, because link test pulse (unlike normal differential data transmissions) unipolar, possible detect polarity receive signal path. This useful feature that used automatically detect correct simple wiring installation errors.
Advantages
user community, 10BASE-T brings several advantages. Reduced Installation Cost cable installation costs more than cable itself. existing telephone cabling used, savings significant. Even cabling must installed, costs generally lower because identical connection technology widely used telecom applications. Therefore, inexpensive, installation easily procured. Long-term Cost Ownership (COO) Benefits During lifetime LAN, long-term benefits outweigh original equipment cost. Addition movement users more difficult coax-based Ethernet. Connection coax cable requires special tools, coax physically accessible. 10BASE-T system literally "plug play." Reconfiguration simple adding wall plug plugging into pre-wired connection from repeater. When user moves (switches system), link test pulses stop being transmitted, repeater port effectively shuts down. Ease Fault Isolation, Management, Security large corporate networks, ability manage maintain network vital. Many businesses depend their communications facilities. utility much like telephone system. When telephone picked dial tone expected. same way, when networked service accessed, expected available. coax bus, faults difficult analyze because nodes connected cable times. With 10BASE-T, only repeater) connected port repeater, behavior connection individually monitored. failure isolated quickly, remainder network operates unimpaired while problem fixed. Access control network security readily administered through repeater. instance, manager instruct shut down particular link p.m. Friday enable link a.m. Monday. Other features such configuration mapping also monitored because each 10BASE-T link generally
Introduction
connected single node. Connections repeaters coax segments obey this rule, this behavior also allows these links identified. Even small low-cost installations which network manager warranted, single point concentration, point-to-point connectivity, rudimentary status indicators make diagnosing problem 10BASE-T network less-daunting task than checking entire coax segment potential connection problem. Volume Manufacturing 10BASE-T topology enables further silicon integration, which will ultimately drive down system cost ways. First, high demand integrated circuits (ICs) board level products will generate fierce competition market share from both silicon systems companies. Second, sheer size market opportunity will lead high volume manufacturing. Interoperability Standardization overwhelming demand from user community interoperability based open standards. standard, itself 10BASE-T, driving creation adoption additional standardization. lack centrally located point monitoring network management long been criticism leveled coax-based 802.3/Ethernet. 10BASE-T hub-based star architecture removes this obstacle. widespread adoption hub-based topologies that support Ethernet, Token Ring, FDDI (Fiber Distributed Data Interface), standardization network management information exchange also underway. Currently, Simple Network Management Protocol (SNMP) defacto standard employed Ethernet networks management infrastructure components, i.e., bridges routers. Institute Electrical Electronics Engineers working create Layer Management Repeater Devices standard (frequently referred Repeater Management Draft4 This standard will specify manageable attributes repeater. This draft been adopted being reviewed simultaneously Internet Engineering Task Force speed publication specification within Internet community. This will ensure that migration hub-based topology will rapid widespread.
INTEGRATION NODE
Silicon vendors began integration process transceiver. huge installed base AUI-compatible machines made silicon integration natural choice, silicon allowed technology proven small device. Am79C98 TPEX(Twisted-Pair Ethernet Transceiver) fully compliant AUI-based 10BASE-T transceiver. device incorporates 10BASE-T drivers receivers. also provides status LEDs, well automatic detection correction receive signal polarity. device jointly developed SynOptics Communications Inc., acknowledged leader 10BASE-T marketplace. Clearly, volume consumption 10BASE-T node connections will desktop computer market, including IBMand Macintoshpersonnal computers, engineering workstations, X-Windowsterminals, similar desktop systems. addition, significant opportunity exists network growth mobile computer (laptops palmtops) arena.
Personal Computers
arena, connectivity almost entirely serviced add-in card market. This largest market segment Ethernet chipsets. Typically, card
Draft Supplement ANSI/IEEE 802.3 -1990 Edition, Layer Management Repeater Devices, Section
Introduction
With submicron-level geometries available mainstream silicon vendors 10BASE-T transceiver's effectiveness when implemented this technology, possible integrate virtually entire add-in card onto single chip. Only those components that require custom programming (i.e., remote boot PROM IEEE address PROM) need remain external integrated Ethernet node silicon. Note that already possible integrate MAC, PLS5 10BASE-T transceiver functions. However, this still does provide most cost-effective system solution. incorporation interface logic provide single-chip, bus-specific controller offers optimal level integration. This approach clearly reduces component count, complexity, form factor Ethernet add-in card market. addition, RJ45 phone jack connector used 10BASE-T incurs minimun board-area computer backpanel space. increased integration, reduced component cost, reduction form factor that 10BASE-T brings attributes that will allow Ethernet become standard feature motherboard. Currently, laptop palmtop most frequently networked using external adaptor that provides Ethernet connection through computer's parallel printer port. Battery life important factor mobile computer environment. address this issue, Ethernet node chips will incorporate sleep capabilities low-power applications, thus allowing 10BASE-T incorporated onto mobile computer motherboard.
Non-PC-Based Applications
Several significant market segments outside area require networking standard optional feature. These include applications such engineering workstation (EWS), X-Windows terminal, laser beam printer (LBP). Virtually systems shipped with Ethernet motherboard, although usually network connector choice, requiring external transceiver. Am7990 LANCE(Local Area Network Controller Ethernet), first generation Ethernet controller, widely used with engineering workstations. Most medium-to-high performance LBPs offer networking optional feature. Some incorporate entire print server hardware software capabilities. almost cases, connection offered add-in card because impossible predict user's preferred technology. However, prevalence 10BASE-T will cause some vendors integrate chipset onto motherboard standard feature. Thus, 10BASE-T will become cheaper preferred technology, with other options offered retrofit. AMD's Am79C900 ILACC(Integrated Local Area Communication Controller) already taken first step integration process incorporating controller (DMA controller function) Manchester encoder/decoder (the function Serial Interface Adaptor) single CMOS device (see Figure device, 32-bit version popular LANCE, offers software compatibility. Both LANCE ILACC master devices that suitable many systems. However, some applications slave-based Ethernet controller preferred because synergy with other slave peripherals system.
ISO/IEC 8802-3 :1990 (E); ANSI/IEEE 802.3-1990 Edition, Section
Introduction
collision indication because both transmit receive functions become active simultaneously. Hence, collision generated every packet. this case, partitioning state machine port isolates transmit function miss-wired port after predefined maximum number consecutive collisions detected (>30). need multi-vendor interoperability generating great deal activity standardization management information transaction, seen activities IEEE Management Task Force. Once Management Draft becomes stable, silicon vendors will resume integration process allow full support IEEE-defined Management Information Base.
High Reliability
star architecture distinct drawback that repeater itself potential single-point failure. Because repeater responsible regeneration network traffic, failure could isolate attached nodes. Silicon integration repeater brings with reduction number inter-chip connections, which major contributor mechanically related failures. From system perspective, integration should allow swappable modularity redundancy medium level required.
Silicon Availability
AMD's Am79C980 Integrated Multiport Repeater(IMR) integrates functions 802.3-compliant repeater single chip, including Manchester encoder/decoder, first in-first (FIFO) buffers, repeater state machines, eight complete 10BASE-T MAUs. addition, device supports single port (see Figure 11), management port, expansion port. worked jointly with Hewlett-Packard implement functionality HP's original EtherTwisthub product. HP's network systems expertise AMD's mixed analog/digital CMOS strength have produced fully compliant highly integrated product.
Management Port Expansion Port
Twisted Pair Port
Twisted Pair Port
16850A-011A
Figure Block Diagram reduces cost complexity repeater technology, enhances reliability, opens market wide variety repeater solutions. Because virtually expertise perform repeater function contained silicon itself, technology entry barrier been removed.
Introduction
Velcro Hubs
provides completely scalable solution repeater market. low-end systems, combined with power supply, crystal, electromagnetic interference/radio frequency interference (EMI/RFI) filter transformer modules effectively produce fully operational 10BASE-T repeater with port that allows connection existing 10BASE2/5 coax backbone.
Power Supply Regulator Isolation Status LEDs Quad Filter/Transformer Module
Quad Filter/Transformer Module
16850A-012A
Figure Simple Velcro Example
ISA-HUBexcellent example low-cost managed repeater ISA-HUB concept. client-server environment, file-server already acts shared resources. implementing repeater PC/AT-compatible format, power supply case provided server itself. addition, server additional compute power available perform management. port count increased cascading multiple IMRs together using built expansion port.
Fully Managed Hubs
high-end applications requiring facilities such modularity, fault-tolerance management Management Draft, SNMP agent capabilities, external logic intelligence added provide these features cost-effective manner. this way, low-end repeaters produced optimum system cost, while cost port will increase accordingly sophisticated management features added.
SUMMARY
Simpler configuration reconfiguration capabilities combined with network management capabilities mean that 10BASE-T network more able respond personnel desktop computer movement than coax-based Ethernet. cost implement 10BASE-T Ethernet will driven down point that will become standard feature many desktop computer applications, including laser printers, PCs, X-Windows terminals. scalability entry cost 10BASE-T will ensure success. 10BASE-T will have major impact networked office, from small user group requiring simple connectivity through remote offices connected dial-up lines interconnection with existing Ethernet LANs large-scale corporate installations. Current generation silicon already fostering price reductions 10BASE-T MAUs, add-in cards, repeaters. Future integration 10BASE-T silicon assured Management Standard solidifies security fault tolerance features incorporated.
Introduction
CHAPTER
CHAPTER System Considerations
PCnet-ISA designed interface seamlessly PC/AT expansion bus, known formally Industry Standard Architecture (ISA) bus. master mode, possible connect pins PCnet-ISA chip directly edge connector pads adapter card without using external buffers, drivers, decoders. system buffering address decoding done inside PCnet-ISA. Shared-memory mode requires some external hardware, offers additional architectural flexibility.
Master Mode
When configured master mode, PCnet-ISA allows user design high-performance Ethernet system with minimal cost parts count. PCnet-ISA also compatible with Novell NE2100 NE1500T Ethernet adapters, which based upon Am7990 LANCE (Local Area Network Controller Ethernet) chip. basic operation PCnet-ISA master mode consists input/output slave cycles control status, master (direct memory access) operations (16-bit) movement transmit receive data. These operations take place over bus; therefore, host system must support mastering. During PCnet-ISA mastering periods, host inactive. 1.1.1 Hardware Considerations When master mode, PCnet-ISA requires 16-bit host platform such PC/AT. PCnet-ISA will function master 8-bit environment. Although PCnet-ISA supports only 8-bit PROM accesses support 8-bit input/output slave cycles, PCnet-ISA assumes that master memory cycles 16-bit; there support chip support 8-bit cycles. From host system software point view, PCnet-ISA-based adapter represents software resources, namely read write space memory read-only space. space consists internal PCnet-ISA registers optional IEEE Ethernet address PROM. read-only memory space refers optional external boot PROM. While both resources accessed 16-bit software entities, internal PCnet-ISA registers must coded 16-bit word locations. Connection-wise, PCnet-ISA pins should connected directly bus. External PROM devices share only system address lines with PCnet-ISA, other PROM connections (data output enable) controlled dedicated pins PCnet-ISA. 1.1.2 Register Addressing PCnet-ISA internal user control status registers (CSRs) that facilitate configuration status transfers between PCnet-ISA host system. Because there many CSRs individual addresses, indexed addressing scheme used access each individual CSR. Specifically, PCnet-ISA single register address port (RAP) into which number written. Once register address port contains desired number, data read from register data port (RDP). Sequential accesses same require writes register address port. second internal registers, configuration registers (ISACSRs), accessed same CSRs, except that data read from RDP, from data port (IDP).
System Considerations
accesses IEEE address PROM locations individually addressed standard locations. 8-bit accesses, PCnet-ISA utilizes system address lines (SA0-19), system data lines (SD0-7), Read (IOR), Write (IOW), address enable (AEN); PCnet-ISA returns channel ready (IOCHRDY). PCnet-ISA configured support 16-bit cycles, system data (SD8-15) lines system byte enable (SBHE) also used. this configuration chip select (IOCS16) returned active only internal PCnet-ISA registers accessed; accesses IEEE PROM will 8-bit cycles only. PCnet-ISA configured perform only 8-bit cycles, even internal registers. This accomplished leaving IOCS16 disconnected from bus, instead shorted ground. following table shows address space supported PCnet-ISA. Offset Bytes Register Address PROM (shared IDP) Reset Vendor-Specific Word
Vendor-specific word internally supported PCnet-ISA. shown here externally decoded address space that available system designer; will used PCnet-ISA future Ethernet controller. offsets listed referenced base address PCnet-ISA. This base address defined current state address (IOAM) pins. IOAM pins also define boot PROM memory address space which internal address decoder will respond. IOAM pins sampled simply inputs internal address decoder. IOAM1-0 Base Boot PROM Base C8000 CC000 D0000 D4000
1.1.3 Boot PROM PCnet-ISA performs boot PROM address decoding buffering internally. address decoder defined state IOAM pins. 8-bit memory cycles, PCnet-ISA utilizes SA0-19 unlatched address lines (LA17-23) address lines, SD0-7 data lines, system memory read select (SMEMR), memory refresh active (REF) AEN; PCnet-ISA returns only IOCHRDY. PCnet-ISA supports 8-bit slave memory cycles only; PCnet-ISA does utilize SBHE slave memory cycles.
System Considerations
1.1.4 Hardware Compatibility Issues stated before, PCnet-ISA master mode must installed host system that supports mastering. PC/XTand some PC/AT compatibles support mastering therefore will function PCnet-ISA (bus master mode) hosts. addition, PCnet-ISA master mode requires 16-bit memory transfers. This precludes PC/XT 8-bit slots PC/AT clones. Another possible compatibility issue involves IOCS16 signal. IEEE P996 standard recommends that IOCS16 signal generated decode address lines only, some systems (i.e. motherboard chipsets) compatible with this timing. Attempts universal compatibility have been implemented, most them involving delaying IOCS16 signal until become active. This scheme helps some cases, causes incompatibilities elsewhere. PCnet-ISA follows IEEE P996 recommendation generation IOCS16. 16-bit cycle compatibility question eliminated simply configuring PCnet-ISA support 8-bit cycles only. This recommended configuration. Because vast majority PCnet-ISA operations master direct memory accesses, limiting PCnet-ISA cycles 8-bit only will have virtually effect system throughput performance. This configuration accomplished disconnecting PCnet-ISA IOCS16 from tying ground. cycles (internal PCnet-ISA registers IEEE PROM) well boot PROM memory cycles, will 8-bit only. PCnet-ISA always performs master DMAs 16-bit transfers. Some PC/AT-compatibles have been known spuriously assert acknowledge (DACKx) signals (other than refresh controller DACK) during memory refresh cycles. master device such PCnet-ISA requests asserting request (DRQx)), might interpret spurious DACKx assertion permission assume mastership. this reason, DACK signal ignored PCnet-ISA when asserted. SMEMR signal also ignored PCnet-ISA while asserted. 1.1.5 Bandwidth Latency Requirements PCnet-ISA performs vast majority tasks master transfers. These include initialization, ring polling, descriptor reads writes, frame data (buffer) transfers. Because Ethernet interface operates rate, PCnet-ISA must ensure that sufficient data available transmit that space available store received data. This scenario requires some definitions. master device that currently controls owns bus, i.e., drives address lines command lines (e.g., IOR, IOW, memory read select (MEMR), memory write select (MEMW)) directs flow data over data lines. environment, default master. non-CPU device obtain master status arbitrating ownership. This arbitration process request-acknowledge handshake protocol. bandwidth percentage time that device (bus master) controls bus. This percentage changes depending upon current task being performed master. PCnet-ISA uses most bandwidth during frame transmission reception; uses least bandwidth when PCnet-ISA simply polling descriptor rings. Conversely, amount available bandwidth changes depending upon tasks that other masters currently performing. latency time beginning when device (bus master) requests ownership until device actually takes ownership bus. This time changes depending upon available bandwidth bus. critical issue here latency. PCnet-ISA that receiving frame must have access that transfer frame memory; making PCnet-ISA wait long mastership results missed packet first in-first (FIFO) System Considerations
buffer overflow, error, both. transmitting PCnet-ISA must have system memory data continuously supplied FIFO maintain Mbps Ethernet rate; late ownership leaves PCnet-ISA middle frame transmission with data finish transmission. therefore, critical that enough bandwidth available ensure minimal latency. Because each master (CPU, refresh controller, controller, PCnet-ISA) environment uses finite amount bandwidth, important that overtaxed master. Under optimal conditions, bandwidth utilization PCnet-ISA approximated ratio Ethernet data rate data rate. maximum data rate based upon master cycle time PCnet-ISA. default value this tuned faster slower operation reprogramming configuration register. addition, maximum performance achieved when buffers chained. Chaining occurs when frame data cannot into single buffer. Assuming default timing buffer chaining PCnet-ISA, this maximum data rate follows: cycle bits cycle 45.7 Mbps This calculation does take into account descriptor accesses; does give PCnet-ISA minimum bandwidth usage approximately 22%. This number will degrade buffers frame ratio increases. PCnet-ISA most sensitive latency when large Ethernet frames involved small data buffers chained together. This PCnet-ISA having descriptor look-ahead operations each chained buffer, thus using bandwidth without transferring frame data. Assuming 32-byte chained buffers, calculations each buffer provided below. bytes transferred from FIFO over cycles cycle (This requires arbitration PCnet-ISA does word memory cycles arbitration.) Descriptor look-ahead operation cycles cycle (This requires arbitration PCnet-ISA does descriptor reads arbitration.) Descriptor update operation cycles (max) cycle (This requires arbitration PCnet-ISA does descriptor writes arbitration.) Microcode travel time (internal PCnet-ISA microcode decision delay) These operations transfer bytes, take total (not including latency), require total three arbitrations. network takes bytes bits byte 25.6 transmit bytes frame data; PCnet-ISA must complete above arbitrations transfer operations least once every 25.6 order keep with network. This leaves 25.6 total time operations time 17.2 total allowable latency three arbitrations, average latency tolerance. bandwidth usage 25.6 29%. latency tolerance improves 12.7 bandwidth improves when using 128-byte chained buffers.
System Considerations
Shared-Memory Mode
When configured shared-memory mode, PCnet-ISA allows user design high-performance Ethernet system environments that support 16-bit memory cycles which mastering either supported desired. basic operation PCnet-ISA shared-memory mode consists slave cycles control status, shared memory operations movement transmit receive data. These shared-memory operations take place over PCnet-ISA private data (PRDB) private address (PRAB) invisible host system. Therefore, during PCnet-ISA PRDB/PRAB accesses, host interrupted preempted. This aspect allows operation host systems that either support mastering cannot afford preemption. shared-memory mode, PCnet-ISA operations take place over bus. 1.2.1 Hardware Considerations When shared-memory mode, PCnet-ISA does require 16-bit platform. host system 8-bit only (such PC/XT), cycles will obviously 8-bit. However, platform 16-bit, PCnet-ISA support 16-bit cycles resources except IEEE address PROM, which supports 8-bit cycles only. From host system software point view, PCnet-ISA-based adapter represents three software resources, namely read write space, memory read write space, memory read-only space. space consists internal PCnet-ISA registers optional IEEE Ethernet address PROM. read-only memory space refers optional external boot PROM. While resources accessed 16-bit software entities, internal PCnet-ISA registers must coded 16-bit word locations. Connection-wise, PCnet-ISA pins should connected directly bus. external PROM devices SRAM devices connected directly PCnet-ISA private address private data bus, other PROM SRAM connections (PROM output enable (OEs); SRAM write enable (WE)) controlled dedicated pins PCnet-ISA. external 6-bit address buffer required, external address comparators boot PROM SRAM. 1.2.2 Register Addressing master mode, PCnet-ISA internal user control status registers shared-memory mode that facilitate configuration status transfers between PCnet-ISA host system. Because there many CSRs individual addresses, indexed addressing scheme used access each individual CSR. Namely, PCnet-ISA single register address port (RAP) into which number written. Once register address port contains desired number, data read from register data port. Sequential accesses same require writes register address port. second internal registers, configuration registers (ISACSRs) accessed same CSRs, except that data read from register data port, from data port (IDP). accesses IEEE address PROM locations individually addressed standard input/output locations. 8-bit accesses, PCnet-ISA uses SA0-19 address lines, SD0-7 data lines, IOR, IOW, AEN; PCnet-ISA returns IOCHRDY. PCnet-ISA configured support 16-bit cycles, SD8-15 lines SBHE also used. this configuration IOCS16 returned active only internal PCnet-ISA registers accessed; accesses IEEE PROM will 8-bit cycles only. PCnet-ISA configured perform 8-bit cycles only, even internal registers. This accomplished leaving IOCS16 disconnected from instead shorting ground.
System Considerations
PCnet-ISA will forced into 8-bit cycle mode accesses (registers, PROMs, SRAM) SBHE left unconnected. This situation would arise PC/XT 8-bit slot PC/AT. table below shows address space supported PCnet-ISA. Offset Bytes Register Address PROM (shared IDP) Reset Vendor-Specific Word
Vendor specific word internally supported PCnet-ISA. shown here externally decoded address space that available system designer; will used PCnet-ISA future Ethernet controller. offsets listed referenced base address PCnet-ISA. This base address defined current state address (IOAM) pins. IOAM pins sampled simply inputs internal address decoder. IOAM1-0 Base
1.2.3 Boot PROM PCnet-ISA performs boot PROM buffering internally, address decoder function must done externally. This external decoder defines address space boot PROM must generate boot PROM address match (BPAM) signal PCnet-ISA; BPAM signal unique address decode boot PROM address space. PCnet-ISA assumes that boot PROM accesses 16-bit cycles. these 16-bit memory cycles, external address decoder should LA17-23 address lines appropriate address lines needed generate unique BPAM boot PROM address space. external address decoder must also return MEMCS16 bus. PCnet-ISA uses SD0-15 data lines, MEMR, REF, SBHE, AEN; PCnet-ISA returns only IOCHRDY. PCnet-ISA made support 8-bit only boot PROM cycles while leaving shared-memory SRAM supporting 16-bit cycles. This accomplished through trickery with BPAM SMAM inputs. While external address comparator would assert only BPAM 16-bit boot PROM accesses, decoder must assert BPAM SMAM simultaneously 8-bit boot PROM cycle. While this logically illegal state, will force PCnet-ISA into 8-bit boot PROM access. Asserting BPAM alone will cause PCnet-ISA execute default 16-bit boot PROM cycle. PCnet-ISA will forced into 8-bit cycle mode accesses (registers, PROMs, SRAM) SBHE left unconnected. This situation would arise PC/XT 8-bit slot PC/AT.
System Considerations
1.2.4 Shared Memory SRAM PCnet-ISA performs shared-memory SRAM buffering internally, address decoder function must done externally. This external decoder defines address space shared-memory SRAM must generate SMAM signal PCnet-ISA; SMAM signal unique address decode SRAM address space. PCnet-ISA assumes that SRAM accesses 16-bit cycles. these 16-bit memory cycles, external address decoder should LA17-23 address lines appropriate address lines needed generate unique SMAM SRAM address space. external address decoder must also return MEMCS16 bus. PCnet-ISA uses SD0-15 data lines, MEMR, MEMW, SBHE, AEN; PCnet-ISA returns only IOCHRDY. PCnet-ISA made support 8-bit only shared-memory SRAM cycles, this forces PCnet-ISA support only 8-bit cycles resources (registers, PROMs, SRAM). This accomplished leaving SBHE unconnected. This situation would arise PC/XT 8-bit slot PC/AT. this case external address decoder SRAM should return MEMCS16 host system. Because MEMCS16 signal does exist PC/XT environment, possible design single Ethernet adapter board that compatible with both 8-bit 16-bit environments still takes full advantage either system's resources. 1.2.5 Hardware Compatibility Issues possible PCnet-ISA host system compatibility issue involves IOCS16 signal. IEEE P996 standard recommends that IOCS16 signal generated decode address lines only, some systems (e.g., motherboard chipsets) compatible with this timing. Attempts universal compatibility have been implemented, most them involving delay IOCS16 signal until become active. This scheme helps some cases, causes incompatibilities elsewhere. PCnet-ISA follows IEEE P996 recommendation generation IOCS16. 16-bit cycle compatibility question eliminated simply configuring PCnet-ISA support 8-bit cycles only. This recommended configuration. Because vast majority PCnet-ISA operations private address data memory accesses memory cycles, limiting PCnet-ISA cycles bits only will have virtually effect system throughput performance. This configuration accomplished disconnecting PCnet-ISA IOCS16 from bus, tying ground. cycles (internal PCnet-ISA registers, IEEE PROM) will then bits only. Leaving SBHE disconnected will also force PCnet-ISA support only 8-bit cycles, will also force PCnet-ISA accesses (registers, PROMs, SRAM) into 8-bit only cycle mode. This situation would arise PC/XT 8-bit slot PC/AT.
System Considerations
System Considerations
CHAPTER
CHAPTER Network Characteristics
Network Operation
outlined Chapter PCnet-ISA acts mastering device when transferring packet data from host memory. addition mastership, additional features built into PCnet-ISA that increase overall efficiency over other types controllers. primary objective most these features minimize occupancy that PCnet-ISA requires given network throughput. These features will discussed terms their purpose their overall benefits. detailed description operation each feature, consult PCnet-ISA data sheet.7 additional detail various features accessed programmed, consult Chapter this manual. starting point, some definitions 802.3 Ethernet frame formats included here. These definitions will basis understanding network performance PCnet-ISA relative effect Industry Standard Architecture (ISA) bus. additional details, consult 802.38 Ethernet9 specifications.
Preamble 1010.1010 Bits 10101011 Bits Dest Addr Bytes Srce Addr Bytes Length Data
Bytes
46-1500 Bytes
Bytes
16850A-013A
Figure 802.3 Frame Organization
Preamble 1010.1010 Bits
SYNCH Bits
Dest Addr Bytes
Srce Addr Bytes
Type
Data
Bytes
46-1500 Bytes
Bytes
16850A-014A
Figure Ethernet Frame Organization
PCnet-ISA Preliminary Information Data Sheet, Publication #16907A. Ethernet: Local Area Network Data Link Layer Physical Layer Specification, Version 2.0, 1982, DEC, Intel, Xerox. ISO/IEC 8802-3 :1990 (E); ANSI/IEEE 802.3-1990 Edition, Section
Network Characteristics
primary difference between 802.3 Ethernet frames described below. start frame delimiter 802.3 defined byte containing 10101011 pattern, whereas Ethernet's synch bits have sequence. However, both cases preamble plus start frame indication bits long. Ethernet 802.3 both specify that packet must range from 1518 bytes. However, actual data field 802.3 smaller than 46-byte value needed ensure this minimum size. result, 802.3 requires Logical Link Control (LLC) layer append characters data field before passing data Media Access Control (MAC) layer. Ethernet assumes that upper layers ensure that minimum data field bytes before passing data MAC, concept characters (although they have effectively been inserted upper-layer software) does exist. IEEE 802.3 uses length field indicate number data bytes (excluding characters) that data field only (excluding frame check sequence (FCS) field). Ethernet, other hand, uses type field same bytes identify message protocol. Because valid Ethernet type fields always assigned above maximum 802.3 packet size, Ethernet 802.3 packets coexist same network. Note that packet size 1518 bytes refers number bytes after start frame, including FCS. preamble used only Manchester encoder/decoder lock-on incoming receive stream. preamble passed through host system. 2.1.1 Collision Fragment Runt Packet Rejection receive FIFO PCnet-ISA bytes deep. After power-up initialization, PCnet-ISA always waits receive FIFO fill minimum bytes, before requests asserting request (DRQ) pin. correctly configured 802.3/Ethernet network, packets contain minimum bytes data, collisions guaranteed occur within 512-bit times bytes) from start packet. This means that receive message that terminates before bytes (due either collision packet completing) flushed from receive FIFO with host interaction. This flushing particular benefits heavily loaded networks, where collisions occur frequently. Because packet flushed from FIFO prior assertion DRQ, there impact bandwidth utilization. Passing runt packets (less than bytes) optionally permitted PCnetISA. This feature enabled setting runt packet accept (RPA, CSR124). normal operation, runt packets rejected. Some non-compliant network protocols send runt packets, however. Note that 512-bit time (64-byte time) period (the slot time) time during which collision occurs normally configured network. slot time worst-case end-to-end delay network, that transmitting node guarantees collision within this period another node simultaneously starts transmit elsewhere. slot time starts with first preamble, whereas 64-byte minimum packet size refers actual packet data excluding preamble. 2.1.2 Auto Retransmit Deletion Collision Automatic retry collisions within slot time. PCnet-ISA ensures that collisions that occur within 512-bit times from start transmission (including preamble) automatically retried with host intervention system impact. transmit FIFO guarantees that data contained within FIFO overwritten until least bytes (512 bits) data have been successfully transmitted onto network. These criteria will met, regardless whether transmit frame first only) frame transmit FIFO ithe transmit frame queued pending completion preceding frame.
Network Characteristics
Deletion packets excessive transmission attempts. total attempts (initial attempt plus retries) made transmit frame, PCnet-ISA abandons transmit process particular frame, reports retry error (RTRY) transmit message descriptor (TMD3), gives ownership (sets zero) transmit descriptor, sets transmit interrupt (TINT) (CSR0), activating external interrupt request (IRQ) provided interrupt unmasked. disable retry (DRTY) mode register (CSR15) set, RTRY will after failed transmission attempt. Internally, PCnet-ISA updates transmit FIFO read write pointers. end-of-frame marker exists transmit FIFO, entire FIFO reset. whole frame does reside transmit FIFO, read pointer moved start next frame free location FIFO, write pointer unaffected. Packets experiencing unsuccessful attempts transmit retried. Recovery from this condition must performed upper-layer software. minimum transmit buffer length. particularly important aspect this recovery mechanism that PCnet-ISA requirement minimum transmit buffer size. This case original LANCE, which requires minimum transmit buffer length ensure that ownership transmit descriptor maintained until after slot time expires. This enables LANCE reload transmit data into FIFO retransmission attempt. Substantial bandwidth savings observed PCnet-ISA implementation over LANCE-based adaptor design (such Novell NE1500T NE2100) heavily loaded networks where significant collision activity present. LANCE-based design must reload transmit data into FIFO when collision detected during transmission. PCnet-ISA does require this reload because transmit FIFO data protected. Elimination minimum transmit buffer size restriction simplifies device driver writing, although existing LANCE drivers that obey restriction function correctly with PCnet-ISA. Even though PCnet-ISA requires minimum transmit buffer size, using extremely small buffers increases overall occupancy because descriptor fetch look-ahead operations occur much more frequently relation number data bytes transferred). addition, heavily utilized other devices, transmit underflow condition could result there insufficient bandwidth allow PCnet-ISA provide sufficient data transmit FIFO keep with network data rate. 2.1.3 Programmable Transmit Start Threshold transmit start point (XMTSP, CSR80) controls point which preamble transmission commences network relation number bytes written into transmit FIFO) current frame. When entire frame FIFO, transmission starts regardless value XMTSP. addition, transmission does start until inter-packet (IPG) timer expires random backoff interval completed. XMTSP given value bytes) after hardware software reset. Regardless XMTSP, FIFO will internally over write data until least bytes entire frame transmitted onto network. This ensures that collisions within slot time window, transmit data need rewritten transmit FIFO retries handled autonomously MAC.
Network Characteristics
CSR80[11-10] Bytes Written
XMTSP default bytes logically chosen based slot time bytes) size transmit FIFO (128 bytes). alternative programming XMTSP used, consideration should given system performance aspects. PCnet-ISA only master device system, there little effect other than lower values bytes) allowing device contend network earlier point. PCnet-ISA multi-master environment, consideration should given likelihood transmit underflow conditions occurring transmit FIFO cannot filled because ISA-bus bandwidth restrictions. With 4-byte threshold, transmit FIFO must receive additional data before preamble/start fram delimiter bits) first bytes bits) have been transmitted (within µs). Because PCnet-ISA normally reads data from host memory 32-byte blocks, preamble will start more data written into transmit FIFO during rest burst. However, caution should used when other options have been programmed limit time number transfers (using activity timer register (CSR82) burst register (CSR80) very small transmit buffers being used. default case, PCnet-ISA requires separate bursts bytes each executed before XMTSP reached. These yield latency 57.6 before transmit FIFO needs additional data. 2.1.4 Programmable Burst Size PCnet-ISA moves transmit receive data across bursts under mastership control. default mode, these bursts read write cycles corresponding bytes data, assuming data buffer aligned word (16-bit) boundary. burst size modified using burst register (DMABR) field within burst FIFO threshold control register (CSR80). value from transfers programmed. Regardless programmed burst size (default user-programmed), burst terminates once programmed high watermark reached transmit FIFO watermark receive FIFO. Programming larger values than default allows arbitration time mastership (which significant) amortized over greater number data transfer cycles, thereby increasing overall efficiency bus. However, care should taken avoid creating "bus hog" that cause other devices experience problems they prevented from accessing significant periods time. LANCE uses 8-cycle fixed burst size bytes maximum), PCnet-ISA already makes better utilization each arbitration cycle. PCnet-ISA takes slightly longer transfer bytes (slightly over than LANCE-based NE2100 NE1500T cards transfer bytes. burst size should constrained allow normal memory refresh approximately every 2.1.5 DMAPLUS explained previous section, default operation mode cycles transmit receive data movement occur 16-cycle bursts until FIFO high watermark reached. DMAPLUS (CSR4) allows PCnet-ISA fill empty transmit receive FIFO burst during single arbitration cycle.
Network Characteristics
DMAPLUS maximum transfers performed. This modified writing burst register (CSR80). DMAPLUS burst will continue until transmit FIFO filled high threshold bytes default) receive FIFO emptied threshold bytes default). exact number cycles during this burst dependent latency PCnet-ISA's mastership request speed operation. 2.1.6 Activity Timer activity timer allows timed burst activity. useful when other devices sensitive being prevented access bus. default configuration this feature disabled. activate feature, timer (CSR4) must appropriate value programmed into activity timer register (CSR82). activity timer gradually decreased every while PCnet-ISA asserts master transfer progress (MASTER) signal. must, therefore, programmed with value that gives correct activity duration using multiplier. value zero programmed, PCnet-ISA performs single cycle. Care should taken this register. While programming reasonable value allow more deterministic allocation bandwidth between devices, large values will certainly lead problems. maximum value 6.55 programmed. useful using this timer ensure that refresh cycles occur (approximately every even memory that PCnet-ISA reading writng adding additional wait states. 2.1.7 Programmable Transmit Request transmit FIFO watermark (XMTFW, CSR80) sets point which buffer management unit (BMU) requests transfer more data from transmit buffers transmit FIFO. specifies point which transmit starts stops, based upon number write cycles that could performed transmit FIFO. Transmit allowed time that number write cycles specified XMTFW executed without causing transmit FIFO overflow. XMTFW value after hardware reset, meaning empty bytes cycles) needed initiate DMA. CSR80[9-8] Write Cycles Reserved
PCnet-ISA will permit transmit FIFO overflow. default configuration, burst size will bytes. burst cycle initiated when bytes space available, full bytes moved burst. actual amount data that will moved dependent delay acquiring mastership number bytes that have been transmitted network during acquisition time. PCnet-ISA suspends burst before transmit FIFO overflows. This feature used conjunction with programmable burst size DMAPLUS enlarge size burst transfers hence minimize number overall arbitration cycles mastership. programming PCnet-ISA wait longer (for more space available transmit FIFO), burst size increased before FIFO's high threshold reached burst suspended. However, will also increase exposure PCnet-ISA underflow conditions cannot gain access ISA-bus. While burst size increased, acquisition latency reduced.
Network Characteristics
2.1.8 Programmable Receive Request receive FIFO watermark (RCVFW, CSR80) sets point which buffer management unit (BMU) requests transfer more data from receive FIFO receive buffers. specifies point which receive requested relation number received bytes receive FIFO). RCVFW specifies number bytes that must present (once packet verified non-runt) before receive requested. However, receive performed frame, least bytes must received. This effectively prevents runt receive frames collisions during slot time (512-bit times). runt packet accept feature enabled, receive requested soon either RCVFW threshold reached complete valid receive frame detected (regardless length). RCVFW value after hardware reset, meaning bytes must received initiate DMA. CSR80[13-12] Bytes Received Reserved
PCnet-ISA will permit receive FIFO underflow. default configuration, burst size bytes. burst cycle initiated when bytes received data available, full bytes moved burst. actual amount data that will moved dependent delay acquiring mastership number bytes that have been received from network during acquisition time. PCnet-ISA will suspend burst before receive FIFO underflows. Programming RCVFW lower value provides additional latency acquire before receive FIFO reach overflow situation. However, even when RCVFW programmed below 64-byte limit, each packet qualified non-runt before receive request issued. programmable burst size DMAPLUS features used conjunction with 64-byte threshold, size receive burst transfers enlarged, thus minimizing number overall arbitration cycles mastership. keeping default RCVFW, PCnet-ISA waits until 64-bytes available receive FIFO. burst size increased before threshold FIFO reached, burst suspended. 2.1.9 Programmable Memory Read Write Active Time PCnet-ISA allows master read write cycle times programmed. After power-up initialization process, default timing MEMR/MEMW command active time This increased reduced increments from Since MEMR/MEMW command inactive time fixed read write cycles programmed from (350 default). feature programmed through Data Port (IDP) located space device. register address port (RAP) pointer must initialized with value access mastermode read (MMRD) location, access master mode write (MMWR) location.
Network Characteristics
Command Active Time (ns) Command Inactive Time (ns) Total Cycle Time (ns)
MMRD/MMWR 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh
This feature specifically advantageous motherboard designs, where interface captive interoperability required over multiple-host systems, unlike adaptor card. Reducing command active time just increases performance during burst operations approximately 14%. feature generally avoided adaptor card designs unless driver setup procedure written specifically allow installer user easily adjust cycle time specific machine. default time been chosen compromise ensure maximum interoperability across bus-compatible machines, while minimizing occupancy device. 2.1.10 Pin-selectable 16-bit While transferring packet data, PCnet-ISA mastership, hence, full control timing. However, when being accessed slave device, read write internal CSRs chip must react correctly host-initiated cycle. this reason hardware compatibility issues relating mastership type devices almost exclusively related slave cycles. Most these incompatibility issues relate timing 16-bit cycles. avoid compatibility issues such this, PCnet-ISA chip supports 8-bit cycles. These cycles have relaxed timing constraints backward compatibility issue with older PC/XT type machines. object this feature maximize compatibility with minimal throughput impact. While chip supports full 16-bit cycles, recommended that 8-bit mode used simply connecting IOCS16 line bus, grounding instead. IOCS16 line connected bus, PCnet-ISA will monitor activity. detects IOCS16 active, will assume system support 16-bit cycles will respond accordingly. Detailed descriptions 8-bit 16-bit cycles available data sheet, they reproduced here.
Network Characteristics
Once PCnet-ISA been initialized driver running, very accesses required internal CSRs. driver originally written LANCE, there accesses CSRs except CSR0 because other CSRs readable unless stop set. PCnet-ISA does allow access additional internal CSRs, even when running. However, these generally limited network statistic counters, which configured provide interrupt when roll over occurs. Hence, performance impact running 8-bit comparison with large amount data transferred using 16-bit mastership cycles) will measurable most types traffic activity. 2.1.11 Transmit Padding During transmission frame, field inserted automatically. auto transmit enables automatic insertion feature (APAD field inserted frame leaves transmit FIFO, thus preserving FIFO space additional frames. addition, allowing PCnet-ISA perform padding relieves software this overhead task minimizes bandwidth avoiding transfer characters. Transmit frames automatically padded ensue bytes information, including destination, source, length, type, message data, fields (excluding preamble). This allows minimum frame size bytes (512 bits) 802.3/Ethernet guaranteed with software intervention from host system. placed between data field field 802.3 frame. always added frame padded, regardless state disable transmit (DXMTFCS) bit. transmit frame will padded bytes with value 00h. Upper-layer software must correctly define actual length field contained message correspond total number data bytes encapsulated packet (length field defined IEEE 802.3 standard). length value contained message used PCnet-ISA compute actual number bytes inserted. PCnet-ISA appends bytes dependending actual number bits transmitted onto network. Once last data byte frame completed prior appending FCS, PCnet-ISA checks ensure that bits have been transmitted. not, bytes added extend frame size this value, then added. 544-bit count derived from following information. Minimum frame size (excluding preamble, including FCS) Preamble/SFD size size bytes bytes bytes bits bits bits
classed minimum-size frame receiver, transmitted frame must contain following bits. Preamble (Min Frame Size FCS) bits point that appended, transmitted frame should contain following bits. Preamble (Min Frame Size FCS) bits (512 bits
minimum-length transmit frame from PCnet-ISA will, therefore, bits after appended. Ethernet specification makes field assumes that minimum-length messages will least bytes length. APAD (CSR4) controls programming automatic padding feature must static when transmit function enabled (TXON CSR0). transmitter should disabled before programming this option. default value APAD will disable auto generation after hardware software reset. Network Characteristics
2.1.12 Receive Frame Stripping During reception frame, field stripped automatically. auto strip receive enables automatic stripping feature (ASTRP_RCV field stripped before frame passed receive FIFO, thus preserving FIFO space additional frames. addition, allowing PCnet-ISA perform stripping relieves software this overhead task minimizes bandwidth avoiding transfer characters. field also stripped because computed transmitting station based data field characters will invalid receive frame that characters stripped. number bytes stripped calculated from embedded length field defined IEEE 802.3 definition) contained packet. length indicates actual number data bytes contained message. received frame that contains length field less than bytes will have field stripped. Receive frames that have length field bytes greater will passed host unmodified. Because valid Ethernet type field value always greater than normal 802.3 length field, PCnet-ISA does attempt strip valid Ethernet frames. some network protocols value passed Ethernet type 802.3 length fields compliant with either standard cause problems. diagram below shows byte ordering received length field 802.3-compatible frame format.
46-1500 Bytes
Bits Preamble 1010.1010
Bits SYNCH 10101011
Bytes Dest Addr
Bytes Srce Addr
Bytes Length
Bytes
Data 1-1500 Bytes
45-0 Bytes
Start Packet Time Increasing Time
Most Significant Byte
Least Significant Byte
16850A-015A
Figure IEEE 802.3-Compatible Frame Format ASTRP_RCV CSR4 controls programming automatic field stripping feature. ASTRP_RCV must static when receive function enabled (RXON CSR0). receiver should disabled before programming this option. default value ASTRP_RCV will disable auto stripping after hardware software reset.
Network Characteristics
Network Interfaces
following diagrams represent typical applications PCnet-ISA. first (see Figure shows 10BASE-T implementation; second (see Figure shows 10BASE-T 10BASE2 configuration. PCnet-ISA provides flexibility selection network interface. After reset, default configuration sets external select (XMAUSEL, ISACSR2), MAUSEL used configure port (MAUSEL HIGH select 10BASE-T). XMAUSEL cleared, selection port controlled either automatically under software control. auto select (ASEL, ISACSR2) set, active network interface automatically determined. 10BASE-T port link pass state (LED0 low, Link on), 10BASE-T port will selected. 10BASE-T port link fail state, port selected. forced software selection, port selection (PORTSEL, CSR15) bits override ASEL forces selection programmed choice. most cases physical dimensions board connector space dictate many interfaces supported. However, because 10BASE-T transceiver integral part RJ45 connector very small footprint, this offers most economical interface terms space, power, cost. Most workgroup installations either 10BASE2 (Cheapernet) 10BASE-T (twisted-pair) based. installations connected remote these interfaces provided, because 10BASE5 installations commonly used PC-based LANs. Because connector largest terms back panel footprint, providing 10BASE-T 10BASE2 will serve large proportion community. 2.2.1 Twisted-Pair (10BASE-T) Interface integrated 10BASE-T transceiver makes implementation this interface extremely simple. only components required transmit receive termination resistors, filter transformer module, RJ45 connector, some additional decoupling capacitors. filter transformer module minimizes potential electromagnetic interference radio frequency interference (EMI/RFI) problems. performance these modules governed some extent 10BASE-T standard, overall EMI/RFI system performance responsibility manufacturer. Common-mode noise primary contributor radiated energy from twisted-pair interface. Additionally, there often significant common-mode power supply noise generated motherboard adaptor other devices, filter transformer modules that incorporate common mode chokes recommended. addition, some modules offer integrated transmit receive termination resistors. list vendors products included Appendix. primary concerns minimize length cross-over connections between PCnet-ISA chip, filter transformer module, RJ45 connector. PCnet-ISA layout been optimized minimize cross-over requirements with most types filter transformer module. Additional information included Chapter interface drivers provided PCnet-ISA allow four status indicators. 10BASE-T implementation, link status (LNKST) provided LED0 mandatory. 10BASE-T standard recommends that indicator green. other LEDs mandatory, additional indicators largely dependent mounting space perceived value that indicator provides. NE1500T provides LEDs, Link (LNKST, LED0 default), Polarity (RCVPOL, LED2 default). The10BASE-T receiver PCnet-ISA ability automatically detect correct reversed polarity. This default configuration, which disabled setting disable automatic polarity correction (DAPC, CSR15) bit. default configuration LED1 display Receive Activity (RCV) LED3 displays Transmit Activity (XMT). default configuration LED1-3 reprogrammed.
Network Characteristics
ANLG 0.1µF 0.1µF Filter Transformer Module
1.21K
AVDD
AVSS TXD+ TXP+ TXD- TXP- RXD+ RXD-
ANLG
61.9 61.9
RJ45 Connector
Filter Note Filter
Note
DGTL LED0 LED1 LED2 LED3 Optional MAUSEL Enable LINK
Am79C960
Optional DGTL
Pulse Transformer
40.2 40.2
Connector
Note
40.2
40.2
0.1µF Optional ANLG
0.1µF
16805A-016A
Notes:
Compatible filter modules, with brief description package type features included Appendix. resistor values recommended general purpose should allow compliance 10BASE-T specification template jitter performance. However, overall performance transmitter also affected transmit filter configuration. Compatible transformer modules, with brief description package type features included Appendix.
Figure 10BASE-T Implementation PCnet-ISA
Network Characteristics
ANLG 0.1µF 0.1µF
AVDD
AVSS TXD+ TXP+ TXD- TXP- RXD+ RXD-
ANLG
61.9 61.9 1.21K
Filter Transformer Module Filter Note Filter
RJ45 Connector
Note
DGTL LED0 LED1 LED2 LED3 Optional LINK
Am79C960
DXCVR MAUSEL
Active Active High Optional Optional DGTL Pulse Transformer
40.2 40.2
Enable
Disable 10BASE2 DC/DC Convertor
10BASE2
Note
Am7996 Am7997
COAX (BNC)
40.2
40.2
Am7996 Am7997 Data Sheet component implementation details
0.1µF Optional ANLG
0.1µF
Notes:
16805A-017A
Compatible filter modules, with brief description package type features included Appendix. resistor values recommended general purpose should allow compliance 10BASE-T specification template jitter performance. However, overall performance transmitter also affected transmit filter configuration. Compatible transformer modules, with brief description package type features included Appendix.
Figure 10BASE-T 10BASE2 Configuration PCnet-ISA
Network Characteristics
2.2.2 Attachment Unit Interface PCnet-ISA chip directly supports fully compliant AUI. used interface external allow connection alternate media such 10BASE2 (Cheapernet), 10BASE5 (Ethernet), 10BASE-FL (fiber link). circuit implementation extremely simple, requiring pulse transformer, connector, some additional terminating decoupling components. However, specification optionally requires that external powered from (host) device. Although this optional, virtually implementations provide power source because cost complexity providing separate supply externally. voltage plus (VP, must provide between This frequently makes unattractive interface support power-sensitive applications. specific details power requirements, designations, connector type, consult Section 7.5.2.5 7.6.3 8802-3: 1990 (ANSI/IEEE 802.3). isolation transformer must provided protect PCnet-ISA chip from external fault conditions. specification requires that drivers receivers must tolerate applied voltage between inputs, outputs, ground with damage. logic PCnet-ISA must protected against this test voltage. list vendors products included Appendix. 2.2.3 Embedded 10BASE2 Medium Attachment Unit (MAU) PCnet-ISA support embedded 10BASE2 (Cheapernet) using port. same concerns apply this application, namely power consumption, board connector space, cost. this configuration externally exposed, power requiremnt allow remote operate from reduced. Typically, 10BASE2 transceiver requires power supply. Suitable convertors available from several vendors. Some these provide input that allows convertor remotely powered down using logic signal. This allows convertor transceiver disabled when 10BASE-T active network port, which substantially reduces overall system power requirements. PCnet-ISA provide either logic high output disable convertor, indicated previous diagram described below. Logic high indicates external convertor should turned off. disable transceiver (DXCVR) output used indicate active network port. high level indicates 10BASE-T port selected port disabled SLEEP active). level indicates port selected twisted-pair interface disabled. Logic indicates external convertor should turned off. LNKST (LED0) output used indicate active network port. high level indicates 10BASE-T port link fail state external convertor should level indicates 10BASE-T port link pass state external convertor should off. isolation transformer must still provided protect rest devices adaptor motherboard from potential network faults coax. full details implement 10BASE2 with Am7996/7 transceiver, consult appropriate data sheet (Am7996, Publication #07506; Am7997, Publication #12473). Because space usually critical adaptor design, 10BASE2 easily accommodated form-factor card. However, space extremely critical motherboard design, advantageous keep 10BASE2 separate module. implemented very small add-in card, which effectively mounted only bracket. would include DC-to-DC convertor, transceiver chip (Am7996/7), additional external components, connector. This also eliminates need special "knock-out" case allow mounting 10BASE2 connector. signals power provided from motherboard jumper cable that plugs into header. Care should taken ensure that cable used connect motherboard provides adequate shielding signals from external noise.
Network Characteristics
2.2.4 Automatic Selection highly desireable feature that integrated into PCnet-ISA ability automatically determine which network connection use. When auto select (ASEL, ISACSR3) set, 10BASE-T port selected link pass state disable link test (DLNKTST, CSR15) been (effectively forcing 10BASE-T port into link pass). 10BASE-T port enters link fail state because receive inactivity, PCnet-ISA automatically switches port activity.
Network Characteristics
CHAPTER
CHAPTER Power Saving Security Features
Power Saving
PCnet-ISA supports hardware power-savings modes. Both entered driving SLEEP LOW. addition, PCnet-ISA offers third, reduced-power mode operation using External Address Detection Interface(EADI), although this primary purpose feature. Security section later this chapter details EADI operation use. 3.1.1 Sleep sleep mode PCnet-ISA goes into deep sleep with support automatically wake itself Sleep mode enabled when AWAKE configuration register (ISACSR2) reset. This mode default power-down mode. 3.1.2 Auto-Wake auto-wake mode, enabled setting AWAKE ISACSR2 driving SLEEP LOW, twisted-pair media attachment unit receive circuitry remains enabled, even while SLEEP driven LOW. LED0 output continues function, indicating good 10BASE-T link link beat pulses valid packet data present. This LED0 used drive external hardware that directly controls deactivation SLEEP pin. This configuration used auto-wake PCnet-ISA part host system. Control reactivation various system parts (when there activity 10BASE-T link) left designer, which provides maximum flexibility product differentiation. Auto-wake mode used only T-MAU selected network port.
Remote Wake (Security)
External Address Detection Interface (EADI) used implement alternative address recognition schemes outside PCnet-ISA complement physical, logical, promiscuous detection supported internally. This interface usually provided allow external perfect address filtering. This feature typically utilized bridge, router, terminal server-type products. However, case PCnet-ISA intended used primarily network security feature. External logic required capture serial stream from PCnet-ISA compare with table stored addresses identifiers. address matching support logic necessary capture present relevant data external table address application-specific. entire 802.3 packet after start frame delimiter (SFD) made available, recognition limited destination address, type (Ethernet), length (802.3) fields. Internetworking protocol recognition performed specific header information fields. diagram below shows block diagram implementation store detect multiple addresses external content-addressable memory (CAM) device. 3.2.1 EADI Standard Operation EADI interface operates directly from non-return zero (NRZ) decoded data clock recovered Manchester decoder. This allows external address detection performed parallel with frame reception address comparison station address detection (SAD) block.
Power Saving Security Features
serial receive data clock (SRDCLK) allows clocking receive stream from PCnet-ISA into external address detection logic. SRDCLK runs only during frame reception activity. Once received packet commences data clock available from decoder, EADI logic monitors alternating (1,0) preamble pattern until ones start frame delimiter (1,0,1,0,1,0,1,1) detected, which point start frame/byte delimeter (SF/BD) output driven high. After SF/BD asserted, data from serial receive data (SRD) should deserialized sent other address detection device.
EADI Interface 74LS595 SRDCLK SF/BD EAM/R SRCK 74LS245 Data Programming Interface
74LS595 SRCK
74LS245 Data
Logic Block MTCH Am99C10
16850A-018A
Figure EADI Simple External Interface allow simple serial-to-parallel conversion, SF/BD serves strobe marker indicate delineation bytes subsequent SFD. This provides mechanism that allows only capture decoding physical logical (group) address, also facilitates capture header information determine protocol internetworking information. external address reject (EAR) driven external address comparison logic reject incoming packet. PCnet-ISA configured with both physical logical address fields operational. internal address match detected comparison with either physical logical address field, packet accepted regardless condition EAR. Incoming packets that pass internal address comparison continue received PCnet-ISA. signal must externally presented PCnet-ISA prior first assertion request (DRQ) signal guarantee rejection unwanted packets. This allows approximately 58-byte times after last destination address available generate signal, assuming PCnet-ISA configured accept runt packets. signal will ignored PCnet-ISA from 64-byte times after SFD, packet will accepted been asserted before this time. Power Saving Security Features
PCnet-ISA configured accept runt packets, signal must generated prior receive message completion, which could short 12-byte times (assuming bytes source address, bytes length, data, bytes FCS) after last destination address available. signal must have pulse width least Setting PROM will cause receive packets received, regardless programming input. table below summarizes operation EADI features. PROM Required Timing timing requirements timing requirements within bits after Received Messages Received Frames Received Frames Physical/Logical Matches
Internal/External Address Recognition Capabilities 3.2.2 EADI Security Operation EADI will operate long start (STRT) CSR0 set, even receiver transmitter disabled software (disable transmit (DTX) disable receive (DRX) bits CSR15 set). This useful power-down mode that PCnet-ISA will perform operations, thus saving power utilizing drivers. However, internal operation PCnet-ISA continues normally packet reception will occur, will serial repeating packet data receive clock over EADI. External circuitry implemented interface EADI pins wait match based specific receive frame contents (versus address alone). This allows PCnet-ISA associated external logic respond specific frames network thereby facilitate remote node controlled node operation. Some emerging network management protocols such 3Com/IBM Specification10 already implementing requirement enable remote control node. applications requiring network-controlled power security management, EADI PCnet-ISA offers unique solution. only station remotely powered-down, segregated power supply distribution, PCnet-ISA, associated EADI logic, remain active, effectively waiting command reactivate station. Because logic "snooping" receive packet power management distribution under control system designer, station implement security disabling keyboard entry display system powering-down non-critical functions.
IBM/3Com Heterogeneous Management: Application Program Interface: Technical Reference, version 1.0, June 1991.
Power Saving Security Features
Power Saving Security Features
CHAPTER
CHAPTER Considerations Motherboard Layout
Am79C960 PCnet-ISA device implements functions Ethernet node controller, serial interface adapter, 10BASE-T transceiver, Industry Standard Architecture (ISA) interface, leaving designer relatively tasks complete Ethernet design. Still, there some precautions designer should consider when designing Ethernet motherboard. These guidelines will help speed process creating functional node that complies with electromagnetic interference radio frequency interference (EMI/RFI) standards. most important issue consider when adding Ethernet motherboard noise. noise that capacitively coupled PCnet-ISA circuitry potential transmitted onto network. When this happens, network media becomes antenna, radiating high-frequency noise that violate (Federal Communications Commission), VDE, other regulatory specifications. Whether Ethernet functionality disrupted this radiation, design that violates EMI/RFI emission regulations should avoided. Therefore, purpose most layout precautions isolate Ethernet circuitry from noise.
Signal Routing Ethernet Placement
area Ethernet circuitry motherboard should kept free interference from unrelated signal traces. Thus, space surrounding grouped Ethernet components should considered limits when routing other signal paths. minimize burden this places rest motherboard layout, Ethernet circuitry should placed together perimeter board, ideally near corner. This makes sense because PCnet-ISA device should reside near physical media connector backplane. Consideration should also given placement Ethernet circuitry relative other noisy devices board. Am79C960 crystal oscillator, particular, house critical timing mechanisms that sensitive noise. Obvious sources noise such CPU, clock, cache controller, numeric coprocessor should placed some distance away from these components. This restriction should cause serious complications because these devices typically located elsewhere motherboard.
Ground Power Planes
Once Ethernet functional block been placed, should isolated from noise within ground power planes. These layers motherboard should specially etched, creating noise "fences" around some areas noise-free "islands" beneath others (see Figure 19).
Considerations Motherboard Layout
Ground Power Planes Am79C960 PCnet-ISA
Crystal Oscillator Transformer/ Filter Module
Etched Areas Ground Power Planes
10BASE-T Connector
16850A-019A
Figure Recommended Ground Power Plane Etching Scheme 10BASE-T Components etch that almost completely surrounds group Ethernet components should created ground power planes. opening this barrier should oriented such that noise produced rest board does have straight path into isolated area. This barrier effectively prevents noise motherboard from being transmitted network. modular architecture Am79C960, analog functionality contained corner device. precaution against cross-coupled noise between analog digital circuitry, another ground power planes should etched isolate this area from rest chip. Approximately quarter chip should delineated across corner nearest pins This trace will protect analog circuitry from digital interference. Additionally, island should etched into ground power planes provide space media-specific interface components. 10BASE-T media access, these components include filter transformer module twisted-pair wire jack. 10BASE2 access, they inlude DC-to-DC converter, isolation transformer, Am7996 tranceiver, coax connector. 10BASE5, this includes only connector. important that these devices placed over ground power plane, noise easily coupled from ground power planes through these components onto network.
Considerations Motherboard Layout
Dedicated Ethernet Components
Because real estate motherboard premium, designers might tempted economize using some components dual purposes. While might obvious that this good idea, message bears repeating. 4.3.1 Crystal Oscillator Crystal oscillators common elements motherboard. However, using crystal that already fulfills another purpose implement Ethernet timing circuitry good idea. Timing network strictly regimented Ethernet/IEEE 802.3 standard. crystal required Ethernet must must vary more than parts million, 0.01%. Such crystal would probably cost-effective other motherboard applications. addition, crystal specified perform this level achieve this degree accuracy actual circuit. Routing long, multi-purpose signal traces from such critical circuit would likely disrupt performance. highly recommended that high-performance crystal dedicated isolated Ethernet circuitry. Crystals from different vendors should tested actual circuit, models from some manufacturers vary frequency more than others. Different crystal device models require different tuning among surrounding capacitors. However, once capacitors have been tuned specific crystals used production, design does need altered board-by-board basis. 4.3.2 Ethernet Address PROM Another recommended element designing Ethernet motherboard standalone address PROM. possible store unique address Ethernet node other memory devices such BIOS PROM system memory. However, compatible with Novell NetWare, Ethernet address must stored addressing space rather than memory addressing space. Thus, unless designer chooses write driver specific hardware, recommended that stand-alone address PROM used ensure Novell NE2100 software compatibility.
Bypass Capacitors
Bypass capacitors should accompany power ground pins Am79C960 device. However, common practice connecting these capacitors power ground planes near pins should avoided, introduces unwanted inductance that decreases effectiveness capacitors. Instead, bypass capacitors should connected directly Am79C960 pins. pins should then connected power ground with feed-through holes (see Figure 20). Ideally, feed-hrough connections should used space permits. feed-through holes placed either behind capacitor.
Considerations Motherboard Layout
Connection Feed-through holes
Am79C960 PCnet-ISA Ground
Am79C960 PCnet-ISA Ground
16850A-020A
Correct
Incorrect
Figure Recommended Connections Bypass Capacitors
Other Considerations
When implementing design, engineer should employ good board layout practices. Keep signal traces short straight possible. 802.3/Ethernet, nodes separated 10BASE-T. signals received from network travel long, difficult path before reaching motherboard, they noisy amplitude. avoid jeopardizing data further, these signals should routed most direct path from system's physical connector Am79C960 PCnet-ISA device.
Considerations Motherboard Layout
CHAPTER
CHAPTER Software Considerations
NE2100 Compatibility
Network software written LANCE-based NE2100 board should PCnetISA-based board without modifications with exception. Loopback diagnostics written NE2100 fail because, default, PCnet-ISA rejects packets shorter than bytes, even loopback mode. following list differences between PCnet-ISA NE2100 boards from programmer's viewpoint. Subsequent paragraphs give more details about items this list. External loopback rejects packets smaller than bytes unless runt packet accept enabled. byte swap (BSWP), control (ACON), byte control (BCON) bits (bits respectively) control status register (CSR3) used. CSR3 always available, just when stop set. Several bits that reserved LANCE used PCnet-ISA. Setting stop PCnet-ISA equivalent hardware reset. Reset does clear register access port. Memory error (MERR) does turn transmitter receiver PCnet-ISA. PCnet-ISA does require write after read finish software reset. internal registers accessed software. There restrictions minimum size transmit receive buffers. Interrupt bits masked independently. Cyclic reduncy check (CRC) generation omitted individual frames. bytes short packets added stripped automatically. There test mode option accept runt packets. There chip register. widths read write signals programmable. PCnet-ISA contains automatic wake circuit that enabled software. idle state attachment unit interface (AUI) drivers programmable software. choice twisted-pair media attachment unit (T-MAU) programmed determined automatically. 10BASE-T link test disabled software. automatic polarity correction feature T-MAU disabled software. software select T-MAU receiver threshold voltages. meaning three driver outputs programmable software. External address detection must enabled software. PCnet-ISA initialized writing directly registers. number descriptors anything between 65535. PCnet-ISA groups registers that accessed through different ports. initialize (INIT) start (STRT) bits CSR0 same time. PCnet-ISA interrupt processor when starts transmit packet. reception broadcast packets disabled.
Software Considerations
Physical address detection disabled. Internal loopback include exclude Manchester encoder/decoder (MENDEC). FIFO watermarks changed. maximum length direct memory access (DMA) bursts programmable. polling transmit descriptors disabled. transmission two-part deferral algorithm disabled. alternate backoff algorithm selected.
PCnet-ISA Changes
following describes functions that available LANCE behave differently PCnet-ISA without affecting software. 5.2.1 Loopback Loopback software written LANCE will fail PCnet-ISA unless runt packet accept enabled before software run. runt packet accept, default, disabled, packets fewer than bytes will rejected, even loopback mode. runt packet accept mode separate program that executed before LANCE software loaded. This should make LANCE loopback software work long LANCE software does cause hardware reset. hardware reset puts PCnet-ISA back into default state, which runt packet accept mode disabled. Setting stop does affect runt packet accept mode. 5.2.2 Register Differences
5.2.2.1 CSR3 BSWP, ACON, BCON bits used. Writing these positions effect. These bits LANCE used configuring interface. PCnet-ISA hardware reset makes device compatible with NE2100.
PCnet-ISA CSR3 always available, just when stop set.
5.2.2.2 Reserved Bits Several positions reserved LANCE used PCnet-ISA enable features implemented LANCE. NE2100 software that writes zeros these positions will properly PCnet-ISA without modifications.
following bits have been added CSR3: babble mask (BABLM), missed-frame mask (MISSM), memory error mask (MERRM), receive interrupt mask (RINTM), transmit interrupt mask (TINTM), initialization done mask (IDONM), disable transmit two-part deferral (DXMT2PD), enable modified back-off algorithm (EMBA). following bits have been added mode register: disable receive broadcast (DRCVBC), disable receive physical address (DRCVPA), disable link status (DLNKTST), disable automatic polarity correction (DAPC), MENDEC loopback mode (MENDECL), receive threshold (LRT), transmit mode select (TSEL), port select (PORTSEL [1:0]). frame check sequence existing setup, ADD_FCS been added TMD1 field transmit descriptor. 5.2.3 Stopping PCnet-ISA Setting stop PCnet-ISA equivalent hardware reset, with LANCE. Setting stop clears appropriate status bits, does change bits registers that affect configuration device. stop resets disables transmit receive state machines. resets internal FIFO descriptor pointers, data queued FIFOs lost internal descriptor pointers point first descriptors transmit receive descriptor rings.
Software Considerations
stop middle transmit receive operation, PCnet-ISA will complete current burst, will issue TINT RINT interrupt before turns receiver transmitter. PCnet-ISA does violate convention when stop set. set, corresponding buffer been completely filled receiver transmitted transmitter. Before software sets STRT bit, should finish processing packets that already received, reinitialize descriptors, queue transmission outgoing packets that sent before stop set. However, software does have reinitialize configuration registers PCnet-ISA.
5.2.3.1 Register Access Port contents register address port (RAP) changed setting stop hardware reset. This register powers unknown state. LANCE software that expects register access port cleared reset must modified work with PCnet-ISA.
5.2.4 Errors MERR does turn transmitter receiver PCnet-ISA. This unlikely problem with software written LANCE. 5.2.5 Software Reset method generating hardware reset PCnet-ISA simpler than that used NE2100 board. NE2100 read from port base address (hex) starts reset pulse, write port ends pulse. PCnet-ISA only necessary read from port. write needed.
PCnet-ISA Enhancements
This section describes programmable functions PCnet-ISA that available LANCE. software controls these functions writing collection registers that present LANCE writing certain bits that used LANCE registers. 5.3.1 General
5.3.1.1 Accessing Internal Registers Compared LANCE PCnet-ISA many more registers that accessed software-more than fact. Fortunately, most these registers never touched normal networking software. They used debugging production testing only.
PCnet-ISA registers divided into groups: control status registers (CSRs) Configuration Registers (ISACSRs). Accessing either group step procedure. First, software must load register address port (RAP) with number desired register. Then read from write register data port (RDP) access CSRs data port (IDP) access ISACSRs. register access port located base address (hex), register data port base (hex), data port base (hex).
5.3.1.2 Buffer Sizes PCnet-ISA places restrictions minimum size transmit receive buffers. This means that packet made more small buffers containing protocol headers plus more large buffers containing data. These buffers linked together descriptors transmit descriptor ring. 5.3.1.3 Masking Interrupt Bits PCnet-ISA adds capability masking individual sources interrupt. setting appropriate mask bits, software allow some conditions cause interrupts while disabling other classes interrupt.
Software Considerations
5.3.1.4 Dynamic Generation Frame check sequence (FCS) generation enabled disabled packet-bypacket basis. This feature useful bridge applications which packet should passed from network another while preserving original FCS.
enable this feature, disable transmit (DXMTFCS) mode register, then each packet that should sent with generation, ADD_FCS TMD1 field first descriptor that points that packet packet occupies more than buffer, ADD_FCS need only first descriptor.) DXMTFCS disables generation general, while ADD_FCS overrides DXMTFCS individual packet.
5.3.1.5 Automatic Generation Stripping simplify driver software save some bandwidth, PCnet-ISA programmed bytes outgoing packets shorter than bytes remove bytes from incoming packets. Automatic generation enabled setting automatic transmit (APAD_XMT) CSR0, automatic stripping enabled setting automatic strip receive (ASTRP_RCV) same register.
PCnet-ISA uses length field IEEE 802.3 header determine many bytes strip. major difference between Ethernet IEEE 802.3 specifications that Ethernet uses bytes after source address field type field rather than length field. this reason driver that handles Ethernet headers should automatic padding stripping features.
5.3.1.6 Missed Packet Count missed-packet counter (MPC) been added PCnet-ISA record number packets addressed this node that were saved because receiver disabled because FIFO overflowed. This 16-bit counter cleared setting stop using hardware reset. This counter read time, cannot cleared software action other than setting stop bit. When rolls over from 65535 PCnet-ISA sets missed-packet counter overflow (MPCOM) CSR4 issues interrupt signal this interrupt enabled (IENA CSR0 MPCOM CSR4).
This counter eliminates need missed-packet (MISS) CSR0, included compatibility with LANCE. MISS causes interrupt every time packet missed, while causes interrupt only after 65536 packets have been missed. software extend effective length this counter maintaining high-order bytes extended counter computer memory. high-order bytes should incremented interrupt service routine when MPCO interrupt occurs. Because cannot reset software, software calculate number packets missed because last time counter read recording initial value counter subtracting this number from current count. continues count missed packets while receiver disabled. user this feature create network traffic monitor. promiscuous disable receiver bits mode register, missed-packet counter will keep accurate count total number packets transmitted over network.
5.3.1.7 Receive Collision Count PCnet-ISA contains receive collision counter that counts collisions detected while device transmitting. This 16-bit counter (CSR114) cleared setting stop using hardware reset. counter never disabled, regardless state receiver. read only read time, cannot changed software action other than setting stop bit.
Software Considerations
5.3.1.8 Accepting Runt Packets PCnet-ISA made accept properly addressed runt packets through test mode. enable this feature, first write enable test (ENTST) CSR4 enable buffer management unit (BMU) test register (CSR124). Then runt packet accept (RPA) test register. Finally, write zero back ENTST CSR4 disable further accesses test register. Networking software should never bits test register other than bit, because these other bits device into modes that useful only tester. 5.3.1.9 Chip PCnet-ISA 32-bit chip register (CSR88) that contains manufacturer's JEDEC code, part number, version number. JEDEC manufacturer's code Advanced Micro Devices Inc. 00000000001 (binary), part number PCnet-ISA 0003 (hex), version number Therefore contents this 32-bit register fixed 0000 3003 (hex). software information this register verify that working with right part.
5.3.2 Interface
5.3.2.1 Timing widths read write signals PCnet-ISA during transfer programmable configuration registers. value master mode read active (MSRDA) register controls width active portion read signal, while value master mode write active (MSWRA) controls width active portion write signal. Both values interpreted increments. 5.3.2.2 Base Address Programming base address PCnet-ISA registers selected address (IOAM0-1) pins. four possible base addresses hex) 300, 320, 340, 360. software cannot read values these pins. However, find base address indirectly using each possible value turn base address, then trying read chip register. these addresses results expected chip number, then extremely likely that that address right use. 5.3.2.3 Automatic Wake-Up Support PCnet-ISA contains auto-wake circuit that programmed remain active while PCnet-ISA low-power sleep mode. When enabled AWAKE miscellaneous configuration register, this circuit monitors 10BASE-T receiver link test pulses. When detects valid link test sequence, turns LED0 pin, which with external logic used wake rest chip.
5.3.3 Network Interface
5.3.3.1 TSEL state attachment unit interface (AUI) drivers during idle programmable through transmit mode selection (TSEL) mode register. TSEL should zero (the default) IEEE 802.3 Ethernet transformer coupled networks. should direct-coupled Ethernet networks. 5.3.3.2 T-MAU PCnet-ISA offers three ways selecting between available network interfaces (AUI T-MAU). choice made software hardware, made automatically link pulse detection logic. external selection (XMAUSEL) miscellaneous configuration register selects between hardware software. this set, selection made selection (MAUSEL) pin. Otherwise port selection (PORTSEL) bits mode register make choice. only valid choices PORTSEL bits select select T-MAU.
Software Considerations
However, auto select (ASEL) miscellaneous configuration register set, state XMAUSEL ignored, selection made automatically. T-MAU detects valid link pulses receive data (RXD) inputs, T-MAU selected. Otherwise, selected.
5.3.3.3 T-MAU Control Jabber T-MAU detects jabber condition, will CSR4, thus causing interrupt. Setting jabber mask (JABM) CSR4 will mask this interrupt. Link Test Setting DLNKTST mode register (CSR15) will prevent PCnet-ISA from monitoring link pulses. This feature used twisted-pair networks that link pulses. Polarity Setting disable automatic polarity correction (DAPC) mode register (CSR15) disables automatic polarity correction. actual polarity detected T-MAU receiver regardless state DAPC read following rather roundabout way: three drivers programmed indicate actual polarity detected T-MAU. processor test state this driver reading output (LEDOUT) corresponding register. Receive Threshold receiver threshold voltage lowered that PCnet-ISA used with twisted-pair cables that longer than maximum specified 10BASE-T standard. enable this feature mode register (CSR15). 5.3.3.4 Programmable LEDs PCnet-ISA four driver output pins. these (LED0) displays T-MAU link status. LED0 programmable. other three drivers programmed display status more following internal signals from T-MAU: collision, jabber, link, receive status, receive polarity, transmit status.
driver programmed display more than signal, output will logical selected signals. example, receive (RCVE) LED1 (ISACSR5) register, LED1 will active whenever receiving packet. RCVE transmit (XMTE) bits LED1 register both set, LED1 active whenever receiving transmitting. Since network events extremely short, each three programmable driver circuits connected pulse stretcher circuits that will cause LEDs turned long enough humans able notice them. Each pulse stretcher enabled setting pulse stretcher (PSE) appropriate register (ISACSR 5-7). state driver signal before pulse stretcher read time examining LEDOUT appropriate register. This technique used test polarity twisted-pair receiver inputs (normal reversed).
5.3.3.5 External Address Detection external hardware used make PCnet-ISA respond more than physical address, EADIselection (EADISEL) miscellaneous configuration register must set. This causes LED1-3 MAUSEL pins converted EADI pins. When EADISEL set, XMAUSEL same register must zero.
When external address detection hardware used, convenient disable receive broadcast (DRCVBC) mode register, thereby disabling automatic reception broadcast messages. internal physical address detection logic turned setting disable receive physical address (DRCVPA)
Software Considerations
mode register. Also, internal logical address filtering disabled filling logical address filter (LADRF) register with zeros. 5.3.4 Network Software Procedures
5.3.4.1 Initialization Automatic Initialization PCnet-ISA initialized just LANCE setting initialization block memory, then setting INIT CSR0. minor difference that with PCnet-ISA, INIT STRT bits same time, whereas with LANCE these bits should separate operations. Direct Initialization alternative LANCE-type automatic initialization, PCnet-ISA initialized directly writing appropriate control status registers. This alternate method simplifies software somewhat. this method used, INIT CSR0 should set. Descriptor Ring Lengths LANCE restricts sizes descriptor rings integer powers PCnet-ISA removes this restriction. software number transmit receive descriptors number between 65535 loading two's complement desired value into CSR76 receive descriptors CSR78 transmit descriptors.
automatic initialization procedure using initialization block INIT CSR0 only descriptor ring lengths integer powers two. However, software bypass this procedure altogether writing directly control status registers, automatic process first, then write directly CSR76 CSR78 override values automatic process.
5.3.4.2 Transmission Reception Start Transmit Interrupt PCnet-ISA interrupt processor when starts transmit packet. This interrupt occurs corresponding mask (TXSTRin CSR4) cleared. This interrupt masked default. Disable Receive Broadcast reception broadcast packets disabled setting DRCVBC mode register (CSR15). This reduces overhead network protocols that broadcast messages. Disable Physical Address Detection DRCVPA mode register (CSR15), PCnet-ISA will save packets addressed node's physical address. 5.3.4.3 Changing Modes change initialization address register (IADR), LADRF, physical address register (PADR), Mode, receive ring length register (RCVRL), transmit ring length register (XMTRL), FIFO threshold register, activity timer register (DMATBAT), software must first stop CSR0. While necessary LANCE-type automatic initialization after stop been set, necessary clean transmit receive queues described earlier this chapter (Stopping PCnet-ISA). 5.3.4.4 Loopback size loopback packets limited bytes with LANCE. fact, unless runt packet accept mode enabled, loopback packets must legal IEEE 802.3 Ethernet packets bytes more. This means that loopback tests written
Software Considerations
LANCE should modified either increase packet size enable runt packet accept. MENDECL CSR15 determines whether internal loopback includes excludes MENDEC. 5.3.5 Network Performance Tuning
5.3.5.1 FIFO Watermark Selection match PCnet-ISA with characteristics computer's bus, software change transmit receive FIFO watermarks number bytes that must loaded into transmit FIFO before device starts transmit. FIFO watermarks points which transfers start.
receive FIFO, watermark number bytes that must present FIFO trigger burst. transmit FIFO, watermark measured write cycles. FIFO must have enough empty space accommodate that number write cycles before transfer starts. transmit start point number bytes that must loaded into FIFO before PCnet-ISA starts transmitting. These three parameters programmed fields CSR80, FIFO threshold, burst control register. watermarks each have three possible values, while transmit start point four possibilities.
5.3.5.2 Burst Length Control maximum time that PCnet-ISA keeps control system during transfer burst controlled ways. maximum number cycles device uses before giving programmable burst counter CSR80. effect this register disabled setting DMAPLUS CSR4. When DMAPLUS set, transfer continues until FIFO empty full.
Alternatively, maximum time that device hold burst programmable CSR82, timer register. This timer enabled disabled timer CSR4. Both techniques enabled same time. this case PCnet-ISA releases whenever either counter times out.
5.3.5.3 Disabling Descriptor Polling polling transmit descriptors disabled setting disable polling (DPOLL) CSR4. When this set, software must transmit demand (TDMD) CSR0 each time packet send. Disabling polling frees some bandwidth. 5.3.5.4 Disabling Transmission Two-part Deferral transmission two-part deferral algorithm disabled setting disable transmit two-part deferral (DXMT2PD) CSR3. 5.3.5.5 Alternate Backoff Algorithm alternate backoff algorithm selected setting EMBA CSR3.
Software Considerations
Programmable Registers
Although PCnet-ISA more than registers that accessed software, most these registers intended debugging production testing purposes only. following only registers that should accessed network software. Control Status Registers Register CSR0 Contents Status control bits (DEFAULT 0004) 8000 0800 MERR 0080 4000 BABL 0400 RINT 0040 2000 CERR 0200 TINT 0020 1000 MISS 0100 IDON 0010 Lower IADR (maps port Upper IADR (maps port Interrupt masks configuration bits (DEFAULT 8000 0800 MERM 0080 4000 BABLM 0400 RIN0040 2000 0200 TIN0020 1000 MISSM 0100 IDONM 0010 DXMT2PD 0008 0004 0002 0001 EMBA TXSTRT TXSTRJAB JABM INTR IENA RXON TXON 0008 0004 0002 0001 TDMD STOP STRT INIT
CSR1 CSR2 CSR3
CSR4
Interrupt masks; configuration status bits (DEFAULT 0115) 8000 ENTST 0800 APADXMT 0080 0008 4000 DMAPLUS 0400 ASTRPRCV 0040 0004 2000 TIMER 0200 MPCO 0020 RCVCCO 0002 1000 DPOLL 0100 MPCOM 0010 RCVCCOM 0001 Logical address filter
CSR8- CSR11
CSR12- Physical address register CSR14 CSR15 MODE: (DEFAULT 8000 PROM 0800 4000 DRCVBC 0400 2000 DRCVPA 0200 1000 DLNKTST 0100 DAPC MENDECL LRT/TSEL PORTSEL1 0080 0040 0020 0010 PORTSEL0 INTL DRTY FCOLL 0008 0004 0002 0001 DXMTFCS LOOP
CSR76 CSR78 CSR80
RCVRL, descriptor ring length XMTRL, descriptor ring length FIFO threshold burst control. (DEFAULT 2810) bits [13:12] RCVFW, receive FIFO watermark 0000 Request when bytes present 1000 Request when bytes present 2000 Request when bytes present* bits [11:10] XMTSP, transmit start point 0000 Start transmission after bytes have been written 0400 Start transmission after bytes have been written 0800 Start transmission after bytes have been written* 0C00 Start transmission after bytes have been written bits [9:8] XMTFW, transmit FIFO watermark 0000 Start when write cycles made* 0100 Start when write cycles made 0200 Start when write cycles made bits [7:0] Burst Register
*default value
Software Considerations
Control Status Registers (Continued) Register CSR82 CSR88 DMATR, timer Chip (contents 00003003) Contents
CSR112 Missed-packet count CSR114 Receive collision count CSR124 test register: Used only runt packet accept (0004)
Configuration Registers Addr Register MSRDA MSWRA Contents Programs width read signal (DEFAULT Programs width write signal (DEFAULT configuration bits (DEFAULT 0001) 0008 EADISEL 0004 AWAKE 0002 ASEL 0001 XMAUSEL Programs function width LED1 signal (DEFAULT 0084) 8000 0080 0010 LED2 LEDOUT XMTE 0008 0004 0002 0001 RVPE RCVE JABE COLE
LED1
Programs function width LED2 signal (DEFAULT 0008) (Same format LED1) Programs function width LED3 signal (DEFAULT 0090) (Same format LED1)
LED3
Software Considerations
CHAPTER
CHAPTER Jumperless Solution
Description
following design implements PCnet-ISA based PC/AT board (bus master mode) that automatically software configured, requiring hardware adjustments settings. While this implementation specifically addresses add-in board application, identical solution equally applicable motherboard design. This jumperless hardware configures address space, direct memory access (DMA) channel, interrupt number used. board configuration stored PCnet-ISA board EEPROM device (93C46), enabling board remember configuration even after loss power. stored configuration installed automatically upon power-up, using reset signal Industry Standard Architecture (ISA) bus. configuration data also installed software control. configuration data written read software control. design presented here implemented using external hardware that intercepts accesses configuration register (ISACSR3); future versions PCnet-ISA could integrate most this design while maintaining 100% software compatibility. PCnet-ISA board must implement former jumpered functions, namely address decoding, interrupt selection, channel selection. jumperless design, jumper positions replaced with configuration bits stored EEPROM. Loaded into hardware, these bits define functionality address decoder interrupt multiplexers. this design external hardware catches last seven select bits they clocked EEPROM. Future PCnet-ISA silicon
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