®1683 switching regulator controller designed lower conducted radiated

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®1683 switching regulator controller designed lower conducted radiated

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LT1683 Ultralow Noise Push-Pull DC/DC Controller DESCRIPTIO
®1683 switching regulator controller designed lower conducted radiated electromagnetic interference (EMI). Ultralow noise achieved controlling voltage current slew rates external N-channel MOSFET switches. Current voltage slew rates independently optimize harmonic content switching waveforms efficiency. LT1683 reduce high frequency harmonic power much 40dB with only minor losses efficiency. LT1683 utilizes dual output (push-pull) current mode architecture optimized noise topologies. includes gate drivers necessary oscillator, control protection circuitry. Unique error circuitry regulate both positive negative voltages. oscillator synchronized external clock more accurate placement switching harmonics. Protection features include gate drive lockout VIN, opposite gate lockout, soft-start, output current limit, short-circuit current limiting, gate drive overvoltage clamp input supply undervoltage lockout.
Greatly Reduced Conducted Radiated Switching Harmonic Content Independent Control Output Switch Voltage Current Slew Rates Greatly Reduced Need External Filters Dual N-Channel MOSFET Drivers 20kHz 250kHz Oscillator Frequency Easily Synchronized External Clock Regulates Positive Negative Voltages Easier Layout Than with Conventional Switchers
APPLICATIO
Power Supplies Noise Sensitive Communication Equipment Compliant Offline Power Supplies Precision Instrumentation Systems Isolated Supplies Industrial Automation Medical Instruments Data Acquisition Systems
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATIO
0.5W FZT853 1N4148 2N3904 8.2V 23.2k 1.2nF 16.9k 3.3k 3.3k 1.5k 0.22µF 22nF 10nF SHDN SYNC LT1683 RVSL RCSL GATE GATE 68µF Si9422 10µF
Ultralow Noise DC/DC Converter
39µF MIDCOM 31244 MBR0530 MBRS340 22µH 150µF OS-CON 10pF 200V MBRS340 10pF 200V 30pF Si9422 PGND
1683 TA01
OPTIONAL 22µH POSCAP 5V/2A
200µV/DIV
20mV/DIV
7.50k
5µs/DIV
1683 TA01a
30pF
2.49k
Output Noise (Bandwidth 100MHz)
200µVP-P
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LT1683
ABSOLUTE
(Note
RATI
PACKAGE/ORDER ATIO
VIEW GATE SYNC PGND GATE RVSL RCSL SHDN
Supply Voltage (VIN) Gate Drive Current Internal Limit Current Internal Limit SHDN Voltage Feedback Voltage (Trans. 10ms) ±10V Feedback Current 10mA Negative Feedback Voltage (Trans. 10ms) ±10V Operating Junction Temperature Range (Note 40°C 125°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LT1683EG LT1683IG
PACKAGE 20-LEAD PLASTIC SSOP
TJMAX 150°C, 110°C/
Consult Marketing parts specified with wider operating temperature ranges.
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 12V, 0.9V, VREF, RVSL, RCSL 16.9k, 16.9k other pins open unless otherwise noted.
SYMBOL VREF FBREG VNFR INFR NFBREG IESK IESRC VCLH VCLL FBOV PARAMETER Reference Voltage Feedback Input Current Reference Voltage Line Regulation Negative Feedback Reference Voltage Negative Feedback Input Current Negative Feedback Reference Voltage Line Regulation Error Amplifier Transconductance Error Sink Current Error Source Current Error Clamp Voltage Error Clamp Voltage Error Amplifier Voltage Gain Overvoltage Shutdown Soft-Start Charge Current Outputs Drivers Disabled CONDITIONS Measured Feedback VREF 2.7V Measured Negative Feedback with Feedback Open VNFB VNFR 2.7V ±50µA
ELECTRICAL CHARACTERISTICS
1.235
1.250 0.012
1.265 1000 0.03 2.45
UNITS
Error Amplifiers
2.56 1100
2.500 0.009 1500 1.27 0.12
0.03 2200 2500
µmho µmho
VREF 150mV, 0.9V VREF 150mV, 0.9V High Clamp, Clamp, 1.5V
1.47
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LT1683
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 12V, 0.9V, VREF, RVSL, RCSL 16.9k, 16.9k other pins open unless otherwise noted.
SYMBOL fMAX fSYNC VSYNC RSYNC DCMAX VGON VGOFF IGSO IGSK VINUVLO tIBL VSENSE VSENSEF VSLEWR VSLEWF VISLEWR VISLEWF VINMIN IVIN VSHDN VSHDN ISHDN IV5SC PARAMETER Switch Frequency Synchronization Frequency Range SYNC Input Threshold SYNC Input Resistance Maximum Switch Duty Cycle Gate Voltage Gate Voltage Gate Source Current Gate Sink Current Gate Drive Undervoltage Lockout (Note Switch Current Limit Blanking Time Sense Voltage Shutdown Voltage Sense Voltage Fault Threshold Output Voltage Slew Rising Edge Output Voltage Slew Falling Edge Output Current Slew Rising Edge Voltage) Output Current Slew Falling Edge Voltage) Minimum Input Voltage (Note Supply Current (Note Shutdown Turn-On Threshold Shutdown Turn-On Voltage Hysteresis Shutdown Input Current Hysteresis Reference Voltage Reference Short-Circuit Current 6.5V 20V, 6.5V 20V, 6.5V Source 6.5V Sink RVSL RCSL RVSL RCSL RVSL RCSL RVSL RCSL VGCL RVSL RCSL 17k, RVSL RCSL 17k,
ELECTRICAL CHARACTERISTICS
CONDITIONS
UNITS
Oscillator Sync Oscillator Frequency 250kHz
10.7 0.35
Gate Drives (Specifications Apply Either Unless Otherwise Noted) RVSL RCSL 4.85k, Frequency 25kHz VGCL 6.5V, Gates Enabled Pulled
10.4
Current Sense 2.55 1.31 4.85 4.80 1.39 1.48 5.20 5.15 V/µs V/µs V/µs V/µs
Slew Control (for Following Slew Tests Test Circuit Figure
Supply Protection
Note Absolute Maximum Ratings those values beyond which life device impaired. Note Supply current specification includes loads each gate Figure Actual supply currents vary with operating frequency, operating voltages, load, slew rates type external FET. Note LT1683E guaranteed meet performance specifications from 70°C. Specifications over -40°C 125°C operating range
assured design, characterization correlation with statistical process controls. LT1683I guaranteed tested over 125° operating temperature range. Note Output gate drivers will enabled this voltage. voltage will also determine drivers' activity. Note Gate drivers ensured when greater than maximum value.
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LT1683 TYPICAL PERFOR CHARACTERISTICS
Feedback Voltage Input Current Temperature
1.260 1.258 1.256 NEGATIVE FEEDBACK VOLTAGE TEMPERATURE (°C)
1683
FEEDBACK VOLTAGE
1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240
Feedback Overvoltage Shutdown Temperature
1.70 1.65 1.60 FEEDBACK VOLTAGE 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 TEMPERATURE (°C)
1683
TRANSCONDUCTANCE (µmho)
1600 1500 1400 1300 1200 1100 1000 TEMPERATURE (°C)
1683
CURRENT (µA)
Threshold Clamp Voltage Temperature
VOLTAGE (mV) VOLTAGE
SHDN VOLTAGE
TEMPERATURE (°C)
1683
Negative Feedback Voltage Input Current Temperature
2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 INPUT CURRENT (µA) TEMPERATURE (°C)
1683
Error Transconductance Temperature
2000 1900 1800 1700 -100 -200 -300 -400
Trip Fault Voltage Temperature
1.50
INPUT CURRENT (nA)
FAULT TRIP
Error Output Current Feedback Voltage from Nominal
-40°C 25°C 125°C
-500 -400 -300 -200 -100 FEEDBACK VOLTAGE FROM NOMINAL (mV)
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SHDN Thresholds Temperature
1.45 1.40
1.35
1.30
TEMPERATURE (°C)
1683
1.25
TEMPERATURE (°C)
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LT1683 TYPICAL PERFOR CHARACTERISTICS
SHDN Hysteresis Current Temperature
SHDN CURRENT (µA) CURRENT (mA) RCSL, RVSL 5.7k RCSL, RVSL RCSL, RVSL VOLTAGE TEMPERATURE (°C)
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TEMPERATURE (°C)
1683
Slope Compensation
GATE DRIVE VOLTAGE PERCENT VOLTAGE 0.9V 25°C 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 9.90 9.80 DUTY CYCLE
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LOAD
GATE DRIVE VOLTAGE
Gate Drive Undervoltage Lockout Voltage Temperature
CURRENT (µA) VOLTAGE TEMPERATURE (°C)
1683
TEMPERATURE (°C)
1683
VOLTAGE
Current Temperature
WITH EXTERNAL MOSFETs
Transfer Function
25°C
VOLTAGE (mV)
1683
Gate Drive High Voltage Temperature
0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05
Gate Drive Voltage Temperature
LOAD
9.70
TEMPERATURE (°C)
1683
TEMPERATURE (°C)
1683
Soft-Start Current Temperature
VOLTAGE 0.9V 5.06 5.04 5.02 5.00 5.08
Voltage Load Current
125°C
25°C
-40°C 4.98 4.96
LOAD CURRENT (mA)
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LT1683
CTIO
Part Supply
(Pin This provides output that sink source 10mA external components. source current comes from Sink current goes GND. must greater than 6.5V order this voltage regulation. this used, small capacitor (<1µF) placed this reduce noise. This left open used. (Pin 11): Signal Ground. internal error amplifier, negative feedback amplifier, oscillator, slew control circuitry, regulator, current sense bandgap reference referred this ground. Keep connection this pin, feedback divider compensation network free large ground currents. SHDN (Pin 14): shutdown disable switcher. Grounding this will disable internal circuitry. Increasing SHDN voltage will initially turn internal bandgap regulator. This provides precision threshold turn rest SHDN increases past 1.39V internal regulator turns enabling control logic circuitry. 24µA current sourced above turn threshold. This used provide hysteresis shutdown function. hysteresis voltage will Thevenin resistance resistor divider driving this times current sourced out. Above approximately 2.1V hysteresis current removed. There approximately 0.1V voltage hysteresis this well. tied high instance). (Pin 17): Input Supply. supply current part comes from this including gate drives regulator. Charge current gate drives produce current pulses hundreds milliamperes. Bypass this with capacitor. When below 2.55V part will into supply undervoltage lockout where gate drivers driven low. This, along with gate drive undervoltage lockout, prevents unpredictable behavior during power PGND (Pin 20): Power Driver Ground. This ground comes from MOSFET gate drivers. This have several hundred milliamperes current when external MOSFETs being turned off.
Oscillator
SYNC (Pin SYNC used synchronize part external clock. oscillator frequency should close external clock frequency. Synchronizing clock external reference useful creating more stable positioning switcher voltage current harmonics. This left open tied ground used. (Pin oscillator capacitor used conjunction with oscillator frequency. 16.9k: COSC(nf) 129/fOSC(kHz) (Pin oscillator resistor used charge discharge currents oscillator capacitor. nominal value 16.9k. possible adjust this resistance ±25% oscillator frequency more accurately.
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LT1683
CTIO
Gate Drive
GATE GATE (Pins 19): These pins connect gates external N-channel MOSFETs. GATE GATE turn with alternate clock cycles. These drivers capable sinking sourcing least 300mA. sets upper voltage gate drive. gate pins will activated until reaches minimum voltage defined (gate undervoltage lockout). gate drive outputs have current limit protection safe guard against accidental shorts. gate drive voltage greater than about opposite gate drive inhibited thus preventing cross conduction. (Pin This sets maximum gate voltage GATE GATE pins MOSFET gate drives. This should either tied Zener, voltage source VIN. tied Zener voltage source, maximum gate drive voltage will approximately VGCL 0.2V. tied VIN, maximum gate voltage approximately 1.6. Approximately 50µA current sourced from this VGCL 0.8V. This also controls undervoltage lockout gate drives. tied Zener voltage source, gate drive will enabled until VGCL 0.8V. this tied VIN, then undervoltage lockout disabled. There internal Zener tied from this ground provide fail-safe maximum gate voltage. voltage slew rate inversely proportional this capacitance proportional current that part will sink source this pin. That current inversely proportional RVSL. RCSL (Pin 15): resistor ground sets current slew rate external drive MOSFETs during switching. minimum resistor value 3.3k maximum value 68k. time slew between states MOSFET current will determine di/dt related harmonics reduced. This time proportional RCSL (the current sense resistor) maximum current. Longer times produce greater reduction higher frequency harmonics. RVSL (Pin 16): resistor ground sets voltage slew rate drains external drive MOSFETs. minimum resistor value 3.3k maximum value 68k. time slew between states MOSFET drain voltage will determine harmonics reduced from this source. This time proportional RVSL, CVA/B input voltage. Longer times produce more rolloff harmonics. CVA/B equivalent capacitance from drain MOSFET.
Slew Control
(Pins 18): These pins feedback nodes external voltage slewing capacitors. Normally small capacitor connected from this drain respective MOSFET.
Switch Mode Control
(Pin allows ramping switch current threshold startup. Normally capacitor placed this ground. internal current source will charge this capacitor voltage cannot exceed voltage Thus peak current will ramp ramps During short circuit fault will discharged ground thus reinitializing softstart. When below clamp voltage will closely track pin. This left open used.
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LT1683
CTIO
(Pin This input current sense amplifier. used both current mode control current slewing external MOSFETs. Current sense accomplished sense resistor (RS) connected from sources external MOSFETs ground. connected Current sense referenced pin. switch maximum operating current will equal 0.1V/RS. 0.1V, gate drivers will immediately turned slew control). 0.22V addition drivers being turned off, will discharged ground (short-circuit protection). This will hasten turn subsequent cycles. (Pin feedback used positive voltage sensing. inverting input error amplifier. noninverting input this amplifier connects internally 1.25V reference. voltage this exceeds reference 220mV, then output drivers will immediately turn external MOSFETs slew control). This provides output overvoltage protection When this input below 0.9V then current sense blanking will disabled. This will assist start (Pin 10): negative feedback used sensing negative output voltage. connected inverting input negative feedback amplifier through 100k source resistor. negative feedback amplifier provides gain -0.5 pin. nominal regulation point would -2.5V NFB. This should left open used. being used then overvoltage protection will occur 0.44V below regulation point. -1.8 current sense blanking will disabled. (Pin 12): compensation used frequency compensation current limiting. output error amplifier input current comparator. Loop frequency compensation performed with network connected from ground. voltage proportional switch peak current. normal range voltage this 0.25V 1.27V. However, during slope compensation upper clamp voltage allowed increase with compensation. During short-circuit fault will discharged ground.
TEST CIRCUITS
20mA A/CAP IN5819
A/CAP 0.9A IN5819
GATE A/GATE
Figure Typical Test Circuitry
ZVN3306A
GATE A/GATE
Si4450DY
1683 F01a
1683 F01b
Figure Test Circuit Slew
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LT1683
BLOCK DIAGRA
100k NEGATIVE FEEDBACK GATE VREG
1.25V
COMP
OSCILLATOR
SYNC
RCSL SHDN RCSL RVSL RVSL DRIVERS REGULATOR GATE ERROR SLEW CONTROL PGND
SENSE RSENSE
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LT1683
OPERATIO
noise sensitive applications switching regulators tend ruled power supply option their propensity generating unwanted noise. When switching supplies required efficiency input/output constraints, great pains must taken work around noise generated typical supply. These steps include post regulator filtering, precise synchronization power supply oscillator external clock, synchronizing rest circuit power supply oscillator halting power supply switching during noise sensitive operations. LT1683 greatly simplifies task eliminating supply noise enabling design inherently noise switching regulator power supply. LT1683 fixed frequency, current mode switching regulator with unique circuitry control voltage current slew rates output switches. Current mode control provides excellent line regulation simplifies loop compensation. Slew control capability provides much greater control over power supply components that create conducted radiated electromagnetic interference. Compliance with standards will easier task will require fewer external filtering components. LT1683 uses external N-channel MOSFETs power switches. This allows user tailor drive conditions wide range voltages currents. CURRENT MODE CONTROL Referring block diagram. switching cycle begins with oscillator discharge pulse, which resets flip-flop, turning external MOSFET drivers. switch current sensed across external sense resistor resulting voltage amplified compared output error amplifier pin). driver turned once output current sense amplifier exceeds voltage pin. this pulse pulse current limit achieved. toggle flipflop ensures that MOSFETs enabled alternate clock cycles. Internal slope compensation provided ensure stability under high duty cycle conditions.
Output regulation obtained using error switch current trip point. error transconductance amplifier that integrates difference between feedback output voltage internal 1.25V reference. output error adjusts switch current trip point provide required load current desired regulated output voltage. This method controlling current rather than voltage provides faster input transient response, cycle-by-cycle current limiting better output switch protection greater ease compensating feedback loop. used loop compensation current limit adjustment. During normal operation voltage will between 0.25V 1.27V. external clamp used lowering current limit. negative voltage feedback amplifier allows direct regulation negative output voltages. voltage gets amplified gain driven input, i.e., regulates -2.5V while amplifier output internally drives 1.25V normal operation. negative feedback amplifier input impedance 100k (typ) referred ground. Soft-Start Control switch current during start obtained using pin. external capacitor from ground charged internal current source. voltage cannot exceed voltage Thus ramps voltage will allowed ramp This will then provide smooth increase switch maximum current. will discharged result voltage exceeding short circuit threshold approximately 0.22V. Slew Control Control output voltage current slew rates achieved feedback loops. loop controls MOSFET drain dV/dt other loop controls MOSFET dI/dt. voltage slew rate uses external capacitor between respective MOSFET drain. These integrating caps close voltage feedback loop. external resistor RVSL sets current integrator.
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LT1683
OPERATIO
voltage slew rate thus inversely proportional both value capacitor RVSL. current slew feedback loop consists voltage across external sense resistor, which internally amplified differentiated. derivative limited value RCSL. current slew rate thus inversely proportional both value sense resistor RCSL. control loops combined internally that smooth transition from current slew control voltage slew control obtained. When turning driver current will slew before voltage. When turning off, voltage will slew before current. general desirable have RVSL RCSL similar value. Internal Regulator Most control circuitry operates from internal 2.4V dropout regulator that powered from VIN. internal dropout design allows vary from 2.7V with stable operation controller. When SHDN 1.3V internal regulator completely disabled. Regulator regulator provided powering external circuitry. This regulator draws current from requires greater than 6.5V regulation. sink source 10mA. output current limited prevent against destruction from accidental short circuits. Safety Protection Features There several safety protection features chip. first overcurrent limit. Normally gate drivers will when output internal sense amplifier exceeds voltage pin. clamped such that maximum output current attained when voltage 0.1V. that level outputs will immediately turned slew). effect this control that output voltage will foldback with overcurrent. addition, voltage exceeds 0.22V, pins will discharged ground also, resetting softstart function. Thus short present this will allow faster MOSFET turnoff less MOSFET stress.
voltage exceeds regulation approximately 0.22V, outputs will immediately low. implication that there overvoltage fault. voltage determines features. first maximum gate drive voltage. This will protect MOSFET gate from overvoltage. With tied Zener external voltage source then maximum gate driver voltage approximately VGCL 0.2V. tied VIN, then maximum gate voltage determined approximately 1.6V. There internal Zener that prevents gate driver from exceeding approximately 19V. addition, voltage determines undervoltage lockout gate drives. This feature disables gate drivers provide adequate voltage turn MOSFETs. This helpful during start insure MOSFETs have sufficient gate drive saturate. tied voltage source Zener less than 6.8V, gate drivers will turn until exceeds voltage 0.8V. VGCL above 6.5V, gate drives insured 7.3V they will turned VGCL 0.8V. tied VIN, gate drivers always enabled (undervoltage lockout disabled). When driving push pull transformer, important make sure that both drivers same time. Even though runaway cannot occur under such cross conduction with this chip because current slew regulated, increased current would possible. This chip opposite gate lockout whereby when MOSFET other MOSFET cannot turned until gate first drops below This insures that cross conduction will occur. gate drives have current limits drive currents. sink source current greater than 300mA then current will limited. regulator also internal current limiting that will only guarantee ±10mA output current.
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LT1683
OPERATIO
There also chip thermal shutdown circuit that will turn outputs event chip temperature rises dangerous levels. Thermal shutdown hysteresis that will cause frequency (<1kHz) oscillation occur chip heats cools down. chip undervoltage lockout feature that will force gate drivers event that drops below
Table Safety Protection Features
FEATURE Maximum Current Fault Short-Circuit Fault Overvoltage Fault Clamp Gate Drive Undervoltage Lockout Thermal Shutdown Opposite Gate Lockout FUNCTION Turn FETs Maximum Switch Current (VSENSE 0.1) Turn FETs Reset Short-Circuit (VSENSE 0.2)
Undervoltage Lockout Gate Drive Source Sink Current Limit Source/Sink Current Limit Shutdown
2.5V. This insures predictable behavior during start shut down. SHDN used conjuction with external resistor divider completely disable part input voltage low. This used insure adequate voltage reliably converter. section Applications Information. Table summarizes these features.
EFFECT GATE DRIVERS SLEW CONTROL EFFECT Immediately Goes Immediately Goes Immediately Goes Limits Voltage Immediately Goes Immediately Goes Inhibits Turn Opposite Driver Immediately Goes Limit Drive Current None Overridden Overridden Overridden None Overridden Overridden None None Discharge None None None None None Turn Drivers VREG 0.22V (Output Overvoltage) Gate Voltage Prevent Gate Breakdown Disable Gate Drives When Low. Turn Drivers Chip Temperature Prevents Opposite Driver from Turning Until Driver (Cross Conduction Transformer) Disable Part When 2.55V Limit Gate Drive Current Limit Current from Disable Part When SHDN <1.3V Overridden None None None None None
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LT1683
APPLICATIO ATIO
Reducing from switching power supplies traditionally invoked fear designers. Many switchers designed solely efficiency such produce waveforms filled with high frequency harmonics that then propagate through rest system. LT1683 provides control over more important variables controlling with switching inductive loads: switch voltage slew rate switch current slew rate. this part will reduce noise over conventional switch mode controllers. Because these variables under control, supply built with this part will exhibit less tendency create less chance encountering problems during production. beyond scope this data sheet into fundamentals. Application Note contains much information concerning noise switching regulators should consulted. Oscillator Frequency oscillator determines switching frequency therefore fundamental positioning harmonics. good quality external components important ensure oscillator frequency stability. oscillator sawtooth design. current defined external resistor used charge discharge capacitor discharge rate approximately times charge rate. allowing user have control over both components, trimming oscillator frequency more easily achieved. external capacitance chosen
2180
where desired oscillator frequency kHz. equal 16.9k, this simplifies
f(kHz)
e.g., 1.29nF 100kHz
Nominally should 16.9k. Since sets current, temperature coefficient should selected compliment capacitor. Ideally, both should have temperature coefficients. Oscillator frequency important noise reduction ways. First lower oscillator frequency lower waveform's harmonics, making easier filter them. Second oscillator will control placement output voltage harmonics which specific problems where might trying avoid certain frequency bandwidth. Oscillator Sync more precise frequency desired (e.g., accurately place harmonics) oscillator synchronized external clock. timing components oscillator frequency lower than desired sync frequency. Drive SYNC with square wave (with greater than 1.4V amplitude). rising edge sync square wave will initiate clock discharge. sync pulse should have minimum pulse width 0.5µs. careful sync'ing frequencies much different from part since internal oscillator charge slope determines slope compensation. would possible into subharmonic oscillation sync doesn't allow charge cycle capacitor initiate slope compensation. general, this will problem until sync frequency greater than times oscillator free-run frequency. Slew Rate Setting primary reason this part gain advantage lower noise slew control. rolloff higher frequency harmonics theoretical basis with primary components. First, clock frequency sets fundamental positioning harmonics second, associated normal frequency rolloff harmonics.
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LT1683
APPLICATIO ATIO
This part creates second higher frequency rolloff harmonics that inversely depends slew time, time that voltage current spends between state state. This time adjustable through choice slew resistors, external resistors ground RVSL RCSL pins external components used external voltage feedback capacitors CAV, (from their respective MOSFET drains) sense resistor. Lower slew rates (longer slew times, lower frequency harmonics rolloff) created with higher values RVSL, RCSL, CAV, current sense resistor Setting voltage current slew rates should done empirically. most practical determining these components CAV, sense resistor value. Then, start making RVSL, RCSL each resistor series with 3.3k. Starting from lowest resistor setting (fast slew) adjust pots until noise level meets your guidelines. Note that slower slewing waveforms will dissipate more power that efficiency will drop. monitor this make your slew adjustment measuring input output voltage their respective currents. Monitor MOSFET temperature slew rates slowed. These components will heat efficiency decreases. Measuring noise should done carefully. easy introduce noise poor measurement techniques. Consult AN70 recommended measurement techniques. Keeping probe ground leads very short essential. Usually will desirable keep voltage current slew resistors approximately same. There circumstances where better optimization found adjusting each separately, these values separated further, loss independence control occur. possible single slew setting resistor. this case RVSL RCSL pins tied together. resistor with value 1.8k (one half individual resistors) then tied from these pins ground. general only RCSL value will available adjustment current slew. current slew time does also depend current sense resistor this resistor
normally with consideration maximum current MOSFETs. Setting voltage slew also involves selection capacitors CAV, CBV. voltage slew time proportional output voltage swing (basically input voltage), external voltage feedback capacitor RVSL value. Thus higher input voltages smaller capacitors will used with lower RVSL values. starting point Table
Table
INPUT VOLTAGE 100V CAPACITOR VALUE 2.5pF
Smaller value capacitors made ways. first simply combining capacitors series. equivalent capacitance then C2)/(C1 C2). second method makes capacitor divider. Care should taken that voltage ratings capacitors satisfy full voltage swing input voltage pushpull configurations) thus essentially same rating MOSFETs.
MOSFET DRAIN
1683
Figure
equivalent slew capacitance Figure C2)/ C3). Positive Output Voltage Setting Sensing positive output voltage usually done using resistor divider from output pin. positive input error connected internally 1.25V bandgap reference. will regulate this voltage. Referring Figure determined
1.25
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LT1683
APPLICATIO ATIO
bias current represents small error usually ignored values R1||R2 10k. word caution, sometimes feedback zero added control loop placing capacitor across feedback capacitively pulls above internal regulator voltage (2.4V), output regulation disrupted. series resistance with feedback eliminate this potential problem. There internal clamp that clamps 0.7V above regulation voltage that should also help prevent this problem.
1683
VOUT
Figure
Negative Output Voltage Setting Negative output voltage sensed using pin. this case regulation will occur when -2.5V. nominal input bias current -25µA (INFB), which needs accounted setting divider. Referring Figure chosen such that:
VOUT 25µA
suggested value 2.5k. normally left open being used.
INFB
1683
-VOUT
Figure
Dual Polarity Output Voltage Sensing Certain applications benefit from sensing both positive negative output voltages. When doing this each output voltage resistor divider individually previously described. When both pins used,
LT1683 will prevent either output from going beyond output voltage. highest output (lightest load) will dominate control regulator. This technique would prevent either output from going unregulated high load. However, this technique will also compromise output load regulation. Shutdown SHDN pulled low, regulator will turn off. SHDN voltage increased from ground internal bandgap regulator will powered This will 1.39V threshold turn internal regulator that runs most control circuitry regulator. Note after control circuitry powers gate driver activity will depend voltage with respect voltage GCL. SHDN enables internal regulator 24µA current will sourced from that provide hysteresis undervoltage lockout. This hysteresis used prevent part shutdown input voltage from initial high current draw. addition current hysteresis, there also approximately 100mV voltage hysteresis SHDN pin. When SHDN greater than 2.2V, hysteretic current from part will reduced essentially zero. resistor divider used turn threshold then resistors determined following equations. VSHDN VSHDN VHYST ISHDN Reworking these equations yields: (VHYST VSHDN VSHDN) (ISHDN VSHDN) (VHYST VSHDN VSHDN)
SHDN
SHDN (VON
VSHDN)
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LT1683
APPLICATIO ATIO
1.39V 0.1V 23.4k 24µA 1.39V 1.39V 0.1V 1.75k 24µA (20V 1.39V)
wanted turn with hysteresis:
Resistor values could altered further adding Zeners divider string. resistor series with SHDN could further change hysteresis without changing turn voltage. Frequency Compensation Loop frequency compensation accomplished series network output error amplifier pin).
0.01µF CVC2 4.7nF
1683
Figure
Referring Figure main pole formed capacitor output impedance error amplifier (approximately 400k). series resistor creates "zero" which improves loop stability transient response. second capacitor CVC2, typically one-tenth size main compensation capacitor, sometimes used reduce switching frequency ripple pin. ripple caused output voltage ripple attenuated output divider multiplied error amplifier. Without second capacitor, ripple
VCPINRIPPLE
1.25 VRIPPLE VOUT
where VRIPPLE Output ripple (VP-P Error amplifier transconductance Series resistor VOUT output voltage
prevent irregular switching, ripple should kept below 50mVP-P Worst-case ripple occurs maximum output load current will also increased poor quality (high ESR) output capacitors used. addition 0.0047µF capacitor CVC2 reduces switching frequency ripple only millivolts. value will also reduce ripple, loop phase margin inadequate. Setting Current Limit sense resistor sets value maximum operating current. When voltage 0.1V gate drivers will immediately slew control). Therefore sense resistor value should 0.1V/ISW(PEAK), where ISW(PEAK) peak current MOSFETs. ISW(PEAK) will depend topology component values tolerances. Certainly should below saturation current value transformer. voltage 0.22V addition drivers going low, will discharged ground. This provide additional protection event short circuit. discharging MOSFET will stressed hard subsequent cycles since current trip will lower. Turn MOSFETs will normally inhibited about 100ns start every turn cycle. This prevent noise from interfering with normal operation controller. This current sense blanking does prevent outputs from turned event fault. Slewing gate voltage effectively provides additional blanking. Traces SENSE resistor should kept short wide minimize resistance inductance. Soft-Start soft-start used provide control switching current during startup. voltage approximately voltage pin. current source will linearly charge capacitor pin. voltage will thus ramp also. approximate time voltage these pins ramp (1.31V/9µA) approximately 146ms
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LT1683
APPLICATIO ATIO
soft-start current will initiated soon part turns Soft-start will reinititated after short-circuit fault. Thermal Considerations Most power dissipation derived from pin. current depends number factors including: oscillator frequency; loads slew settings; gate charge current. Additional power dissipated sinks current during MOSFET gate discharge. power dissipation will current times sink current times gate drive's discharge current times voltage Because strong component advantageous operate LT1683 possible. always recommended that package temperature measured each application. part internal thermal shutdown minimize chance destruction this should replace careful thermal design. thermal shutdown feature does protect external MOSFETs. separate analysis must done those devices insure that they operating within safe limits. Once power dissipation, PDIS, determined junction temperature then computed TAMB PDIS where TAMB ambient temperature package thermal resistance. 20-pin SSOP, 100°C/W. Magnetics Design magnetics dependent topology. following details design magnetics push-pull converter. this converter transformer usually stores little energy. following equations should considered starting point building prototype. following definitions will used: Input supply voltage Switch-on resistance
Maximum switch current VOUT Desired output voltage IOUT Output current Oscillator frequency Forward drop rectifier Duty cycle major defining equation this topology. Note that output basically filter chopped voltage duty cycle controls output voltage. turns ratio transformer. turns ratio must large enough ensure that transformer voltage equal output voltage plus diode under minimum input conditions. Note transformer operates half oscillator frequency (f).
)[VIN(MIN) (RON RSENSE)]
VOUT
DCMAX maximum duty cycle each driver with respect entire cycle, which consists periods on). effective duty cycle DCMAX. controller, general, determines maximum duty cycle. maximum duty cycle guaranteed value this part. Remember sufficient margin turns ratio account drops transformer windings, worstcase diode forward drops switch voltage. Also very slow slew rates effective reduced. There number ways choose inductance value suggest starting point that selected such that converter continuous IOUT(MAX)/4. your minimum IOUT higher than this your components handle higher peak currents then higher number.
VOUT LPRI ROUT
RSENSE
1683
Figure Push-Pull Topology
1683f
LT1683
APPLICATIO ATIO
Continuous operation occurs when current inductor never goes zero. Discontinuous operation occurs when inductor current drops zero before start next cycle occur with small inductors light loads. There nothing inherently about discontinuous operation, however, converter control operation somewhat different. inductor smaller discontinuous operation peak currents switch, transformer, diodes, inductor capacitor will higher which produce greater losses. continuous operation inductor ripple current must less than twice output current. worst case this maximum input (lowest duty cycle, DCMIN) following will evaluate nominal input since IOUT/4 somewhat arbitrary. Note when both inputs off, inductor current splits between both secondary outputs diode common goes Looking inductor current during time, output ripple current
IOUT IOUT (MIN) IOUT (MIN) IOUT (MAX) IOUT
(VOUT(MIN)
inductance transformer primary should such that when reflected into primary, dominates input current. other words, want magnetizing current transformer small with respect current going through transformer general, then, inductance primary should least five times that reflected input. This ensures that most power will passed through transformer load. also increases power capability converter reduces peak currents that switch will see.
magnetizing current small, below 100mA, then smaller used with higher percentage switch current generated magnetizing current. LPRI
With value set, ripple inductor
(VOUT
However, peak inductor current evaluated maximum load maximum input voltage (minimum DC).
IL(MAX) IL(MAX)
IL(MAX)
magnetizing ripple current shown
IMAG
VOUT LPRI
peak current switch ISW(PEAK) IL(MAX) IMAG This current should less than current limit. Worst-case switch ripple ISW(PEAK) IL(MAX) IMAG push-pull converter maximum switch voltage will VIN. Because voltage slew-controlled, leakage spikes small. MOSFET should have maximum rated switch voltage least higher than VIN. given turns ratio, primary inductance current, transformer designed. design transformer will require analyzing power losses transformer making necessary adjustments. Most transformer companies assist with designing optimal solution. instance Midcom, Inc. (1-800643-2661). Linear Technology's application group also help. example designing ±20% 100kHz converter with output 500mA ripple. Then starting with guess voltage MOSFET plus sense resistor 0.5V 0.5V:
1683f
LT1683
APPLICATIO ATIO
continuous operation IOUT(MIN) IOUT(MAX)/4, inductor ripple (the same output ripple): duty cycle nominal input
VIN(NOM) 47.5 35.3%
VOUT
Then
0.5) 35.3%) 16µH
100kHz
Off-the-shelf components used this inductor. choose 22µH inductor then ripple current maximum input 29.1%)
0.5) 29.1%) 1.03A
22µF 100kHz
maximum inductor current IL(MAX) 1.03A 2.52A
Primary inductance should greater than: LPRI 22µH 6.12 4.1mH secondary inductance would then 4.1mH/6.12 110µH magnetizing ripple current approximately:
IMAG
4.1mH 100kHz
81mA
Peak switch current ISW(PEAK) 2.51A 81mA 494mA Note that discern your magnetizing ripple looking reflected inductance ripple subtracting from switch current ripple. IMAG ripple current switch ISW(MAX) 1.03A 81mA 0.25A Knowing peak switch current back iterate with more accurate switch voltage. would have know FET. case assumptions 0.5V switch voltage valid RSENSE Capacitors Correct choice input output capacitors very important noise switcher performance. Push-pull topologies other noise topologies will general have continuous currents, which reduce requirements capacitance. However, noise depends more capacitors. addition lower also improve efficiency. Input capacitors must also withstand surges that occur during switching some types loads. Some solid tantalum capacitors fail under these surge conditions. Design Note offers more information following brief summary capacitor types attributes.
Aluminum Electrolytic: cost higher voltage. They used this application general will need higher capacitance achieve ESR. Additional nonelectrolytic capacitors required achieve better performance. Specialty Polymer Aluminum: Panasonic come with their series capacitors. While they only available voltages below 16V, they have very good surge capability.
1683f
LT1683
APPLICATIO ATIO
Solid Tantalum: Small size impedance. Typically maximum voltage rating 50V. With large surge currents capacitor need derated need special type such line. OS-CON: Lower impedance than aluminum only available less. Form factor problem. Ceramic: Generally used high frequency high voltage bypass. They resonate with their before becomes dominant. Recent multilayer ceramic (MLC) capacitors provide larger capacitance with ESR.
There continuous improvements being made capacitors consult with manufacturers your specific needs. Input Capacitors input capacitor should have high frequencies since this will important factor concerning much conducted noise created. There separate requirements input capacitors. first supply part's pin. will provide current part itself gate charge current. worst component from point gate charge current. actual peak current depends gate capacitance slew rate, being higher larger values each. total current estimated gate charge frequency operation. Because slewing with this part gate charge spread over longer time period than with normal driver. This reduces capacitance requirements. Typically current will have spikes under 100mA located gate voltage transitions. This charge/ discharge from threshold voltage. Most slewing occurs with gate voltage near threshold. Since part's will typically under many options available choice capacitor. Values
input capacitor just requirement will typically 50µF range with under 0.1. addition part supply, decoupling supply transformer needs considered. this same supply then that capacitor will need increased. However, often with this part transformer supply will higher voltage such separate capacitor. transformer decoupling capacitor will switch current ripple. above switch current computation used estimate capacity these capacitors.
VCAP ISW(MAX)
where VCAP allowed input capacitor. equivalent series resistance cap. general allowed will tenths volts. Output Filter Capacitor output capacitor chosen both capacity ESR. capacity must supply load current switch state. While slew control reduces higher frequency components ripple current capacitor, capacitor magnitude output ripple current controls fundamental component. should also reduce capacitor dissipation. capacitance value computed consideration desired load ripple, duty cycle ESR.
VOUT IL(MAX)
1683f
LT1683
APPLICATIO ATIO
MOSFET Selection
There wide variety MOSFETs choose from this part. part will work with either normal threshold logic level threshold devices 2V). Select voltage rating insure under worst-case conditions that MOSFET will break down. Next choose sufficiently meet both power dissipation capabilities MOSFET package well overall efficiency needs converter. LT1683 handle large range gate charges. However very large charge stability affected. power dissipation MOSFET depends several factors. primary element heating when device addition, power dissipated when device slewing. estimate power dissipation
where average current, ripple current switch, current slew rate, voltage slew rate, oscillator frequency, duty cycle MOSFET on-resistance.
Setting Voltage Setting voltage depends what type MOSFET used desired gate drive undervoltage lockout voltage. First determine maximum gate drive that require. Typically will want least greater than maximum threshold. Higher voltages will lower resistance increase efficiency. certain check maximum allowed gate voltage. Often this some logic threshold MOSFETs only 10V. VGCL needs approximately 0.2V above desired gate threshold. addition needs least 1.6V above gate voltage. tied which will result maximum gate voltage 1.6V. This also controls undervoltage lockout gate drives. undervoltage lockout will prevent MOSFETs from switching until there sufficient drive present. tied voltage source Zener less than 6.8V, gate drivers will turn until exceeds voltage 0.8V. VGCL above 6.5V, gate drives insured 7.3V they will turned VGCL 0.8V. tied VIN, gate drivers always (undervoltage lockout disabled). Approximately 50µA current sourced from this VGCL 0.8V. This could used bias Zener. internal Zener ground that will provide failsafe maximum gate voltage. example using Siliconix Si4480DY which RDS(ON) rated VGCL needs 6.2V needs least 7.6V.
1683f
LT1683
APPLICATIO ATIO
Gate Driver Considerations
general, MOSFETs should positioned close part possible minimize inductance. When part active gate drives will pulled less than 0.2V. When part off, gate drives contain resistor series with diode ground that will offer passive holdoff protection. using some logic level MOSFETs this might sufficient. resistor placed from gate ground, however value should reasonably high minimize losses possible issues. gate drive source current comes from VIN. sink current exits through PGND. general decoupling should placed close these pins. Switching Diodes general, switching diodes should Schottky diodes. Size breakdown voltage depend specific converter. lower forward drop will improve converter efficiency. other special requirements needed. Layout Considerations with switcher careful consideration should given board layout. Because this part reduces high frequency board layout less critical, however high currents voltages still produce need careful board layout eliminate poor erratic performance. Basic Considerations Keep high current loops physically small area. main loops shown Figure power switch loops rectifier loop These loops kept small physically keeping components close another. addition, connection traces should kept wide lower resistance inductances. Components should placed minimize connecting paths. Careful attention ground connections must also maintained. Without getting into elaborate detail careful that currents from different high current loops
coupled into ground paths other loops. Using singular points connection grounds best this. major points connection bottom input decoupling bottom output decoupling cap. Typically sense resistor device PGND device will bottom input cap. There other loops attention current slew involves high bandwidth control that goes through MOSFET switch, sense resistor into part GATE MOSFET. Trace inductance resistance should kept GATE drive trace. trace should have inductance. sense resistor should physically close PGND MOSFETs' sources. Finally care should taken with pins. part will tolerate stray capacitance ground these pins (<5pF) however stray capacitance respective drains should minimized. This path would provide alternate capacitive path voltage slew. More Help AN70 contains information about noise switchers measurement noise should consulted. AN19 AN29 also have general knowledge concerning switching regulators. Also, Application Department always ready lend helping hand.
COUT GATE GATE
1683
Figure
1683f
LT1683
TYPICAL APPLICATIO
0.5W FZT853
10µF 2N3904
23.2k
SHDN SYNC LT1683 RVSL RCSL 10nF
1200pF
16.9k 3.3k 3.3k 0.22µF 22nF
PACKAGE DESCRIPTIO
5.20 5.38** (.205 .212)
7.65 7.90 (.301 .311) (.002 .008)
SSOP 0501
(.005 .009)
(.022 .037)
NOTE: CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS DIMENSIONS (INCHES) DRAWING SCALE *DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED .152mm (.006") SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED .254mm (.010") SIDE
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
Ultralow Noise ±12V DC/DC Converter
47µF 100V CTX0215542 22µF 8.2V MBR01100 GATE GATE Si9422 Si9422 0.068 PGND 8.66k 25pF C2:SANYO 16TPC33 MURATA GRM235Y5V106Z NIPPON THCR60EIE226Z IN4148 MBRS1100 COOPER DS50224 COOPER CTX02-15542 200V 25pF 200V 10µH 33µF 16V, 33µF 16V, -12V/1A 10µH 10.0k 12V/1A 2.74k
1683 TA03
Package 20-Lead Plastic SSOP (5.3mm)
(Reference 05-08-1640)
7.07 7.33* (.278 .289)
1.73 1.99 (.068 .078)
(.0256)
(.010 .015)
1683f
LT1683
TYPICAL APPLICATIO
6.9k 2N3904 68µF 1.5nF 16.9k 3.3k 3.3k 15nF 10nF
SHDN SYNC LT1683 RVSL RCSL
RELATED PARTS
PART NUMBER LT1533 LT1534 LT1738 LT1777 LT1425 LT1576 LT176X Family LTC1922-1 DESCRIPTION Ultralow Noise Switching Regulator Ultralow Noise Switching Regulator Ultralow Noise DC/DC Controller Noise Step-Down Switching Regulator Isolated Flyback Switching Regulator 1.5A, 200kHz Step-Down Switching Regulator Dropout, Noise Linear Regulator Synchronous Phase Modulated Full-Bridge Controller COMMENTS Push-Pull Design Noise Isolated Supplies Ultralow Noise Regulator Boost Topologies High Current Output Ultralow Noise Boost Regulator; Drives External MOSFET Programmable dI/dt; Internally Limited dV/dt Excellent Regulation without Transformer "Third Winding" Constant Frequency, 1.21V Reference Voltage 150mA SOT-23 TO-220 Adaptive DirectSenseZero Voltage Switching, Kilowatts, Synchronous Rectification
DirectSense trademark Linear Technology Corporation.
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900 FAX: (408) 434-0507
Ultralow Noise DC/DC Converter
39µF MBR2045CT 8.2V 6-10 2-12 10pF IRF540 IRF540 PGND
1683 TA02
COILTRONICS VP5-1200 4.7µH 330µF MBR2045CT 10pF
OPTIONAL 5V/5A POSCAP
GATE GATE
7.50k 2.49k
1683f LT/TP 0402 PRINTED
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001

®1683 switching regulator controller designed lower conducted radiated

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