Reset System Startup Configuration PORT0 Register RSTCON Presents

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Reset System Startup Configuration PORT0 Register RSTCON Presents

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Microcontrollers ApNote AP163703
Reset System Startup Configuration PORT0 Register RSTCON
Presents overview about different reset types (power-on reset, long/short hardware reset, software reset, reset) system startup configuration PORT0 register RSTCON. calculation pull-up/down resistors PORT0 also included.
Author: Mariutti
Semiconductor Group
12.99,
Reset System Startup
Contents
Page
Overview about different Reset Sources Hardware Reset Software Reset Watchdog Timer Reset Bidirectional Reset System Startup Configuration PORT0 Configuration during Reset PORT0 Sample Timing different Reset Types System Startup Configuration upon Single-Chip Mode Reset Calculation Pull-up/down Resistors PORT0 Startup Configuration Pull-down Calculation Pull-up Calculation Calculation Pull-down Res. Entry Single-Chip Mode Appendix PORT0 Configuration during Reset Reset, Clock Options Steps
Note: Some products mentioned this Application Note officially announced yet.
AP163703 ApNote Revision History Actual Revision: 12.99 Previous Revision: 6.98 Page actual Rev. Page prev.Rel. updated Device list updated Table updated Notes added chapter "System Startup Configuration upon Single-Chip Mode Reset" Note added chapter "Calculation Pull-down Resistor Entry Single-Chip Mode" Appendix "Reset, Clock Options Steps" updated Subjects (changes since last release) RSTCON title added
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AP163703 12.99
Reset System Startup
Overview about different Reset Sources
During reset, device executes special internal sequence order internal signals Special Function Registers (SFRs) their specified default values. contents some Special Function Registers controlled during system startup configuration PORT0 default value. system startup configuration PORT0 sampled upon different reset events. table Hardware Reset: Power-on Reset Short Hardware Reset (Warm Reset) Long Hardware Reset (Power Down Wakeup Reset)
Software Reset Watchdog Timer Reset
reset source also indicated reset source indication flags register WDTCON.
Reset Source Power-on Reset Short Hardware Reset Long Hardware Reset Watchdog Timer Reset Software Reset Table Reset Sources Reset Conditions
Short-cut PONR SHWR LHWR WDTR
Condition Power-on, tRSTIN 1024 tRSTIN 1024 tRSTIN 1024 overflow SRST command
Hardware Reset
hardware reset triggered when reset input signal RSTIN sampled low. ensure recognition RSTIN signal (latching), must held least clock cycles Clock). Also shorter RSTIN pulses trigger hardware reset, they coincide with latch's sample point. However, microcontrollers with on-chip recommended keep RSTIN guarantee that locked. After reset sequence been completed, RSTIN input sampled again. When reset input signal active (low) that time internal reset condition prolonged until RSTIN gets inactive (high). input RSTIN provides internal pull-up device equalling resistor (the minimum reset time must determined lowest value). Simply connecting external capacitor sufficient automatic power-on reset proper level RSTIN between power reached). RSTIN also connected output other logic gates.
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AP163703 12.99
Reset System Startup
Three different kinds external hardware resets have considered: Power-on Reset complete power-on reset requires active RSTIN time reset sequences 1024 51.2 Clock) after stable clock signal available. Depending oscillation frequency type external oscillator circuit, on-chip oscillator needs about 0.01.50 (quartz crystal: 2.50 ceramic resonator: 0.01.0.5 stabilize. This means that power-on reset time dominant oscillator start-up time. Long Hardware Reset long hardware reset requires active RSTIN time longer than duration internal reset sequence. duration internal reset sequence 1024 (1024 25.6 Clock). long hardware reset also named power down wakeup reset. Short Hardware Reset active RSTIN time short hardware reset between 1024 TCL. RSTIN signal active least clock cycles (100 Clock) internal reset sequence started (1024 TCL, 25.6 Clock). After internal reset sequence been completed, RSTIN input sampled. When reset input still active that time internal reset condition prolonged until RSTIN gets inactive. RSTIN signal active more then 1024 then behaviour PORT0 latch mechanism equal long hardware reset.
Software Reset
reset sequence triggered time protected instruction SRST (Software Reset). This instruction executed deliberately within program, e.g. leave bootstrap loader mode, upon hardware trap that reveals system failure. software reset takes 1024 (25.6 MHz).
Watchdog Timer Reset
When watchdog timer disabled during initialization serviced regularly during program execution will overflow trigger reset sequence. watchdog timer reset releases automatically software reset. Other than hardware reset watchdog timer reset completes running external cycle this cycle either does READY all, READY sampled active (low) after programmed waitstates. When READY sampled inactive (high) after programmed waitstates running external cycle aborted. Then internal reset sequence started. Note: watchdog timer reset cannot occur while device bootstrap loader mode!
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AP163703 12.99
Reset System Startup
Bidirectional Reset
bidirectional reset feature implemented since devices steps listed below. steps parentheses only reflect software- watchdog timer reset RSTIN short hardware reset shown figure
Device C161RI C161CI C161PI C161CS C161OR C164CI-8EM
Step
Device C167CR-LM C167CR-4RM C167CR-16RM C167S-4RM C167CS 167SR
Step (CA), (AB), (BA),
Table Devices with implemented Bidirectional Reset Feature
bidirectional reset mode device's line RSTIN (normally input) driven active chip logic e.g. order support external equipment which required startup (e.g. flash memory).
RSTIN
Internal Circuitry
Reset sequence active BDRSTEN
Figure Bidirectional Reset Operation
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AP163703 12.99
Reset System Startup
Bidirectional reset reflects internal reset sources (software, watchdog) also RSTIN converts short hardware reset pulses minimum duration internal reset sequence. Bidirectional reset enabled setting BDRSTEN register SYSCON (SYSCON.3) changes RSTIN from pure input open drain line with integrated pull-up resistor. When internal reset triggered SRST instruction watchdog timer overflow level applied RSTIN line, internal driver pulls duration internal reset sequence. After that released then controlled external circuitry alone. bidirectional reset function useful applications where external devices require defined reset signal cannot connected device's RSTOUT signal, e.g. external flash memory which must come reset deliver code well before RSTOUT deactivated EINIT. following behaviour differences must observed when using bidirectional reset feature application:
BDRSTEN register SYSCON cannot changed after EINIT. After reset BDRSTEN cleared (bidirectional reset disabled). WDTR will always '0', even after watchdog timer reset. PORT0 configuration treated like hardware reset. Especially bootstrap
loader activated when P0L.4 (RD) low. RSTIN only connected external reset devices with open drain output driver.
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AP163703 12.99
Reset System Startup
System Startup Configuration
Some system features have selected before first instruction program executed. These selections made during reset pins PORT0 which latched reset, fixed configuration value which used when High (single chip mode reset, section details). PORT0 Configuration during Reset
Table shows PORT0 configuration pins which kind reset (sample event) does sample which depending whether bidirectional reset enabled (on) disabled (off).
PORT0
sampled
Mode Invert P0H.7 External Access enable P0L.0
sampled
BDRST
transparent
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
Sample event PONR LHWR SHWR WDTR/SWR LHWR SHWR WDTR/SWR
Table System Startup Configuration PORT0
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AP163703 12.99
disable entry
Adapt Mode
Config.
Segm. Addr. Lines Lines Chip Selects
Reserved
Reserved Reserved
Clock options
Type
Reset System Startup
PORT0 startup configuration sampled either with internal reset sequence with external hardware reset. external RSTIN signal deactivated before internal reset sequence (short hardware reset) then internal reset signal (IRS) device used latch system startup configuration PORT0, else (power-on reset long hardware reset) PORT0 latched after rising edge RSTIN with signal IRS. sampling point PORT0 (prescaler enabled) (direct drive PLL) after rising edge RSTIN shown PORT0 sample timing (see figures below). duration internal reset sequence 1024 initializing internal Special Function Registers plus jump address 00'0000H after internal reset sequence. bidirectional reset feature converts software reset, reset short hardware reset externally visible hardware reset with duration 1024 TCL. This feature disabled after hardware reset enabled software.
PORT0 Sample Timing different Reset Types
different reset sources timing relations PORT0 during reset shown below. reset event occurs then PORT0 switched input mode internal pull-ups active. During that time possible that desired input voltage levels PORT0 (VIH forced internal/external pull-ups pull-downs startup configuration) reached. Therefore PORT0 transparent 1024TCL (power-on reset 2048 TCL) prevent unexpected behaviour system. After that time part PORT0 becomes transparent reset these pins sampled with signal. Depending reset type some PORT0 pins transparent, e.g. P0L.1 P0L.0 which control Adapt Mode Emulation Mode. Noise these lines during reset would force microcontroller Adapt Mode Emulation Mode. Therefore both pins transparent until sample point reset condition. PORT0 sample timings shown below based following conditions: tP0fix: tSHR: IRS: During tP0fix PORT0 constant System Startup Configuration latched correctly. Duration short hardware reset. tSHR 1024 Internal Reset Signal: Sampling point PORT0 configuration bits (prescaler enabled) (direct drive PLL) after rising edge RSTIN after internal reset sequence. *fCPU), Clock
TCL:
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Reset System Startup
2048 RSTIN P0[15:2] P0[1:0] System clock available Figure PORT0 sample Timing: Power-on Reset transparent transparent tP0fix transparent
1024 RSTIN P0[15:2] P0[1:0] transparent transparent tP0fix transparent
Figure PORT0 sample Timing: Long Hardware Reset, Bidirectional Reset enabled disabled tSHR RSTIN P0[12:2] P0[15:13] P0[1:0] transparent transparent transparent 1024 tP0fix Figure PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset disabled transp.
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Reset System Startup
1024 P0[12:6] transparent tP0fix transp.
P0[15:13] P0[5:0] Reset
transparent
Figure PORT0 sample Timing: Software Reset Reset, Bidirectional Reset disabled
1024 RSTIN P0[15:2] P0[1:0] Reset transparent transparent tP0fix transparent
Figure PORT0 sample Timing: Software Reset Reset, Bidirectional Reset enabled
1024 RSTIN P0[15:2] P0[1:0] transparent transparent transparent tP0fix
Figure PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset enabled
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AP163703 12.99
Reset System Startup
Note: characteristic that PORT0[1:0] transparent before latched shown figure only implemented actual devices. PORT0[1:0] characteristic older ones listed below differs that point. these devices PORT0[1:0] transparent same duration PORT0[15:2]. During software reset reset (bidirectional reset disabled) PORT0[1:0] latched therefore transparent, figure
Device C161V C163-L C165 C167CR-LM
Step C167-LM C167S-4RM C167SR-LM
Device
Step BA,BB
C167CR-16RM
Table Devices were PORT0[1:0] transparent during Reset
Note: Latching PORT0 configuration when High different devices with flash chip. devices without single chip-mode reset (RSTCON), i.e. devices included Table5, when level high during reset, configuration P0H.[4:0] P0L.[7:0] latched with internal reset condition, about later (due program Flash voltage ramp-up). This behavoiur should present problem systems where reset configuration realized external resistors PORT0 where other device driving onto PORT0 (the data bus) unless explicitly selected microcontroller under software control otherwise, make sure that reset configuration maintained PORT0 until after internal reset condition that PORT0 switched output external accesses performed during first program execution.
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AP163703 12.99
Reset System Startup
System Startup Configuration upon Single-Chip Mode Reset
single-chip mode reset (indicated High) configuration PORT0 replaced fixed configuration value XX2BH, (see User's Manual chapter "System Startup Configuration upon Single-Chip Mode Reset"). this case PORT0 needs external circuitry (pull-ups/pulldowns) also internal configuration pull-ups activated. This fixed default configuration activated after each long hardware reset (LHWR) power-on reset (PONR). fixed default configuration selects safe worst-case configuration. initialization software then modify these parameters register RSTCON select intended configuration given application. Table includes principle differences system startup configuration related High. column "Configuration Source" shows comparison devices with without register RSTCON.
single-chip mode reset register RSTCON feature implemented since devices listed below. Device C164CI-xRM C164xy-8FM Step AA*) Device C161CS-32RM C167CS-4RM Step
Table Devices with Single-Chip Mode Reset (RSTCON) first step C164CI-4RM -8RM (32/64 Kbyte version), intermediate solution, when High during reset, configuration read from internal address 00.003Eh instead P0H.[7:0], copied into register RP0H. this case, status PORT0 during reset evaluated. Register RSTCON implemented during startup content address 00.003Eh used instead default configuration single-chip mode reset.
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AP163703 12.99
Reset System Startup
Mode
Type Reset BDRST (on/off)
Configuration Behaviour
Configuration Source Device with RSTCON Device without RSTCON P0H[7:5] don't care/P0H[4:3] don't care/P0H[2:1] P0H[0] don't care P0L[5:2] P0L[1] P0L[0] possible don't care don't care/P0H[4:3] P0H[2:1] don't care/P0H[0] don't care P0L[5:2] P0L[1] P0L[0] possible PORT0 off7) PORT0 selected, active high level driven) (active high level driven) (active level driven)
P0H[7:5] clock options PONR, LHWR, (SHWR, WDTR, SWR) BDRST Single Chip Mode High P0H[4:3] segm. addr. lines P0H[2:1] chip select lines P0H[0] configuration P0L[7:6] type P0L[5:2] entry P0L[1] adapt mode P0L[0] emulation mode entry P0H[7:5] clock options P0H[4:3] segm. addr. lines (SHWR, WDTR, SWR) BDRST P0H[2:1] chip select lines P0H[0] configuration P0L[7:6] type P0L[5:2] entry P0L[1] adapt mode P0L[0] emulation mode entry Startup configuration source Reset BDRST on/off PORT0 pull-ups during reset pull-ups after reset pull-ups after reset pull-down after reset Startup configuration source Ext. PORT0 pull-ups during reset Reset BDRST on/off pull-ups after reset pull-ups after reset pull-down after reset Oscillator watchdog disable EA=High PORT0 pull-ups after reset Reset BDRST on/off pull-ups during reset pull-ups during reset pull-down during reset EA=Low
default/RSTCON default/RSTCON default/RSTCON default/RSTCON default/RSTCON possible possible possible RSTCON RSTCON RSTCON RSTCON RSTCON possible possible possible default/RSTCON
Table System Startup Configuration
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AP163703 12.99
Reset System Startup
Adapt mode entry only Low. single-chip mode possible activate adapt mode. mode entry only Low. single-chip mode possible activate emulation mode.
Emulation
Oscillator watchdog disabled test purposes pull-down
system starts single-chip mode external enabled software later, then PORT0 startup configuration used external changed software. P0H[2:1]: signals selected PORT0 will driven active high after reset.
Internal pull-ups active during reset.
Only SHWR. WDTR possible. P0L[5:2]: entry done then clock XTAL1 clock divided (fCPU fOSC/2). This considered appropriate communication baudrate with external host.
signals driven active high after RSTCON copied RP0H. system starts single-chip mode will used external access then depending system demands, external pull-up resistors necessary signals because after reset before RSTCON copied RP0H, signals tristate without defined level (internal pull-ups disabled).
Pull-ups active until BUSACTx register BUSCONx set; then driven active high.
Pull-down
active until BUSACTx register BUSCONx set; then driven active low.
Table System Startup Configuration (cont'd)
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AP163703 12.99
Reset System Startup
Calculation Pull-up/down Resistors PORT0 Startup Configuration
specification Data Sheet includes values PORT0 configuration currents IP0L IP0H. Pull-down Calculation
IP0L base calculation pull-down resistors PORT0 startup configuration. IP0Lmin -100 VILmax. That means that port configuration current greater equal than input voltage lower equal VILmax. system current ISYSL direct influence value needed pull-down resistor. relation between different parameters calculation with example shown below. Note: currents flowing into microcontroller defined positive currents flowing defined negative. Because internal pull-up transistor direction IP0L device therefore sign current specification negative.
RESET 100µA Port VILmax leakage current
C16x
System
Figure System Environment Pull-down Resistor Startup Current Specification Data Sheet: 4.5V 5.5V 0.8V 1.0V IP0L |-100µA|
0.2Vcc 0.1V IP0Lmin -100µA
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Reset System Startup
Pull-down resistor calculation:
ILmax ILmax SYSL
Example without system current: (ISYSL recommended maximum value:
ILmax 100µA 8000
Pull-up Calculation
IP0H base calculation pull-up resistors PORT0 startup configuration. IP0Hmax VIHmin. already mentioned PORT0 supplies internal pull-up resistors which only active during Reset, during Hold-or Adapt-mode. normal systems this internal pull-up resistors sufficient reach input high voltages PORT0 pins. This situation changes when system current ISYSH exceeds Then additional external pull-up resistors mandatory. example system flash memory with high leakage current cause increased ISYSH. calculation example shown below.
RESET 10µA Port VIHmin
leakage current
C16x
System
Figure System Environment Pull-up Resistor Startup
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Reset System Startup
Current Specification Data Sheet: IP0H |-10
IP0Hmax
Pull-up resistor calculation:
CCmin IHmin SYSH
Example: ISYSH 50µA:
67.5 50µA 10µA
recommended maximum value: 67.5
Note: leakage current some hold devices exceeds specified value IP0Hmax µA|. that case PORT0 pins configured level need pull-up resistor. calculation pull-up value please refer specified leakage current hold device.
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Reset System Startup
Calculation Pull-down Resistor Entry Single-Chip Mode
IRWL base calculation pull-down resistor entry when single-chip mode selected. specification Read/Write active current IRWLmin -500µA (VOUT VOLmax) also valid VILmax. That means that read active current greater equal than input voltage lower equal VILmax. system current ISYSL direct influence value needed pull-down resistor. relation between different parameters calculation with example shown below.
Note: currents flowing into microcontroller defined positive currents flowing defined negative. Because internal pull-up transistor direction IRWL device therefore sign current specification negative.
RESET IRWL 500µA VILmax leakage current
C16x
System
Figure System Environment Pull-down Resistor Entry
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Reset System Startup
Current Specification Data Sheet: 4.5V 5.5V 0.8V 1.0V IRWL |-500µA|
0.2Vcc 0.1V IRWLmin= -500µA
Note: Worst case calculation that case ILmax 5.5V
Pull-down resistor calculation:
ILmax ILmax SYSL
Example without system current: (ISYSL
ILmax 1.0V 500µA
recommended maximum value: 2000
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Reset System Startup
Appendix PORT0 Configuration during Reset
CLKCFG
SALSEL
CSSEL
BUSTYP
SMOD
SMOD (P0L.5:2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Emulation Mode Adapt Mode Special Modes reserved reserved reserved reserved reserved reserved reserved External Host Mode (EHM)1) reserved reserved Bootstrap Loader Host Mode1) Bootstrap Loader reserved reserved Host Mode (CHM)1) normal Start
Comment Condition Quality P0H.7 inverted
this combination this combination this combination this combination this combination this combination this combination requires Emulation Mode this combination this combination Serial programming Start from internal boot this combination this combination programming mode normal start defined
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Reset System Startup
BUSTYP (P0L.7:6) CSSEL (P0H.2:1) SALSEL (P0H.4:3) CLKCFG (P0H.7-5)
External Data Width 8-bit Data 8-bit Data 16-bit Data 16-bit Data Write Configuration Chip Select Lines Max: CSx.CS0 None Two: CS1.CS0 Three: CS2.CS0 Segment Address Lines Two: A17.A16 Axx.A16 None Four: A19.A16 Frequency fCPU fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL
External Address Mode Demultiplexed Addresses Multiplexed Addresses Demultiplexed Addresses Multiplexed Addresses
Default without pull-downs Port pins free
Directly accessible Address Space KByte (Default, without pull-downs) (Maximum) KByte (Minimum) MByte Notes2) Default configuration
Direct drive
Prescaler
This modes implemented devices. Please refer User's Manuals. clock configuration bits fully decoded devices steps. Please Appendix User's Manuals detailed information.
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Reset System Startup
Reset, Clock Options Steps
Device
Step
BDRST
RSTCON
Clock Options
Factors
C161RI C161V C161OR C161PI C161CS/JC/JI-32F C161SI/CI-32F C161CS-32R C163-L C163-16F C163-16F C164CI C164CI-8R C164CH-8F C165
AA,BA
VPP/OWE VPP/OWE VPP/OWE VPP/OWE
no5)
1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5
C167 C167CR-LM
1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5
C167CR-4RM
C167CR-16FM C167CR-16RM
1.5/2/2.5/3/4/5
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Reset System Startup
Device
Step
BDRST
RSTCON
Clock Options
Factors
C167CS-32FM C167CS-4RM C167S-4RM
AA,AB,AD,AE,CA,CB
1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5
1.5/2/2.5/3/4/5 2/3/4/5
C167SR-LM
1.5/2/2.5/3/4/5
described options implemented since steps listed below. Oscillator Watchdog (OWD) disabled different kinds. implemented.
VPP/OWE level VPP/OWE disables OWD.
level disables OWD. level type reset disables OWD. level latched with IRS. figure level disables OWD.
Besides other features Power Management (PM) includes Slow Down Divider (SDD). separate clock path selected Slow Down operation bypassing basic clock path used standard operation. programmable Slow Down Divider divides oscillator frequency factor mode effect. Prescaler option Direct drive option clock used prescaler option fOSC 0.5) direct drive option (fCPU fOSC 1.0). first step C164CI-4RM -8RM (32/64 Kbyte version), intermediate solution, when High during reset, configuration read from internal address 00.003Eh instead P0H.[7:0], copied into register RP0H. this case, status PORT0 during reset evaluated. Register RSTCON implemented during startup content address 00.003Eh used instead default configuration single-chip mode reset.
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AP163703 12.99

Reset System Startup Configuration PORT0 Register RSTCON Presents

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