Test Environment ATUSBTESTSS7400 Summary Overview ATUSBTEST-

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Test Environment ATUSBTESTSS7400 Summary Overview ATUSBTEST-

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Simple Command-driven Host Model Comprehensive Reports Monitor Protocol Validation Monitor Comprehensive Test Suite Fully Compliant with Forum Checklist Generates Monitors Packets NRZI, Bit-stuffed, Encoded Packets Error Packets Generated Test Robustness Provides Commands Generate Different Transactions Interfaces with Atmel's Cores ATUSBHUB-SSU8040 ATUSBFUNC-SS7211
Test Environment ATUSBTESTSS7400 Summary
Overview
ATUSBTEST-SS7400 simulation environment designed simulate verify application functionality during initial phases design verify complete application final stages design. typical environment consists these functional blocks: host functional model generate traffic; monitor model monitor traffic; target device core such ATUSBFUNC-SS7211 (full-speed core) ATUSBHUBSSU8040 (hub); application model emulate application. ATUSBTEST-SS7400 includes host functional model with command file interface simple integrated monitor model. ATUSBTEST-SS7400 also includes application model. This model handle control transfers, interrupt transfers, bulk/ISO bulk/ISO transfers. simple command file interface transfer required data simple controls generate STALL RESPONSE from application. This model, course design, easily replaced application's synthesized logic. This test environment supports both low- full-speed implementations, although ATUSBFUNC-SS7211 only allows full speed.
Simple Simulation Environment
Report File: hst_log Monitor Model
Command File: hst_cmds
Host Functional Model
Device Core
Application Model
Command File: app_cmds
Rev. 1669AS-07/01
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Test Environment Guidelines
Setting Test Bench
Users need make sure that ATUSBTEST-SS7400 installed using detailed instructions installation document. Upon successful installation ATUSBTEST-SS7400, following design steps need taken proper simulation verification device under test (DUT). Instantiate host model (from ATUSBTESTSS7400) testbench module. Instantiate instances transceiver model (provided): transceiver connect host model. transceiver connect DUT. Instantiate make appropriate connections transceiver model suggested sample testbench. application portion design developed, user needs instantiate ATUSBFUNC-SS7211 device core sample application model provided with simulate application interface. Upon having instance ATUSBTESTSS7400, transceivers, ATUSBFUNCSS7211 application model, testbench module complete use. Along with testbench module, necessary design modules needed generate traffic hst_mdl.v (for ATUSBTESTSS7400), modules related ATUSBFUNC-SS7211, xvr.v (for transceiver) app_mdl.v (for application model). generate traffic, ATUSBTESTSS7400 requires command file hst_cmds, which explained detail next section. hst_cmds file user-friendly, customizable traffic generator. This file translated into format that understood hst_mdl using executable script called hst_mdl. This script, when hst_cmds file, generates intermediate files that compliant with requirements host model. hst_mdl also flags format errors hst_cmds file. sample application model being used generate traffic communicate with device core, test directory needs have three files data transfers from device host. ep0_data file that contains data transfers from application host; ep1_data contains data transfers from application host; ep2_data contains data transfers from application host. format these files explained section Application Model. application model requires another file, app_cmds, which used application model generate response interrupts stall different device endpoints. Once preceding files available, user ready simulate device core using ATUSBTEST-SS7400.
Running Simulations
executable hst_mdl hst_cmds file generate intermediate files required host model monitor model. Compile device core-related modules, application model, host model transceivers. specific amount time until host model reaches hst_cmds file. host model designed automatically exit upon completion last executable command hst_cmds file.
Logs Reports Pre-simulation Logs
hst_cmd.out When hst_mdl executed hst_cmds file, file named hst_cmd.out generated. This generates possible errors hst_cmds files. such logs are: Include file found Data files found Incorrect number bytes transfer user defines data that does byte boundary) Incorrect data format (such character through data) Number commands found hst_cmds files. (User check commands intended were processed.)
ATUSBTEST-SS7400
ATUSBTEST-SS7400
Post-simulation Logs
Host Side ep0_rcvd_app This file stores data received line endpoint from device. also specifies transaction number which data received. ep1_rcvd_app This file stores data received line endpoint from device. also specifies transaction number which data received. ep2_rcvd_app This file stores data received line endpoint from device. also specifies transaction number which data received. hst_log This file logs data transmitted/received line with summary errors, recommendation every transaction. also specifies transaction number which data received. This explained detail section monitor reports. Device Side ep0_rcvd_host This file logs data received line endpoint from host setup, data portion control transfer. ep3_rcvd_host This file stores data received line endpoint from host. app_log This file stores interrupts received, action performed, count value interrupt status register value complete simulation. Correctness Protocol This checked looking ***ERROR hst_log. This tells user whether performed protocol violation such transmitting incorrect CRC, invalid handshake, etc. user also recommended check ***WARNING user unintentionally introduced errors hst_cmds file such illegal packet sizes, incorrect addresses, incorrect endpoints, etc. Correctness Data This checked comparing data transferred from application data received host, vice versa. Atmel provides simple script process received transmitted data simulation. This script tailor-made specific applications, primarily variable data formats. Check with your Atmel Support Engineer details this script.
Installing Design
Install complete design common place. following commands root. Later releases will installed this directory.
PROMPT> /installation_dir/ PROMPT> unzip ss7211.zip
Running Simulation
Compile Verilog files (SS7211/core) directory SS7211/SS7400/ Compile Verilog files (SS7211/SS7400) directory SS7211/SS7400/ compile_mti file script compilation Model Tech environment. simulator batch file run??.bat environment SS7211/SS7400/ run_mti <Test Case No.> UNIX environment SS7211/SS7400 batch file: Compiles host commands files pattern Verilog; Runs Verilog simulation; Scans simulation reports simulation status.
Verification Correctness
Correctness simulation checked phases: Correctness protocol Correctness data
Installation Directory Structure
CORE Verilog Files Core
TEST1 TEST SS7211 TEST12
Command Data Files
Command Data Files
SS7211 Document SS7400 Document Test Environment Document
SS7400
Host model file, ram_data, batch files host, application, xvr, models testbench
SCRIPTS
SYNTHESIS SCRIPTS
run_mti (script test cases) compile_mti (compile script Model Tech tool) TEST1 RSLT TEST12 hst_log monitor. hst_log monitor.log
Host Model
host functional model simple, user-friendly, configurable comprehensive command file interface. Based commands initiated user, host model generates bit-stuffed, NRZI data line. also maintains necessary frequency signaling based full-speed low-speed signaling. generates CRC5 token CRC16 data. generates SYNC pattern, maintain packet integrity. Through command line interface, user generate error conditions that help checking correctness design protocol integrity device under test. receiver mode, host model detects SYNC pattern, EOP. performs NRZI encode unstuffing checks correctness CRC. host model also capable detecting time-out conditions, ACK, STALL conditions. host model also capable performing retry NAKed packet. host model generates necessary packets such SETUP, OUT, from command file, which described detail following sections.
Command File
host functional model uses file named hst_cmds generate necessary traffic line. This file generated user/designer based format described next section. This file needs available current directory where simulation run.
ATUSBTEST-SS7400
ATUSBTEST-SS7400
Appendix Functional Block Diagrams Host Model
Name oe_n clk_4x suspend fsen line_rcv Direction Output Output Output Input Input Input Output Input Input Input Input Comments Goes transceiver generate differential signal line Goes transceiver generate differential signal line Enables transceiver transmitter Used from device detect suspend monitor Indicates current speed transfer Indicates from device whether current transfer isochronous Digital data corresponding differential data line (from transceiver) Digital data corresponding differential data line (from transceiver) Data received from line (from transceiver)
Host Model
oe_n clk_4x suspend fsen line_rcv
Transceiver Model
Name fsen oe_n Note: Direction Input Input Input Input Output Output Output Comments Determines signaling from transceiver. This generated host model. Data from host model generate differential data line Data from host model generate differential data line Generated host model enable transmitter Generated transceiver indicate idle, line status Generated transceiver indicate idle, line status Generated transceiver receive mode indicate received data from line
This table shows pinout transceiver model used building testbench.
Transceiver Model
fsen oe_n
ATUSBTEST-SS7400
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Test Environment ATUSBTESTSS7400 Summary Overview ATUSBTEST-

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