Block Diagram Function Core High-speed, Mbps Block XCVR

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Block Diagram Function Core High-speed, Mbps Block XCVR

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1.1-compliant Approximately 6.5K Gates Supports Mbps Transfers Only Functionally Compatible with Open UHCI Modular Design Ease Integration Supports Control, Interrupt, Bulk Isochronous Transfers Four Configurable Endpoints Complete Error Handling Capability Automatic Data Retry Hardware Flexible Application Interface Supports Power Management
Block Diagram
Function Core High-speed, Mbps
Block
XCVR Clk_4x Engine Application Interface
ATUSBFUNCSS7211 Summary
Application
Overview
ATUSBFUNC-SS7211 fully synthesizable core that implemented Atmel ASIC library (gate array standard cell). core supported comprehensive test environment (ATUSBTEST-SS7400) that used verify entire design, including application. Function Core used high-speed Mbps) application, such printer, camera scanner. core configured before synthesis respond standard hub/host commands. four endpoints supported. interface application consists application interface FIFO interface. There user programmable registers this core. internal state machine control logic decode hub/host commands control data transfers across FIFO interface. Control signals used transfer error status information from application.
Rev. 1668AS-07/01
Note: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
Description
There four major blocks Function Core: Serial Interface Engine (SIE), Engine, Application Interface Block.
Application Interface
Application Interface provides simple mechanism interface user logic. This interface allows direct access endpoint FIFOs except control endpoint EP0. This block generates signals other endpoint transfers provides access their respective FIFOs. example, bulk transfer done setting, clearing stall conditions controlled application. EP1, endpoints controlled independently. This allows simultaneous access these endpoints.
interfaces with standard transceiver line side. DPLL used extract clock from received data stream. converts received serial data stream into parallel bytes delivers Engine. transmit mode, converts parallel bytes from Engine into serial data stream sends over transceiver. part protocol, performs sync detect, stuffing/unstuffing, decode, NRZI encoding/decoding, checking/generation token data packets. also monitors line detect reset, Packet (EOP), Start Packet (SOP) idle condition. transmit mode, generates SOP, Resume signaling. keeps track byte boundaries.
Block
transfers endpoint (control transfers) handled this block. commands decoded either memory (external RAM) registers accessed. Standard-, class- vendor-specific commands decoded, simple provided access registers. interface this block accesses configuration data.
Engine
Engine keeps track transaction from EOP. SOP, checks validity address endpoint initiates appropriate data transaction based status endpoint FIFOs. handles data retry mechanism, using data toggling, generates appropriate handshakes.
ATUSBFUNC-SS7211
ATUSBFUNC-SS7211
Pinout
scan ap_reset ep0_zlen_dpkt_rcvd ep0_zlen_dpkt_sent ep1_rrdy ep1_rdata ep1_raddr ep1_wrdy ep1_wdata ep1_waddr valid_ep1_bytes ep2_rdy valid_ep2_bytes ep2_raddr ep2_rdata ep3_rdy ep3_wdata ep3_waddr remote_wakeup ep0_app_stall clr_ep0_stall ep1_app_stall clr_ep1_stall ep2_app_stall clr_ep2_stall ep3_app_stall clr_ep3_stall ep1_rd ep1_wr ep2_rd ep3_wr update_ep1_rptr rewind_ep1_rptr update_ep1_wptr rewind_ep1_wptr update_ep2_ptr ep2_transfer rewind_ep2_ptr update_ep3_ptr rewind_ep3_ptr ep3_transfer usb_reset usb_clk ram_rd ram_wr ram_data_in ram_data_out ram_addr reg_data_in reg_addr reg_data_out word_mode reg_rd reg_wr suspend Frame_reg usb_intfcreg_app wr_usb_intfcreg ep1_zlen_dpkt_rcvd ep3_zlen_dpkt_rcvd
clk_4x oe_n
ATUSBFUNC-SS7211
Transceiver Signals
This signal along with used identify signaling bus. (See Note
Application Signals
scan scan signal used select between application full scan mode. Logic selects scan mode logic selects application mode. scan mode, signal ap_reset global reset. scan mode, signal logi implemented rx_signaling.v file. signal usb_reset used reset other modules.
This signal along with used identify signaling bus. (See Note
Receive data. receive data from upstream port seen this pin.
ap_reset usb_reset usb_reset_i
This signal along with used represent logic logic "0". (See Note
This signal along with used represent logic logic "0". (See Note oe_n
scan
Asserted when transceiver transmit mode.
scan mode, signal clk_4x global clock. scan mode, signal clk_4x connected clk. This logic implemented dpll.v file. signal used clock other modules. usb_clock ap_clk same.
Note Decode
Signaling Full Speed Speed Error
scan c_upcounter[1] clk_4x usbclk
Note Decode
Signaling Logic Logic Illegal
clk_4x
clock used DPLL extract clock from receive data stream. This clock full-speed, 12-Mbps transfer. ap_reset
Application reset. application-specific logic reset when this signal asserted.
ATUSBFUNC-SS7211
ATUSBFUNC-SS7211
ep0_zlen_dpkt_rcvd value valid_ep1_bytes eight. value valid_ep1_bytes greater than eight, fifo_ctl block treats valid number bytes eight only. valid number bytes zero, ap_interface sends zero length data packet host. valid_ep2_bytes[10:0]
This signal gives status zero-length data packet received application. ep0_zlen_dpkt_sent
This signal gives status zero-length data packet sent application. ep1_zlen_dpkt_rcvd
This signal gives status zero-length data packet received application. ep3_zlen_dpkt_rcvd
This signal gives status zero-length data packet received application. ep1_rrdy
When asserted, endpoint (FIFO) been filled with application data. data will provided host during next host-in transfer EP1. ep1_wrdy
endpoint valid number bytes bus. This gives number valid bytes FIFO, well valid number bytes that read from FIFO. maximum value valid_ep2_bytes bulk mode isochronous mode 1024. value valid_ep2_bytes greater than bulk mode, fifo_ctl block treats valid number bytes only. value valid_ep2_bytes greater than 1024 isochronous mode, fifo_ctl block treats valid number bytes 1024 only. valid number bytes zero, ap_interface sends zero length data packet host. mode specified with signal usbintfc_reg[0]. ep2_rdata[7:0]
Assertion this signal indicates endpoint available host data. data from previous host-out transfer been successfully consumed. ep2_rdy
endpoint read data bus. When ep2_rd signal asserted, FIFO read using this bus. endpoint addressed ep2_raddr[5:0]. remote_wakeup
When asserted, endpoint (FIFO) been filled with application data. data will provided host during next host-in transfer EP2. ep3_rdy
application asserts this signal wake device from suspend mode. When detects idle more than suspend signal asserted. application, which remote wake-up capability, asserts this signal; otherwise, deasserted. ep0_app_stall
Assertion this signal indicates endpoint available host data. data from previous host-out transfer been successfully consumed. ep1_rdata[7:0]
When asserted, application stalls endpoint transactions. host transfers this endpoint will returned with STALL. This condition needs host intervention. CLEAR STALL command clears stall condition. clr_ep0_stall
endpoint read data bus. When ep1_rd signal asserted, FIFO read using this bus. endpoint addressed ep1_raddr[2:0]. ep1_wdata[7:0]
When host issues CLEAR STALL command EP0, application clears endpoint stall asserting this signal. ep1_app_stall
endpoint write data bus. When ep1_wr signal asserted, FIFO written using this bus. endpoint addressed ep1_waddr[2:0]. valid_ep1_bytes[3:0]
endpoint valid number bytes bus. This gives valid number bytes FIFO. maximum
When asserted, application stalls endpoint transactions. host transfers this endpoint will returned with STALL. This condition needs host intervention. CLEAR STALL command clears stall condition.
clr_ep1_stall
When host issues CLEAR STALL command EP1, application clears endpoint stall asserting this signal. ep2_app_stall
configuration interface stored application registers. register address read strobe generated application Function Core; application will provide data same cycle. usb_reset
When asserted, application stalls endpoint transactions. host transfers this endpoint will returned with STALL. This condition needs host intervention. CLEAR STALL command clears stall condition. clr_ep2_stall
Asserted when reset signaling detected line. Deasserted when reset signaling complete. ep3_wdata[7:0]
When host issues CLEAR STALL command EP2, application clears endpoint stall condition asserting this signal. ep3_app_stall
Endpoint write data bus. Host data endpoint written from this bus. ep3_rd, Function Core will load data FIFO. FIFO addressed ep3_waddr[5:0]. reg_addr[7:0]
When asserted, application stalls endpoint transactions. host transfers this endpoint will returned with STALL. This condition needs host intervention. CLEAR STALL command will clear stall condition. clr_ep3_stall
Register address. This addresses application registers. example, status, configuration interface registers application register address space addressed. reg_data_out[15:0]
When host issues CLEAR STALL command EP3, application clears endpoint stall asserting this signal. ep1_rd
Register data out. control transfer, block application will result either EPROM access DESCRIPTORS application register accesses. Reg_data_out contains data command, reg_addr corresponding address this data. word_mode asserted, bits contain valid information; otherwise, [7:0] valid. word_mode
Endpoint read strobe. When asserted, data from ep1_rdata[7:0] sent host. endpoint addressed ep1_raddr[2:0]. ep1_wr
Endpoint write strobe. When asserted, data written FIFO using ep1_wdata[7:0] bus. endpoint addressed ep1_waddr[5:0]. ep2_rd
this mode, data written bits wide. When Function Core writes registers application, write 16-bit mode 8-bit mode. 16-bit mode, this signal asserted. During 8-bit mode, this signal deasserted, reg_data_out[7:0] used write data. reg_rd
Endpoint read strobe. data from ep2_rdata [7:0] sent host when this signal asserted. endpoint addressed ep2_raddr[5:0]. ep3_wr
Register read strobe. This signal asserted during register read operations. reg_wr
Register write strobe. Asserted during register write operations. suspend
Endpoint write strobe. When asserted, data written FIFO using ep3_wdata[7:0] bus. endpoint addressed ep3_waddr[5:0]. reg_data_in[7:0]
Asserted when detects idle line more than Deasserted when line active when device wants send resume transfers.
Register data bus. application-specific registers read using this bus. Information like endpoint status,
ATUSBFUNC-SS7211
ATUSBFUNC-SS7211
ep1_raddr[2:0] cycle. This signal issued before checking data that data packet. rewind_ep2_ptr
During endpoint read access, FIFO addressed using this bus. ep1_rd strobe asserted when data from location address ep1_raddr [2:0] sent host ep1_rdata[7:0]. ep1_waddr[2:0]
Endpoint addressed using this during write access. ep1_wr strobe asserted when data from ep1_wdata[7:0] written into location addressed this bus. ep2_raddr[9:0]
host-in transfer endpoint sends data from FIFO host. host does send ack, this signal asserted indicate that application data been successfully sent host. update_ep3_ptr
Endpoint addressed using this during access. ep2_rd strobe asserted when data from location address ep2_raddr[9:0] sent host ep2_rdata[7:0]. bulk mode, ep2_raddr should greater than address depth). ep3_waddr[9:0]
host-out transfer endpoint fills FIFO. Upon successfully receiving data from host, this signal asserted indicate that application host data. rewind_ep3_ptr
host-out transfer endpoint fills FIFO. receive data from host error, this signal asserted indicate application ignore data. ep3_transfer
Endpoint addressed using this during access. ep3_wr strobe asserted when data from ep3_wdata[7:0] written into location addressed this bus. bulk mode, ep3_waddr between update_ep1_ptr
host-in transfer endpoint sends data from FIFO host. Upon receiving from host, this signal asserted indicate that previous interrupt data been successfully sent host. rewind_ep1_ptr
This signal asserted before data transfer takes place. This indication data transfer. This signal generated after verification token PID, check token. token belongs endpoint error, this signal generated clock cycle. This signal issued before checking data that data packet. frame_reg [10:0]
This 11-bit frame register bus. usb_clk
host-in transfer endpoint sends data from FIFO host. host does send ack, this signal asserted indicate that previous interrupt data been successfully sent host. update_ep2_ptr
This extracted clock. usb_intfcreg_app[1.0]
host-in transfer endpoint sends data from FIFO host. Upon receiving from host, this signal asserted indicate that application data been successfully sent host. ep2_transfer
When wr_usb_intfcreg asserted, usb_intfcreg (this signal core) gets value usb_intfcreg_app.The usb_intfcreg bits mode bits EP2, EP3. zero, corresponding endpoint usb_intfcreg_app[0] endpoint (BULK usb_intfcreg_app[1] endpoint (BULK OUT). reset, bulk mode. wr_usb_intfcreg
This signal asserted before data transfer takes place. This indication data transfer. This signal generated after verification token PID, check token. token belongs endpoint error, then this signal generated clock
wr_usb_intfcreg strobe. When asserted, usb_intfcreg_app sent usb_intfcreg, which decides mode endpoint EP2, EP3.
Memory Interface
ram_wr ram_data_out[7:0] Memory write strobe. When this signal asserted, external write cycle. ram_rd During write cycle, data memory written from this bus. ram_addr[7:0]
Memory read strobe. When this signal asserted, external read cycle. ram_data_in[7:0]
external addressed using this bus.
During read cycle, data from memory read from this bus.
ATUSBFUNC-SS7211
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1668AS-07/01
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Block Diagram Function Core High-speed, Mbps Block XCVR

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