Semiconductor Products Inc. AN930 HIGH VOLTAGE, HIGH CURRENT
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Semiconductor Products Inc.
AN930
HIGH VOLTAGE, HIGH CURRENT, NONDESTRUCTIVE Pshaenich TESTING FBSOA
This Application Note provides specifications form test instrumeAt whichcan used perform non-destructive testing Second Breakdown (S.B.) limits Forward Bias Safe Operating Area (FBSOA)curve. addition, this note Illustrates typical portions FBSOA temperature derating curves forvarious technologies.
INTRODUCTION prime concern both users suppliers power transistors verification second breakdown capabilityof devices. Second breakdown energy limitation manifest itselfunder operating conditions: activeregion safe operating area, commonly referred Forward Bias Safe Operating Area (FBSOA); Reverse Bias Safe Operating Area (RBSOA). FBSOA defined turn-on conditionswhere base flows, forward biased forward base current, other when base open circuited. RESQA, hand, occurs when reverse base current, 152, flows during device turn-off. either condition, second breakdown (S.B.)is resultofcurrent crowdingin emitterfinger direction lateral field base. field causes current crowding periphery emitter during forward biasand center oftheemitterduring reverse bias. This greater current density produces spot which eventually causes transistor into second breakdown. Ifthe energy quickly removed, device will destroyed. NOTE: mechanism theory ofS.B. been under inveetigationainceasearlyas 1958. Rather thanto brieflytryto review complex phenomena, reader refer references listed this paper. This paper will address non-destruct testing FBSOA. Since conventional methods measuring S.B. limits FBSOA curve (Figure invariably result device failures, generation complete family ofcurves through destructive testingis costlyand time consuming. Generally, transistor under test (TUT) measured S.B. capability common base configuration (Figure allowing easily adjustable repeatable collectorcurrent, collector-emitter voltage pulse width measurements. determine capability ofthe transistor, either voltage current particular pulse width increased until device fails. Severaltransistors aretested inthis manner failed points recorded. number ofdevices tested each condition isdictated bythe degree ofclustering offailedparts; unusual many five devices tested each point S.B. curve determine guaranteed energy level. (The specification often listed
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VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) FIGURE Typical FBSOA Curve
P~-r1-VEE
FIGURE Simplified Common-Base Test Circuitfor Measuring FBSOA Second Breakdown
transistor data sheet which defines guaranteed point FBSOA curve.) single pulse width S.B. limitation curve, perhaps four different power levels tested. complete family curves could thus require destructive testing many transistors.
MOTOROLA INC.
FIGURE 3-Block Diagram Non-Destruct Forward Bias Second Breakdown Tester
further complicate picture, temperature effects ofS.B. investigated, even more devicesmust tested. non-destruct FBSOA tester used, then conceivably only transistor perhaps several fails degraded) used generate complete family curves. This Application Note discusses design operation Non-Destruct FBSOA Tester power transistors. addition, this Note illustrates typical S.B. portions FBSOA temperature derating curves various technologies. NON-DESTRUCT TESTERS non-destruct tester, FBSOA RBSOA, requires energy limitation detection circuit that will measure onset S.B. very rapidly remove this energy from TUTbefore overstressed. Some commercialtesters detect collapsing collector-emitter voltage when S.B. occurs measured positive going emitter voltage transistor connected common base configuration. Another non-destruct tester, developed Sherwin Rubin David Blackburn thermal instability National Bureau Standards1, measures onset monitoring base-emitter voltage waveform anomalies. When stable spot starts develop, baseemitter voltage will suddenly decrease slightly negative temperature coefficient junction. stable spot condition occurs some power transistors somewhat lower energy level than that ofsecond breakdown. increasing sensitivity detector monitoring base-emitter voltage, stable spot detected power removed from device before failure degradation occurs. Motorola non-destruct FBSOA fixture uses base-emitter voltage monitoring method with addi-
tion over-voltage over-current sensing circuitry. Empirical tests this non-destruct FBSOA fixture reveal that reducing detectors sensitivity small signal indicating stable spot ignored, larger signal second breakdown detected. `lbst measurements were verified opening detector lcop ultimately causing fail same energy level when lcop intact. These secondbreakdown test results also correlated very well with tests performed commercial tester.
NON-DESTRUCT SECOND BREAKDOWN TESTER CIRCUIT OPERATION block diagram Non-Destruct Forward Bias Second Breakdown Thsteris shown Figure shown simplified schematic Figure connected common base configurationwith both supplies switchable, allowing variable pulse widths applied transistor. other main blocks Operational Differentiator, connected emitter detecting anomalies; Noise Gate locking switching transients; Crowbar circuit rapidly removing collectorsupply from when second breakdown detected; internal Pulse Generator, designed with CMOS IC's. Other secondary circuits are: Over-CurrentDetector; Pbsitive Detector; Greater than Duty Cycle Lockout; Sample Hold Readout circuits. With exception ofthe supplies, system self contained capability subjecting with much Pulse widths variable from about either free running lesa than duty cyclesor single pulsed shot). complete schematic shown Figure
PULSE GENERATOR pulse generator designed with CMOS MC14001, quad 2-input gates, using variable frequency means potentiometer astable multivibrator (MV) clocking monoetable variable Pulse Width CR2) (U2A U2B). T~,vo other MV's associated with pulse generator Noise Gate (U3A U3B) Sample Delay (U2C U2D). Additionally, Noise Gate, consisting gates U3C, U3D, U2C, completes total gate complement three I.C.'s. free operation, switch position shown, allowing astable clock three monostable MV's. Single pulse operation obtained throwing 1-Shot position depressing pushbutton start switch, Note that these I.C.'s powered with internally packaged, power supply. Thus, output Pulse Width (gate U2B) positive going pulse referenced
form compound configuration requiring only about base drive supply emitter current from Qil. Like clamp Emitter Switch, clamps when second breakdown detected.
OPERATIONAL DIFFERENTL4IOR
operational differentiator most unique important circuit inthe system. monitors emitter-base voltage, detecting rapid change waveform, shown Figure reality, measures plus forward voltage drop reverse base current blocking diode base TUT). Pulse Generator output Emitter Collector Switches (Figure allows propagation-delayed collector current flow (Figure 5B), with resultant (Figure 5C). When spot onset second breakdown starts occur, will suddenly decrease (dotted portion curve). input capacitor op-amp will differentiate this waveform (Figure SD), producing Operational Differentiator output (Figure 5E). magnitude this signal function capacitor chosen front-panel selector switch larger capacitor, greater differentiatorsensitivity Ahigh gain comparator follows this stage (with input threshold control noise immunity) setting quiescent output high.) output ofU5 will consequently that ofFigure false switching signals leading trailing edges ofthe waveform with true signal, second breakdown detected, somewhere middle. This signal then sent Noise Gate discrimination.
EM1TrER SWITCH
emitter switch, consisting cascaded transistor transistor power output transistor amplifies CMOS pulse width output current levels high minimizeinternal power supply drain, Darlington transistor emitter tied ground (base drive derived from -VEE). Thus drive transistor emitter connected necessitating CMOS gates' supply operation. Emitter currentfor iscontrolled varying external -VEE power supply and/or front panel selectable switch 54B) collector load resistors Base drive also varied accordingly with switch S4A. When second breakdown detected, trigger pulse gate clamping offQ3 thus turning emitter switch; (the Pulse Generator also turned off, will subsequently described). DUTY CYCLE LIMIT Since transistor stages direct coupled, duty cycle (D.C.) must limited about maximum prevent excessive dissipation coupling resistors (particularly ohm, base current limiting resistor Q3). This accomplishedby Darlington transistor input clamp transistor D.C. increases, charge builds integrating capacitor base circuit eventually turning Consequently, D.C. turns indicating excessive duty cycle, turns effectively limiting input pulse width. COLLECTOR SWITCH were fail shorting, external, variable, supply would excessively stressed unless this power supply could quickly removed from system. TheCollector Switch preventsthis condition this circuit switched onand offconcurrent with Emitter Switch. This series connected switch must sustain full supply (400 max, max); therefore, input must amplified level translated from CMOS Pulse Generator output level. This accomplished negative going output pulse ofgate turning order, driver constant current configured level translator driver series switch Qil. Transistors Q1O, Darlington transistor
NOISE GATE Utilizing gate logic propagationdelay Emitter Switch, Noise Gate reject respective leading trailing edge switchingsignals. NORingthe positive going Noise Gate output, Figure with inverted Pulse Width output, UlD, waveform Figure will result. When this waveform, turn, NOR'd with comparator output, result will waveform Figure 51-just signal spotting second breakdown will transmitted. This signal will amplified cascaded switching transistors supply trigger shutdown circuits.
CROWBAR addition clamp SCR's Emitter
Collector Switches being activated second breakdown trigger, Crowbar power MOSFET also turned This TMOS FET, rated and4 connected from collectorof ground. Being extremely fast switching device, will quickly divert crowbar current from when second breakdown occurs, momentarily shorting power supply delay time required open Collector Switch (about p.s). Having high pulsed current ratings, well able sustain this energy Using crowbar greatly ensures survival TUT. Another feature tester ability shut down Pulse Width once second breakdown occurs, required. This shut down accomplished being fired trigger, which turns (through series connected switches, clamp transistor, Q17. This transistor places logic (ground) nor-
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-12V
Noise Gate Output
Sample Delay
-I1V
Sample Pulse
FIGURES-Waveforms ofSB. Non-Destruct Tester
mally (-12 input gate UlD, inhibiting monostable from pulsing thus preventing further application power TUT. system (5CR Q16) reset depressing pushbutton Switch this latch condition required, Switch thrown open system free-runs, although Pulse Widths shorter than normal S.B. Now, clamp SCR'S reset after every free running pulse.
ground prevents this voltage from exceeding diode drop. This signal then measured comparator whose output will also trigger when goes positive. effect, this aredundant detector, offering secondary protection, Operational Differentiator normally triggers earlier.
SAMPLE HOLD READOUTS
last main blocks circuits collector current, collector-emitter voltage, VcE/100, readouts. Employing standard Sample Hold (S/H)circuitry, circuit samples voltage drop across supply sense resistor VcE/100 circuit measures attenuated collector-ground voltage (VcG~VcE). (For accurate power measurements, techniques required analog measurements integrate transient responses pulsed power supplies.) Both circuits driven common samplepulse, with Sample Delay (gates U2D) positioning sample pulse transistor (configured half monostable providingthe pulse width. Normally turned offby negative going, trailing edge Sample Delay pulse (Figure SJ). differentiating circuit base Q18thus dictates sample pulse width output (Figure 5K). positive going pulse (approximately jz.s wide) then turns respective series conected switches (Q19 Q20) charge hold capacitors. Unity gain connected op-amp buffers high impedance, collector voltage atten-
OVER CURRENT
ensure that output stages ofthe Emitter Collector Switches operate within their maximum current ratings, simple comparator circuit incorporated. comparator measures voltage drop across sense resistor return supply. When this total power supply current approaches comparator will switch positively thus fire clamp Q12. Consequently, Collector Switch opens, removing supply from system.
POSITiVE DETECTOR
Some commercial testers detect second breakdown monitoring positive going, above ground, voltage. Recall that common base configuration, normal pulse negative going from ground (Figure SC). When second breakdown occurs, collapsing collector-emitter voltage will force emitter positive. With Motorola tester, clamp diode from emitter
TABLE Forward Bias Second Breakdown Derating with Temperature
DEVICE 2N5301
CASE 10-3 10-3
10-3 10-3 10-3
PROCESS
BASE BASE BASE BASE BASE
APPUCATION DESIGNATION
BASE BASE BASE BASE BASE
COND~ONS
(ins)
DERATED TOAT15
W15003
SJ400S MJ15052 MJ15022
0.96 0.64 0.75
MJ11032
10-3
BASE
DARUNGION
2N6282 MJ10016
70-3
BASE
DARLINGION
H.V~ DARUNGION H.V. DEFLECTION
44)0
BU806 MJE12026
2N6488
10-3 10-220 10-220
10-220 10-220
DIFF 01FF TRIPLE DIFF.
BASE
S.M.
DARLINGTON GEN. PURPOSE
0.38 0.35
0.69 0.65 0.56 0.47
MJE1503
10-220
DIFF PLANAR
AUDIODRIVER
uating resistors op-amps Hold amplifiers. These three op-amps have inputs provide required extremely high input impedance.
POWER SUPPLIES
With exceptionofthe external, high power, variable supplies, S.B. tester completely selfcontained includes power ±12V supplies which simple, linear power suplies derived from regulators U12. These regulators easily handle pulsed current requirements system's level circuitry (about max).
detected points five devices. results quite linear, with five devices derated down about from 250C reading. tosimilar manner, temperature data taken several other transistors; test results shown Table average, TUT's were derated about 60%, varying from high about 50%. This admittedly limited test program (only three typical transistors each type were tested) showed that S.B. transistors some cases second order function and/or pulse width. conditions listed table describe these variables.
SECOND BREAKDOWN TESF RESUI2TS Second Breakdown `Thmperature Derating
FBSOA curves similar Figure commonly shown power transistor data sheets generally defined given case temperature junction temperature ambient temperature What usually shown second breakdown temperature derating curves specifications. non-destruct S.B. tester simplifies generation second breakdown temperature derating curve since only device few, degraded with testing) need tested with variable temperatures, voltages and/or pulse widths. number Motorola power transistors coveringvarious processes applications, TO-3 TO-220 cases were S.B. tested. major interest behavior these TUT's with increasing case temperature. simple method varying transistor case temperature elevate heat sink temperature with power resistors. Then, S.B. measured case temperature. Figures through describe actual S.B.
Second Breakdown Versus Pulse Width
Also interest behavior S.B. versus pulse width familiar FBSOA curves. Accurate results obtained because curves generated from device. TYpical examples illustrated curves Figures through These curves should compared with plot offailed devicesderived from destructive testing, shown Figure (The intermixing points variouspulse tests complicates drawingofthe final, derated curve). variation second breakdown with large pulse widths shown Table several devices. This data importance particularly when trying correlate results from different testers; example, some equipment might pulse test second another test ins. regard correlation testing, results comparing commercial tester (TES Corporation [Tanaka] 7622TS Tester 7623-PU Power Unit) with nondestruct tester were excellent. Twelve BU807 devices were tested both machines ins;
FIGURE Forward Bias Secend Breakdewn Temperature Derating
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15030 -4-~5
O.47A(a'25C
Vca=70V
kE.5A(w
zL.50
Tc.CASE TEMPERATURE
Tc,CASE TEMPERATURE
17500
FIGURE MJE15O3O 10O-~
FIGURE 68-MJ11032
TIP121
MJE12026 0.35
Vc~=60V
Ic=0.69A( SOms
Tc.CASE TEMPERATURE
FIGURE MJE12026
Tc.CASE TEMPERATURE (0C) FIGURE 11P121
itation primarily response time switched power supplies. ringing transients switched leading edge reflect detector error signal. Consequently, time this transient damp must blanked from detector.
Motorola tester, Noise Gate provides blanking period. Empirical testing determined that minimum blanking time required power supplies used should about ~i.s testing with narrow pulses.
Larger pulse widths longer blanking periods.
front-panel switch, 57B, allows selection ofeither blanking time. Sections this switch (57A 57C) ganged Pulse Width Sample Delay change their time accordingly. second condition that limits non-destruct pulse width time constant differentiating circuit input Operational Differentiator. This network must completely recover time frame involved. Consequently, narrow pulse widths, smallest capacitor must used, still must provide enough sensitivity fire shutdown circuits. second breakdown protection, 0.01 capacitor wassatisfactory pulse widths down Sins; pulses, 0.0033 capacitor usually suffices protects TUT. Thsting with pulses narrower than generally reliable. This tester originally designed detect stable spots power transistors, thus required greater dif-
1./s Tc.CASE TEMPERATURE FIGURE 2N6488
differences S.B. were most average). Similar results were obtained when comparingthe MJE15030 ins. Tester, however, costs about $20,000 only (200 capability. testers, including Motorola unit described this paper, have limited minimum pulse width non-destruct capability. lim-
FIGURE 7-Active Region Safe Operating Area (FBSOA) Curves Derived with Non-Destruct Tester
~s.o
Sins ~Oms(~ 2110 -~-~
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3.1-
2N6259
250.
DUTY C~LE
COLLECTOREMfl7ER VOLTAGE (VOLTS) FIGURE BUSOS
COLLECIOR-EMITrER VOLTA3E (VOLTS) FIGURE 2N6259
SOins
urns
200ms
2N5301
DUTY C'vVLE Vcs. COLLECIDR-EMmFER VOLTA~3E (VOLTS)
Vcs. COLLECTOR-EMITTER VOOA~3E (VOLTS)
FiGURE MJE15O3O
FIGURE 2N5301
~Lii
urns
TABLE Effect Pulse Width Forward Bias Second Breakdown Normalized Versus Pulse Device SOms 200ms Width (Amps)
2N5301 MJ1SOO3 2N6259 MJ15052 0.85 0.74 0.43 0.69 0.47 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
SinsSOms
200rns
DUlY !~tLE.
140150 COLLECTOR-EMITTER VOLTAGE (VOLTS)
MJ11032 2N6282 MJ1001S BU8OS
FIGURE 7E-MJ15003
ferentiator sensitivity (0.1 0.47 J.LF). Therefore, locus stable spot curve generally falls within measured second breakdown curve those transistors that exhibit this phenomenon. (The published S.B. curve should adequately derated include spotting.)This illustrated curves Figure data Table
MJE12O2S TlP121 2N6488 MJE15O3
100%
TABLE 3-Difference Collector Current Between Second Breakdown Spot
DEVICE
WIDTH PULSE (gUS)
BRKDWN@ SPOT 0.85
0.39 0.47
MJ10016
MJE12026 MJE15030 2N6282
0.51
0.12 0.27
5070100
VcE, COLLECTOR-EMfli~ER VOLTAGE (VOLTS)
FIGURES Derivation MJ15022 FBSOA Curves
lastly, purpose non-destruct tester test devices without degradation (which generally shows increase leakage current). meaningful change leakage current `cso noted several devices measured before after number S.B. stresses.
REFERENCES
Rubin D.L. Blackburn, Test Unit Non-Destructive Determination Forward-Biased Safe Operating Area Limits Power Transistors, Annual, 666-673. D.L. Blackburn, Safe Operating Area Limits Power Transistors, Special Publications 400-44, U.S. Department Commerce, National Bureau Standards. Hower, Stable Spots Second Breakdown Power Transistors, PESC Record, 234-246. M.E. Snyder, Physics ofSecond Breakdown, Force Weapons Laboratory Final Report AFWL-TR-83-22. Roehr, Avoiding Second Breakdown, Motorola Application Note AN415A. Schultz, Power Transistor Safe Operating Area Special Considerations Motor Drives, Motorola Applications Note AN861. Pshaenich, Effects ofBase Drive Conditions RBSOA, Motorola Applications Note AN828.
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FIGURE 9-Comparison FBSOA Second Breakdown Versus Stable Spot forthe MJEt5O3
wwVfratn ~ns,nwvl, h~in Motorola makes nowarranty, representation orguaranteeregan~ng suit~iHty ofits products particularpurpose, does Motorola assume liablay arising outof application prochjct circuit, andspecifically disdains anyand liability, includingwithout imitation consequential orincidertaldamages. "Typical"parameters vary different applications. operating parameters, including`Typicair must validated each customer application customer's technical experts. Motorola does convey license under patent rights north. rIghts others. Motorola products notdesigned, intended, authorizedfor components systems intended Surgical implant into body, other applications intended supportor sustain lila, other application which failureof Motorola product could create situation where personal kitzy death occur. Should Buyer purchase Motorola products such unintendedor unauthorizedapplication, Buyershall indemnifyand hold Motorola officers, employees, subsidiaries, affiliates, distributorsharmless against claims, costs, damages, expenses, reasonatile attorney fees arising dIrectly indirectly, claim personal injury death associatedwith such unintendedor unauthorized use, evenI such claimalleges that Motorola negigent regarding thedesign manufacture ofthe part. Motorolaand registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirrnallve Action Employer.
Motorolareservesthe riohtto makechanneswlthniitfr
Uteuuture Dlstilbutlon Centers: USA: Motorola Uterature Distribution; 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Uterature Centre; Tanners Drive, Blakelands, Milton Keynes. MKl4 England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semioonckictors Lt&; Silicon Harbour Center, No.2 King Street~ Industrial Estate, N.T., Hong Kong.
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UPS/POD
AN930/D
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