PCnetTM-SCSI Combination Ethernet SCSI Controller Systems DISTINC
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Am79C974
PCnetTM-SCSI Combination Ethernet SCSI Controller Systems
DISTINCTIVE CHARACTERISTICS Features
Direct glueless interface MHz, 32-bit local Mbyte/s burst transfer rate Compliant local Specification Revision
Advanced Micro Devices
SCSI Features
Compliant ANSI standards X3.131 1986 (SCSI-1) X3.131 199X (SCSI-2) Fast 8-bit SCSI-2 Mbyte/s synchronous Mbyte/s asynchronous data transfer rate SCSI specific Mastering engine (32-bit address/data) 96-byte FIFO latency On-chip state machine control SCSI sequences hardware Integrated industry standard Fast SCSI-2 core Single-Ended outputs drive SCSI directly Support Scatter-Gather data transfers Hooks silicon software enable disk drive spin down power savings
Ethernet Features
Supports 8802-3 (IEEE/ANSI 802.3) Ethernet Standards High-performance Master architecture with integrated Buffer Management Unit utilization Individual 136-byte transmit 128-byte receive FIFOs provide frame buffering increased system latency MicrowireEEPROM interface supports jumperless design Integrated Manchester Encoder/Decoder Provides integrated Attachment Unit Interface (AUI) 10BASE-T transceiver with automatic port selection Automatic Twisted-Pair receive polarity detection automatic correction receive polarity Dynamic transmit generation programmable frame-by-frame basis Internal/external loopback capabilities Supports following types network interfaces: external 10BASE2, 10BASE5, 10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch Twisted-Pair medium
General Features
Software compatible with AMD's Am79C960 PCnet-ISA, Am79C961 PCnet-ISA+, Am79C965 PCnet-32, Am79C970 PCnet-PCI register descriptor architecture Plug-in software compatible with AMD's PCSCSI family SCSI controllers NAND Tree test mode connectivity testing printed circuit boards Single power supply operation Low-power, CMOS design with sleep modes both Ethernet SCSI controllers allows reduced power consumption critical battery powered applications `Green PCs' Fully static design frequency power operation 132-pin PQFP package
GENERAL DESCRIPTION
PCnet-SCSI combination Ethernet 8-bit Fast SCSI controller with 32-bit interface highly integrated Ethernet-Fast SCSI system solution designed address high-performance system application requirements. This single-chip flexible bus-mastering device that used many applications, including network- SCSI-ready PCs, printers, modems, bridge/router designs. bus-master architecture provides high data throughput system system utilization. PCnet-SCSI controller fabricated with AMD's advanced low-power CMOS process provide operating standby current power sensitive applications.
Publication# 18681 Rev. Issue Date: October 1994 Amendment
This document contains information product under development Advanced Micro Devices, Inc. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
PRELIMINARY overhead, providing sufficient latency during frame transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder (MENDEC) eliminates need external Serial Interface Adapter (SIA) system. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity jabber status.
PCnet-SCSI part AMD's product family plug-in software compatible SCSI Ethernet controllers. This product compatibility ensures cost system upgrade path lower motherboard manufacturing costs.
Ethernet Specific
PCnet-SCSI controller includes complete Ethernet node integrated into single VLSI device. contains interface unit, buffer management unit, IEEE 802.3-defined Media Access Control (MAC) function, individual 136-byte transmit 128-byte receive FIFOs, IEEE 802.3-defined Attachment Unit Interface (AUI) Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), Microwire EEPROM interface. PCnet-SCSI controller also register compatible with LANCE (Am7990) Ethernet controller, C-LANCE (Am79C90) Ethernet controller, ILACC (Am79C900) Ethernet controller, Ethernet controllers PCnet Family, including PCnetISA controller (Am79C960), PCnet-ISA+ controller (Am79C961), PCnet-32 controller (Am79C965). buffer management unit supports LANCE, ILACC, PCnet descriptor software models. PCnet-SCSI controller software compatible with Novell NE2100 NE1500 Ethernet adapter card architectures. addition, Sleep function been incorporated provide standby current, excellent notebooks Green PCs. 32-bit multiplexed interface unit provides direct interface local applications, simplifying design Ethernet node system. With built-in support both little endian byte alignment, this controller also addresses proprietary non-PC applications. PCnet-SCSI controller supports auto configuration configuration space. Additional PCnet-SCSI controller configuration parameters, including unique IEEE physical address, read from external non-volatile memory (serial EEPROM) immediately following system RESET. controller also capability automatically select either port Twisted-Pair transceiver. Only interface active time. individual transmit receive FIFOs optimize system
SCSI Specific
PCnet-SCSI controller also includes highperformance Fast SCSI controller with glueless interface local bus. PCnet-SCSI integrates 32-bit mastering engine with industry standard Fast SCSI-2 block. engine accompanying byte FIFO allow 32-bit burst data transfers across high bandwidth speeds Mbyte/s. Full support scatter-gather transfers optimize performance multi-tasking system applications. PCnet-SCSI's on-chip state machine controls SCSI sequences hardware coupled with mastering engine eliminate need onchip RISC processor. This results smaller size giving Am79C974 superior price/performance versus competitive offerings. supports Am79C974 with total system solution which includes: full suite licensable SCSI drivers utilities fully tested under following operating system environments: Windows Windows OS/2 Netware 3.x, UNIX 3.2.4, INT13h Compatible SCSI BIOS ASPI Compatibility Complete hardware reference design more detailed information PCnet-SCSI refer technical manual, #18738A.
Am79C974
HIGH LEVEL BLOCK DIAGRAM
SCSI Data SCSI Control 10Base-T, Ports
SCSI Sequences, SCSI Control, SCSI Registers
802.3 Core
SCSI FIFO
Registers
FIFO
FIFO Control
FIFO
FIFO Bytes
FIFO Control
Registers Control
Host Control Interface
18681A-1
Data/Address
Host Control
Am79C974
Cache SRAM
DRAM Memory
PCnet-SCSI (Am79C974)
Video Control
Control Address Data Core Logic
PC-AT
Super IDE/Floppy Ser/Par
Keyboard Control
18681A-2
Am79C974 System
Am79C974
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION HIGH LEVEL BLOCK DIAGRAM RELATED PRODUCTS CONNECTION DIAGRAM ORDERING INFORMATION DESIGNATIONS Listed Number Listed Name Quick Reference Description Listed Driver Type
LOGIC SYMBOL DESCRIPTION Interface Ethernet Controller Pins Board Interface Microwire EEPROM Interface Attachment Unit Interface Twisted-Pair Interface SCSI Controller Pins Test Interface Miscellaneous Power Supply System Interface Function Software Interface Ethernet Interfaces SCSI Interfaces
BASIC FUNCTIONS
DETAILED FUNCTIONS Interface Unit (BIU) Slave Configuration Transfers Slave Transfers Acquisition Master Transfers Target Initiated Termination Master Initiated Termination
Ethernet Controller Buffer Management Unit (BMU) Initialization Re-Initialization Buffer Management Descriptor Rings Descriptor Ring Access Mechanism Polling Transmit Descriptor Table Entry (TDTE) Receive Descriptor Table Entry (RDTE)
Am79C974
PRELIMINARY Media Access Control Transmit Receive Message Data Encapsulation Media Access Management Manchester Encoder/Decoder (MENDEC) External Crystal Characteristics External Clock Drive Characteristics MENDEC Transmit Path Transmitter Timing Operation Receiver Path Input Signal Conditioning Clock Acquisition Tracking Carrier Tracking Message Data Decoding Differential Input Terminations Collision Detection Jitter Tolerance Definition Attachment Unit Interface (AUI) Twisted-Pair Transmit Function Twisted-Pair Receive Function Link Test Function Polarity Detection Reversal Twisted-Pair Interface Status Collision Detect Function Signal Quality Error (SQE) Test (Heartbeat) Function Jabber Function Power Down 10BASE-T Interface Connection
Twisted-Pair Transceiver (T-MAU)
Ethernet Power Savings Modes Software Access Ethernet Configuration Registers Resources Register Access Hardware Access PCnet-SCSI Controller Master Accesses Slave Access Resources EEPROM Microwire Access Transmit Operation Transmit Function Programming Automatic Generation Transmit Generation Transmit Exception Conditions Receive Function Programming Automatic Stripping Receive Checking Receive Exception Conditions
Receive Operation
Loopback Operation Support
Am79C974
H_RESET, S_RESET, STOP H_RESET S_RESET STOP SCSI Controller SCSI Specific Engine FIFO Blast Command Funneling Logic SCSI Programming Sequence Based Programming Scatter-Gather Mechanism
Memory Descriptor List (MDL) Scatter-Gather Operation aligned elements) Scatter-Gather Operation (Non-4k aligned elements set) Interrupts Fast SCSI Block SCSI Block SCSI FIFO Threshold Data Transmission REQ/ACK Control Parity
Parity Checking SCSI Parity Generating SCSI Reset Levels Hard Reset: Soft Reset: Disconnected Reset: Device Commands Command Stacking Invalid Commands Command Window Initiator Commands Information Transfer Command Initiator Command Complete Steps Message Accepted Command Transfer Bytes Command Command Reset Command Select Without Steps Command Select With Steps Command Select With Stop Steps Command Enable Selection/Reselection Command Disable Selection/Reselection Command Select With ATN3 Steps Command Operation Command Clear FIFO Command Reset Device Command Reset SCSI Command Am79C974
Idle State Commands
General Commands
PRELIMINARY SCSI Power Management Features SCSI Activity Reduced Power Mode Power Down (PWDN Pin) Software Disk Spin-Down NAND Tree Testing
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES CHARACTERISTICS: Board Interface CHARACTERISTICS: Attachment Unit Interface CHARACTERISTICS: 10BASE-T Interface CHARACTERISTICS: SCSI Interface CHARACTERISTICS: Capacitance, ESD, Latch SWITCHING CHARACTERISTICS: Board Interface SWITCHING CHARACTERISTICS: 10BASE-T Interface SWITCHING CHARACTERISTICS: Attachment Unit Interface SWITCHING CHARACTERISTICS: SCSI Interface SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS SWITCHING WAVEFORMS: System Interface SWITCHING WAVEFORMS: 10BASE-T Interface SWITCHING WAVEFORMS: Attachment Unit Interface SWITCHING WAVEFORMS: SCSI Interface PHYSICAL DIMENSIONS APPENDIX Register Summary Ethernet Controller Control Status Registers -Bus Configuration Registers SCSI Controller SCSI Register Register APPENDIX PCnet-SCSI Compatible Media Interface Modules APPENDIX Recommendation Power Ground Decoupling APPENDIX Alternative Method Initialization Ethernet Controller APPENDIX SCSI System Considerations APPENDIX Designing Single Motherboard Family
Am79C974
LIST FIGURES
Figure Slave Configuration Read Figure Slave Configuration Write Figure Slave Read Figure Slave Write Figure Acquisition Figure Non-Burst Read Cycles With Wait States Figure Non-Burst Read Cycles Without Wait States Figure Non-Burst Read Cycles With Without Wait States Figure Burst Read Cycles Figure Burst Write Cycles Figure Disconnect With Data Transfer Figure Disconnect Without Data Transfer Figure Target Abort Figure Preemption When FRAME Deasserted Figure Preemption When FRAME Asserted Figure Master Abort Figure 16-Bit Data Structures: Initialization Block Descriptor Rings Figure 32-Bit Data Structures: Initialization Block Descriptor Rings Figure Receiver Block Diagram Figure Differential Input Termination Figure 10BASE-T Interface Connection Figure 8802-3 (IEEE/ANSI 802.3) Data Frame Figure 802.3 Frame Length Field Transmission Order Figure Control Logic Figure Engine SCSI Block Figure FIFO SCSI FIFO Interface Figure Am79C974 NAND Tree Test Structure Figure NAND Tree Waveform Figure SCSI Clock Input Figure Asynchronous Initiator Transmit Figure Asynchronous Initiator Receive Figure Synchronous Initiator Transmit Figure Synchronous Initiator Receive Figure E-1. Ideal Routing Scheme SCSI Figure E-2. Poor Routing Scheme SCSI Figure E-3. Motherboard Layout Approach Figure E-4. Motherboard Layout Approach Figure E-5. Decoupling Capacitor Placement Figure E-6. Regulated Termination Figure F-1. Family Connections
Am79C974
LIST TABLES
Table Crystal Specifications Table Clock Drive Characteristics Table Master Accesses Table Slave Accesses Table EEPROM Contents Table Registers Table Summary SCSI Commands Table NAND Tree Configuration
Am79C974
RELATED PRODUCTS
Part Am33C93A Am386® Am486Am53C94/96 Am53C974 Am53CF94/96 Am79C90 Am79C98 Am79C100 Am79C900 Am79C940 Am79C960 Am79C961 Am79C965 Am79C970 Am79C981 Am79C987 Am7990 Am7996 Am85C30 Description Synchronous SCSI Controller High-Performance 32-Bit Microprocessor High-Performance 32-Bit Microprocessor High-Performance SCSI Controller PCSCSIBus Mastering Fast SCSI Controller Systems Enhanced Fast SCSI-2 Controller CMOS Local Area Network Controller Ethernet (C-LANCE) Twisted-Pair Ethernet Transceiver (TPEX) Twisted-Pair Ethernet Transceiver Plus (TPEX+) Integrated Local Area Communications Controller(ILACCTM) Media Acces Controller Ethernet (MACETM) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug Play support) PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, buses) PCnet-PCI Single-Chip Ethernet Controller Local Integrated Multiport Repeater Plus(IMR+TM) Hardware Implemented Management Information Base(HIMIBTM) Local Area Network Controller Ethernet (LANCE) IEEE 802.3/Ethernet/Cheapernet Transceiver Enhanced Serial Communication Controller
Am79C974
CONNECTION DIAGRAM
AD28 AD29 VSSB AD30 AD31 REQA REQB GNTA GNTB INTB INTA RESERVE SLEEP EECS DVSS EESK/LED1 EEDI/LNKST EEDO/LED3 DVDD AVDD2 CIDI+ DIAVDD1 DOAVSS1
VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 IDSELA IDSELB AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB
Am79C974 PCnet-SCSI
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXDTXPAVDD4 RXD+ RXDDVSS VSSBS DVSS VDDBS VSSBS VSSBS
C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB PWDN SCSICLK BUSY SCSI^RST
marked orientation. RESERVE Don't Connect.
18681A-3
Am79C974
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination
AM79C974
ALTERNATE PACKAGING OPTION Trimmed Formed Tray OPTIONAL PROCESSING Blank Standard Processing TEMPERATURE RANGE Commercial (0°C +70°C)
PACKAGE TYPE (per Prod. Nomenclature) Plastic Quad Flat Pack Trimmed Formed (PQB132) SPEED OPTION Applicable
DEVICE NUMBER/DESCRIPTION Am79C974 PCnet-SCSI Combination Ethernet SCSI Controller Systems
Valid Combinations AM79C974 KC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C974
DESIGNATIONS Listed Number
Name VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 IDSELA IDSELB AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB Name C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB PWDN SCSICLK BUSY SCSI^RST Name VSSBS VSSBS VDDBS DVSS VSSBS DVDD DVSS RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DVDD EEDO/LED3 EEDI/LNKST EESK/LED1 DVSS EECS SLEEP RESERVE INTA INTB GNTB GNTA REQB REQA AD31 AD30 VSSB AD29 AD28
Am79C974
DESIGNATIONS Listed Name
Name AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BUSY C/BE0 C/BE1 C/BE2 C/BE3 DEVSEL DVDD DVDD DVSS DVSS DVSS EECS EEDI/LNKST EEDO/LED3 EESK/LED1 FRAME GNTA Name GNTB IDSELA IDSEL INTA INTB IRDY LOCK PERR PWDN REQA REQB RESERVE RXD- RXD+ SCSICLK SCSI^RST SERR SLEEP Name STOP TRDY XTAL1 XTAL2 TXD- TXD+ TXP- TXP+ VDDB VDDB VDDB VDDB VDDBS VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSBS VSSBS VSSBS
Am79C974
DESIGNATIONS Quick Reference Description
Name Interface AD[31:00] C/BE[3:0] DEVSEL FRAME GNTA, GNTB IDSELA, IDSELB INTA, INTB IRDY LOCK PERR REQA, REQB SERR STOP TRDY Board Interface EECS EEDI/LNKST EEDO/LED3 EESK/LED1 SLEEP XTAL1-2 CI+/CI- DI+/DI- DO+/DO- 10BASE-T Interface RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Receive Differential Pair Transmit Differential Pair Transmit Pre-distortion Differential Pair Link Status/Microwire Serial EEPROM Data Microwire Serial PROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire APROM Data Out/LED predriver Microwire Serial PROM Clock/LED1 Sleep Mode Crystal Input/Output Collision Differential Pair Data Differential Pair Data Differential Pair Address/Data Command/Byte Enable Clock Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Lock Parity Parity Error Request Reset System Error Stop Target Ready Description Type Driver Pins
ETHERNET SPECIFIC
Attachment Unit Interface (AUI)
Am79C974
DESIGNATIONS (continued) Quick Reference Description
Name SCSI SPECIFIC SCSI Interface [7:0] SCSI^RST Miscellaneous SCSI RESERVE Power Management PWDN Test Interface BUSY Power Supplies AVDD AVSS VDD/DVDD VSS/DVSS VDDB/VDDBS VSSB/VSSBS Analog Power Analog Ground Digital Power Digital Ground Buffer Power Buffer Ground NAND Tree Test Output Power Down Indicator SCSI Core Clock Reserved, CONNECT SCSI Data SCSI Data Parity Message Command/Data Input/Output Attention Busy Select SCSI Reset Request Acknowledge OD48 OD48 OD48 OD48 OD48 OD48 OD48 Description Type Driver Pins
Listed Driver Type
following table describes various types drivers that implemented PCnet-SCSI controller. Current given milliamperes:
Name OD48 Type Tri-State
(mA)
(mA) -2.0 -2.0 -0.4 -0.4 -0.4 -0.4
Tri-State Totem Pole Totem Pole Totem Pole Open Drain Open Drain
Am79C974
LOGIC SYMBOL
CI+/- DI+/- C/BE [3:0] XTAL1 XTAL2 FRAME TRDY IRDY EECS STOP DEVSEL Interface IDSELA [7:0] IDSELB REQA REQB GNTA GNTB INTA INTB LOCK PERR SERR PCnet-SCSI (Am79C974) SCSI^RST SCSI RESERVE Power Management Signals Test Interface SCSI EESK/LED1 EEDO/LED3 DO+/- RXD+/- TXD+/- TXP+/- EEDI/LINKST
[31:0]
Ethernet
PWDN
BUSY
18248B-4
Am79C974
DESCRIPTION Interface AD[31:00]
Address Data Input/Output, Active High These signals multiplexed same pins. During first clock transaction AD[31:00] contain physical byte address bits). During subsequent clocks AD[31:00] contain data. Byte ordering little endian default. AD[07:00] defined least significant byte AD[31:24] defined most significant byte. FIFO data transfers, PCnetSCSI controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when PCnet-SCSI controller master, AD[31:2] will address active DWORD (double-word). PCnetSCSI controller always drives AD[1:0] `00' during address phase indicating linear burst order. When PCnet-SCSI controller master, AD[31:00] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:00] driven PCnet-SCSI controller when performing master writes slave read operations. Data AD[31:00] latched PCnet-SCSI controller when performing master reads slave write operations. When active, AD[31:0] inputs NAND tree testing.
with respect this edge. PCnet-SCSI controller operates over range MHz. When active, input NAND tree testing.
DEVSEL
Device Select Input/Output, Active This signal when actively driven PCnet-SCSI controller slave device signals master device that PCnet-SCSI controller decoded address target current access. input indicates whether device been selected. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output, Active This signal driven PCnet-SCSI controller when master indicate beginning duration access. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted when transaction final data phase. When active, FRAME input NAND tree testing.
GNTA
Grant Input, Active This signal indicates that access been granted Am79C974's SCSI controller. Am79C974 controller supports parking. When idle system arbiter asserts GNTA without active REQA from Am79C974 controller, controller will actively drive AD[31:00], BE[3:0], lines. When active, GNTA input NAND tree testing.
C/BE [3:0]
Command Byte Enables Input/Output, Active These signals multiplexed same pins. During address phase transaction, C/BE[3:0] define command. During data phase C/BE[3:0] used Byte Enables. Byte Enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[07:00]) C/BE3 applies byte (AD[31:24]). function Byte Enables independent byte ordering mode (CSR3, When active, C/BE[3:0] inputs NAND tree testing.
GNTB
Grant Input, Active This signal indicates that access been granted Am79C974's Ethernet controller. Am79C974 controller supports parking. When idle system arbiter asserts GNTB without active REQB from Am79C974 controller, controller will actively drive C/BE lines.
Clock Input This signal provides timing transactions devices including PCnet-SCSI controller. signals sampled rising edge parameters defined
Am79C974
When active, GNTB input NAND tree testing.
IRDY
Initiator Ready Input/Output, Active This signal indicates PCnet-SCSI controller's ability, master device, complete current data phase transaction. IRDY used conjunction with TRDY. data phase completed clock when both IRDY TRDY asserted. During write IRDY indicates that valid data present AD[31:00]. During read IRDY indicates that data accepted PCnet-SCSI controller master. Wait states inserted until both IRDY TRDY asserted simultaneously. When active, IRDY input NAND tree testing.
IDSELA
Initialization Device Select Input, Active High This signal used SCSI controller selection Am79C974 during configuration read write transaction. When active, IDSELA input NAND tree testing.
IDSELB
Initialization Device Select Input, Active High This signal used Ethernet controller selection PCnet-SCSI controller during configuration read write transaction. When active, IDSELB input NAND tree testing.
LOCK
Lock Input, Active LOCK used current master indicate atomic operation that require multiple transfers. slave device, PCnet-SCSI controller locked master device. When another master attempts access PCnet-SCSI while locked, PCnet-SCSI controller will respond asserting DEVSEL STOP with TRDY deasserted (PCI retry). PCnet-SCSI controller will never assert LOCK master. When active, LOCK input NAND tree testing.
INTA
Interrupt Request Input/Output, Active Low, Open Drain This signal combines interrupt requests from both SCSI engine SCSI core. interrupt source determined reading SCSI Status Register. cleared when Status Register read. When active, INTA input NAND tree testing. This only time INTA input.
INTB
Interrupt Request Input/Output, Active Low, Open Drain asynchronous attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB, MPCO, TXSTRT. Each status flag mask which allows suppression INTB assertion. flags have following meaning:
BABL RCVCCO RPCO MISS MERR MPCO RINT IDON TXSTRT Babble Receive Collision Count Overflow Runt Packet Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
Parity Input/Output, Active High Parity even parity across AD[31:00] C/BE[3:0]. When PCnet-SCSI controller master, generates parity during address write data phases. checks parity during read data phases. When PCnet-SCSI controller operates slave mode target current cycle, generates parity during read data phases. checks parity during address write data phases. When active, input NAND tree testing.
PERR
Parity Error Input/Output, Active Low, Open Drain This signal asserted PCnet-SCSI controller when detects parity error during data phase when AD[31:00] lines inputs. PERR only active when PERREN (bit command register set.
When active, INTB input NAND tree testing. This only time INTB input.
Am79C974
PRELIMINARY PCnet-SCSI controller monitors PERR input during master write cycle. will assert Data Parity Reported Status register Configuration Space when parity error reported target device. When active, PERR input NAND tree testing.
When active, SERR input NAND tree testing.
STOP
Stop Input/Output, Active slave role, PCnet-SCSI controller drives STOP signal inform master stop current transaction. master role, PCnet-SCSI controller receives STOP signal stops current transaction. When active, STOP input NAND tree testing.
REQA
Request Input/Output, Active Am79C974's SCSI controller asserts REQA signal that wishes become master. Once asserted, REQA remains active until GNTA become active. When active, REQA input NAND tree testing. This only time REQA input.
TRDY
Target Ready Input/Output, Active This signal indicates PCnet-SCSI controller's ability selected device complete current data phase transaction. TRDY used conjunction with IRDY. data phase completed clock both TRDY IRDY asserted. During read TRDY indicates that valid data present AD[31:00]. During write, TRDY indicates that data been accepted. Wait states inserted until both IRDY TRDY asserted simultaneously. When active, TRDY input NAND tree testing.
REQB
Request Input/Output, Active Am79C974's Ethernet controller asserts REQB signal that wishes become master. Once asserted, REQB remains active until become active, independent subsequent assertion SLEEP setting STOP access S_RESET port (offset 14h). When active, REQB input NAND tree testing. This only time REQB input.
Reset Input, Active When asserted low, then PCnet-SCSI controller performs internal system reset type H_RESET (HARDWARE_RESET). must held minimum periods. While H_RESET state, PCnet-SCSI controller will disable deassert outputs. asynchronous when asserted deasserted. recommended that deassertion synchronous guarantee clean bounce free edge. When active, NAND tree testing enabled. interface pins input mode. result NAND tree testing observed BUSY output (pin 62).
Ethernet Controller Pins
Board Interface
LED1
LED1 Output This shared with EESK function. LED1, function polarity this programmable through BCR5. default, LED1 active indicates receive activity network. LED1 output from PCnet-SCSI controller capable sinking current necessary drive directly. LED1 also used during EEPROM Auto-detection determine whether EEPROM present PCnet-SCSI controller Microwire interface. trailing edge pin, LED1 sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. EEPROM Auto-detection section more details. circuit attached this pin, then pull pull down resistor must attached instead, order resolve EEDET setting.
SERR
System Error Input/Output, Active Low, Open Drain This signal asserted PCnet-SCSI controller when detects parity error during address phase when AD[31:00] lines inputs. SERR only active when SERREN (bit PERREN (bit command register set.
Am79C974
PRELIMINARY Both XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP asserted while asserted, then PCnet-SCSI controller will wait assertion GNT. When asserted, signal will deasserted then PCnet-SCSI controller will proceed power savings mode. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay assertion SLEEP until three cycles after completion valid operation. SLEEP does affect SCSI section.
LED3
LED3 Output This shared with EEDO function Microwire serial EEPROM interface. When functioning LED3, signal this programmable through BCR7. default, LED3 active indicates transmit activity network. Special attention must given external circuitry attached this pin. circuit were directly attached this pin, would create requirement that could serial EEPROM that would also attached this pin. Therefore, this used additional output while EEPROM used system, then buffering required between LED3 circuit. EEPROM included system design, then LED3 signal directly connected without buffering. LED3 output from PCnet-SCSI controller capable sinking current necessary drive this case. more details regarding connection, section LEDs.
XTAL1
Crystal Oscillator Input Input
XTAL2
Crystal Oscillator Output Output crystal frequency determines network data rate. PCnet-SCSI controller supports quartz crystals generate frequency compatible with 8802-3 (IEEE/ANSI 802.3) network frequency tolerance jitter specifications. section External Crystal Characteristics section Manchester Encoder/Decoder) more detail. network data rate one-half crystal frequency. XTAL1 alternatively driven using external CMOS level source, which case XTAL2 must left unconnected. Note that when PCnet-SCSI controller coma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power will consumed driving this resistor. XTAL1 driven this time power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion REQ. Microwire EEPROM Interface
LNKST
LINK Status Output This provides driving LED. default, indicates active link connection 10BASE-T interface. This also programmed indicate other network status (see BCR4). LNKST polarity programmable, default, active LOW. Note that this multiplexed with EEDI function.
SLEEP
Sleep Input When SLEEP asserted (active LOW), PCnetSCSI controller performs internal system reset S_RESET type then proceeds into power savings mode. (The reset operation caused SLEEP assertion will affect registers.) interface section effected SLEEP. particular, access configuration space remains possible. None configuration registers will reset SLEEP. accesses PCnet-SCSI controller will result target abort response. PCnet-SCSI controller will assert while sleep mode. When SLEEP asserted, non-PCI interface outputs will placed their normal S_RESET condition. non-PCI interface inputs will ignored except SLEEP itself. De-assertion SLEEP results wake-up. system must refrain from starting network operations PCnet-SCSI device seconds following deassertion SLEEP signal order allow internal analog circuits stabilize.
EESK
EEPROM Serial Clock Input/Output EESK signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses Microwire interface protocol. EESK connected Microwire EEPROM's Clock pin. controlled either PCnet-SCSI controller directly during read entire EEPROM, indirectly host system writing BCR19, EESK also used during EEPROM Auto-detection determine whether EEPROM present
Am79C974
PRELIMINARY PCnet-SCSI controller Microwire interface. trailing edge signal, EESK sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. EEPROM Auto-detection section more details. EESK shared with LED1 function. circuit attached this pin, then pull pull down resistor must attached instead, order resolve EEDET setting. Attachment Unit Interface
Collision Input
differential input pair signaling PCnet-SCSI controller that collision been detected network media, indicated inputs being driven with pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. Operates pseudo levels.
EEDO
EEPROM Data Input EEDO signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDO connected Microwire EEPROM's Data Output pin. controlled EEPROM during reads. read host system reading BCR19 EEDO shared with LED3 function.
Data Input
differential input pair PCnet-SCSI controller carrying Manchester encoded data from network. Operates pseudo levels.
Data Output
differential output pair from PCnet-SCSI controller transmitting Manchester encoded data network. Operates pseudo levels. Twisted-Pair Interface
EECS
EEPROM Chip Select Output function EECS signal indicate Microwire EEPROM device that being accessed. EECS signal active high. controlled either PCnet-SCSI controller during command portions read entire EEPROM, indirectly host system writing BCR19
RXD±
10BASE-T Receive Data Input 10BASE-T port differential receivers.
TXD± 10BASE-T Transmit Data Output
10BASE-T port differential drivers.
EEDI
EEPROM Data Output EEDI signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions output. This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDI connected Microwire EEPROM's Data Input pin. controlled either PCnet-SCSI controller during command portions read entire EEPROM, indirectly host system writing BCR19 EEDI shared with LNKST function.
TXP± 10BASE-T Pre-Distortion Control Output
These outputs provide transmit pre-distortion control conjunction with 10BASE-T port differential drivers.
Am79C974
SCSI Controller Pins
SCSI Interface Signals SCSI Pins
SCSI^RST
Reset Input/Output, Active Low, Schmitt Trigger, Open Drain SCSI input signal Schmitt trigger output signal drive.
[7:0]
SCSI Data Input/Output, Active Low, Open Drain/Active Negation, Schmitt Trigger These pins defined bi-directional SCSI data bus.
Request Input, Active Low, Schmitt Trigger This SCSI input signal with Schmitt trigger initiator mode.
SCSI Data Parity Input/Output, Active Low, Open Drain/Active Negation, Schmitt Trigger This defined bi-directional SCSI data parity.
Acknowledge Output, Active Low, Open Drain/Active Negation This SCSI output signal with drive initiator mode.
Message Input, Active Low, Schmitt Trigger Schmitt trigger input initiator mode.
SCSI
SCSI Clock Input SCSI clock signal used generate internal device timings. maximum frequency this input minimum required maintain SCSI timings.
Command/Data Input, Schmitt Trigger Schmitt trigger input initiator mode.
Input/Output Input, Schmitt Trigger Schmitt trigger input initiator mode.
Attention Output, Active Low, Open Drain This signal output initiator mode. This signal will asserted when device detects parity error; also, asserted certain commands.
Note: clock must supplied this input achieve Mbyte/s Synchronous Fast SCSI transfers.
PWDN
Power Down Indicator Input, Active High This signal, when asserted, sets PWDN status status register sends interrupt host.
Busy Input/Output, Active Low, Schmitt Trigger, Open Drain SCSI input signal Schmitt trigger output signal drive.
Test Interface BUSY
NAND Tree Output, Active This signal logically equivalent SCSI signal BSY. duplicated that external logic connected monitor SCSI activity. results NAND tree testing observed BUSY where asserted; otherwise, BUSY will reflect state SCSI Signal line (pin 64).
Select Input/Output, Active Low, Schmitt Trigger, Open Drain SCSI input signal Schmitt trigger output signal drive.
Am79C974
Miscellaneous RESERVED
Reserved_DO CONNECT Input This (#116) reserved internal test logic. MUST CONNECTED anything proper chip operation. It's subject change future products.
Digital Power Supply Pins VDD/DVDD
Digital Power Pins) Power There power supply pins that used internal digital circuitry. pins must connected supply.
Power Supply Pins Analog Power Supply Pins AVDD
Analog Power Pins) Power There four analog supply pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix Technical Manual (PID #18738A) details.
VDDB/VDDB
Buffer Power Pins) Power There power supply pins that used Input/Output buffer drivers. VDDB pins must connected supply.
VSS/DVSS
Digital Ground Pins) Ground There ground pins that used internal digital circuitry.
AVSS
Analog Ground Pins) Power There analog ground pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix Technical Manual (PID #18738A) details.
VSSB/VSSBS
Buffer Ground Pins) Ground There ground pins that used Input/Output buffer drivers.
Am79C974
PRELIMINARY registers used controller operating modes, enable disable various features, start certain operations, monitor operating status. addition registers space, Ethernet controller uses certain data structures that (typically host computer) normal memory space. These data structures initialization block that contains configuration data that Ethernet controller automatically loads into Configuration Status Registers (CSRs), Receive Transmit Descriptor Rings, that contain pointers receive transmit buffers status control information about these buffers, receive transmit buffers. Ethernet controller uses master accesses read locations buffers, store frames received from network into receive buffers, transmit contents transmit buffers.
BASIC FUNCTIONS System Interface Function
During normal operations Am79C974 operates master with slave accesses status control functions. Ethernet controller initialized through combination Configuration Space accesses, space Slave accesses, Memory Space Master accesses, optional reads external serial EEPROM. EEPROM read through Microwire interface either automatically Am79C974 indirectly series slave accesses Ethernet Configuration Registers (BCRs). EEPROM normally contains 8802-3 (IEEE/ ANSI 802.3) Ethernet node address data loaded into some Ethernet BCRs. SCSI controller initialized slave writes SCSI Core SCSI registers.
Ethernet Interfaces
Am79C974 controller connected 802.3 network network interfaces. Attachment Unit Interface (AUI) provides 8802-3 (IEEE/ANSI 802.3) compliant differential interface remote on-board transceiver. 10BASE-T interface provides twisted-pair Ethernet port. While auto-selection mode, interface determined auto-sensing mechanism which checks link status 10BASE-T port. there active link status, then device assumes connection.
Software Interface
Am79C794 uses four address spaces: Ethernet configuration space, SCSI configuration space, space, memory space. SCSI configuration space selected when IDSELA active. Ethernet configuration space selected when IDSELB active. that IDSELA IDSELB controlled depends external hardware. Section 3.6.4.1 Specification recommends methods generating configuration cycles called Configuration Mechanism Configuration Mechanism Configuration Spaces used system software identify SCSI Ethernet controllers device configuration without jumpers. Certain configuration registers have read-only information about devices resource requirements. Other registers used mail boxes that system configuration software uses inform other software what resources have been allocated device. only Configuration Registers that affect operation Am79C794 SCSI Ethernet Base Address Registers, which found offset each configuration spaces, Command Registers offset Writing these registers establishes base address SCSI space base address Ethernet space. SCSI controller registers occupy bytes space that starts whatever 128-byte boundary that programmed into Base Address Register offset SCSI Configuration Space. Ethernet controller registers occupy bytes space that starts whatever 32-byte boundary that programmed into Base Address Register offset Ethernet Configuration Space. These
SCSI Interfaces
Am79C974 acts bridge between SCSI buses. maximum data transfer rate very high Mbyte/s compared with SCSI Mbyte/s, buffering required between buses. buffering provided FIFOs: 16-byte (16X8 bits) SCSI Core FIFO additional 96-byte (24X32 bits) FIFO. These FIFOs provide temporary storage command, data, status message bytes they transferred between 32-bit 8-bit SCSI bus. Am79C974's SCSI Core registers addressed using value Base Address Register (offset Configuration Space). SCSI registers occupy double words engine registers occupy double word locations. address follows:
Start Offset 0x0000 0x0040 Offset 0x003F 0x005F Block Name SCSI Core Size DW/64B DW/32B
configuration space, Ethernet controller SCSI controller described detail following sections.
Am79C974
DETAILED FUNCTIONS Interface Unit (BIU)
interface unit built several state machines that synchronously CLK. interface unit state machine handles accesses where Am79C974 controller slave, another handles accesses where Am79C974 controller master. inputs synchronously sampled. outputs synchronously generated rising edge CLK. descriptions that follow, GNT, REQ, INT, IDSEL used refer GNTA, REQA, INTA, IDSELA SCSI controller GNTB, REQB, INTB, IDSELB Ethernet Controller, respectively. Slave Configuration Transfers host access Am79C974 configuration
space with configuration read write command. Am79C974 controller will assert DEVSEL IDSEL input asserted during address phase access configuration cycle. DEVSEL asserted clock cycles after host asserted FRAME. configuration cycles fixed length. Am79C974 controller will assert TRDY clock data phase. Slave Configuration Read Slave Configuration Read command used host read configuration space Am79C974 controller. This provides host with information concerning device capabilities. This single cycle, non-burst 8-bit, 16-bit, 32-bit transfer.
FRAME
ADDR
DATA
C/BE
1010
BE's
IRDY
TRDY
DEVSEL
STOP
IDSEL
18681A-5
Figure Slave Configuration Read
Am79C974
Slave Configuration Write
PRELIMINARY control basic activity device, such enable/disable, change location, etc. This single cycle, non-burst 8-bit, 16-bit, 32-bit transfer.
Slave Configuration Write command used host write configuration space Am79C974 controller. This allows host
FRAME
ADDR
DATA
C/BE
1011
BE's
IRDY
TRDY
DEVSEL
STOP
IDSEL
18681A-6
Figure Slave Configuration Write
Am79C974
PRELIMINARY Slave Transfers After Am79C974 controller configured device setting IOEN Command register), starts monitoring access internal registers. Am79C974 controller will look address that falls within address space. Am79C974 controller will assert DEVSEL detects address match access cycle. DEVSEL asserted clock cycles after host asserted FRAME. Am79C974 controller will assert DEVSEL detects address match, command type read write.
Am79C974 controller will suspend looking cycles while being master. Slave Read Slave Read command used host read Am79C974's CSRs, BCRs EEPROM locations SCSI registers. single cycle, non-burst 8-bit,16-bit 32-bit transfer which initiated host CPU. typical number wait states added slave read access part Am79C974 controller clock cycles. Am79C974 controller will produce Slave Read commands while being master.
FRAME
ADDR
DATA
C/BE
0010
BE's
IRDY
TRDY
DEVSEL
STOP
18681A-7
Figure Slave Read
Am79C974
Slave Write
PRELIMINARY initiated host CPU. typical number wait states added slave write access part Am79C974 controller clock cycles. Am79C974 controller will produce Slave write commands while being master.
Slave Write command used host write Am79C974's CSRs, BCRs EEPROM locations SCSI registers. single cycle, non-burst 8-bit, 16-bit, 32-bit transfer which
FRAME
ADDR
DATA
C/BE
0011
BE's
IRDY
TRDY
DEVSEL
STOP
18681A-8
Figure Slave Write
Am79C974
PRELIMINARY Acquisition Am79C974 microcode buffer management section) will determine when transfer should initiated. first step Am79C974 master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal. Figure shows Am79C974 controller acquisition. asserted clock Am79C974 controller starts driving AD[31:00] C/BE[3:0] prior clock FRAME asserted clock indicating valid address command AD[31:00] C/BE[3:0]. ADSTEP (bit Command register indicated that Am79C974 controller uses address stepping. Address stepping only used first address phase master period.
FRAME
ADDR
C/BE
18681A-9
Figure Acquisition
Am79C974
Master Transfers
PRELIMINARY indicated buffer pointer value. such instances, Am79C974 controller will internally discard unneeded bytes. Figure shows typical non-burst read access. Am79C974 controller asserts IRDY clock immediately after address phase starts sampling DEVSEL. target extends cycle asserting DEVSEL until clock Additionally, target inserts wait state asserting ready (TRDY) clock
There four primary types transfers. Am79C974 controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Cycles Am79C974 controller non-burst read accesses command type Memory Read (type Note that during non-burst read operations, Am79C974 controller will always activate byte enables, even though some byte lanes contain valid data
FRAME
ADDR
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-10
Figure Non-Burst Read Cycles With Wait States
Am79C974
PRELIMINARY Figure shows non-burst read access within arbitration cycle. Am79C974 controller will drop FRAME between consecutive non-burst read cycles. Am79C974 controller will re-request right again preempted before starting second
access. example below also shows target that respond Am79C974 controller read cycles without wait states.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-11
Figure Non-Burst Read Cycles Without Wait States
Am79C974
Basic Non-Burst Write
PRELIMINARY immediately preempted before starting second access. example below shows extended cycle first access. target asserts DEVSEL clock cycles after address phase (FRAME asserted) adds extra wait state asserting TRDY only clock second write cycle example shows ZERO wait state access.
Am79C974 controller non-burst write accesses command type Memory Write (type Figure shows non-burst write access within arbitration cycle. Am79C974 controller will drop FRAME between consecutive non-burst write cycles. Am79C974 controller will re-request
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
BE's
0111
BE's
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-12
Figure Non-Burst Write Cycles With Without Wait States
Am79C974
PRELIMINARY Basic Burst Read Cycles Am79C974 controller burst read transfers command type Memory Read Line (type14). AD[1:0] will both ZERO during address phase indicating linear burst order. four byte enable signals will ZERO during data phase Am79C974 controller always reads full 32-bit word when burst mode.
Figure shows typical burst read access. Am79C974 controller arbitrates bus, granted access, reads four 32-bit words (DWORD) from system memory then releases bus. four data phases this example take clock cycles each, which determined timing TRDY.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-13
Figure Burst Read Cycles
Am79C974
Basic Burst Write Cycles
PRELIMINARY Am79C974 controller arbitrates bus, granted access, writes four 32-bit words (DWORDs) from system memory then releases bus. this example, memory system extends data phase first access wait state. following three data phases take clock cycle each, which determined timing TRDY.
Am79C974 controller burst write transfers command type Memory Write (type AD[1:0] will both ZERO during address phase indicating linear burst order. four byte enable signals will ZERO during data phase Am79C974 controller always writes full 32-bit word when burst mode. Figure shows typical burst write access.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-14
Figure Burst Write Cycles
Am79C974
Transaction Termination
Termination transaction initiated either master target. During termination, master remains control bring transactions orderly systematic conclusion regardless what caused termination. transactions concluded when FRAME IRDY both deasserted, indicating IDLE cycle. Target Initiated Termination When Am79C974 controller master, cycles produces terminated target three different ways: Disconnect with data transfer, disconnect without data transfer, target abort.
Disconnect With Data Transfer Figure shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination sequence. Data still transferred during this cycles, since both IRDY TRDY asserted. Am79C974 controller terminates current transfer with deassertion FRAME clock then clock cycle later with deassertion IRDY. finally releases clock Am79C974 controller will re-request after clock cycles, wants transfer more data. starting address transfer will address next untransferred data.
FRAME
ADDR
DATA
DATA
ADDR
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled Am79C974 controller.
18681A-15
Figure Disconnect with Data Transfer
Am79C974
Disconnect Without Data Transfer
PRELIMINARY cycle later with deassertion IRDY. finally releases clock Am79C974 controller will re-request after clock cycles retry last transfer. starting address transfer will same address last untransferred data.
Figure shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. Am79C974 controller terminates current transfer with deassertion FRAME clock clock
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled Am79C974 controller.
18681A-16
Figure Disconnect Without Data Transfer
Am79C974
PRELIMINARY Target Abort Figure shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retried. Additionally, Am79C974 controller cannot make assumption about success previous data transfers current transaction. Am79C974 controller terminates current transfer with deassertion FRAME clock clock cycle later with deassertion IRDY. finally releases clock
Since data integrity guaranteed, Am79C974 controller cannot recover from target abort event. Ethernet, Am79C974 controller will reset locations their H_RESET values. ongoing network activity will stopped immediately. configuration registers will cleared. SCSI, when target aborts, INTA will asserted, ABORT (bit status register offset 54h), set. either Ethernet SCSI target abort causes RTABORT (bit status register appropriate configuration space set.
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled Am79C974 controller.
18681A-17
Figure Target Abort
Am79C974
Master Initiated Termination
PRELIMINARY when transferring data. FRAME deasserted between address phases. While FRAME deasserted, central arbiter remove Am79C974 controller time service another master. When removed, Am79C974 controller will finish current transfer then release bus. will keep asserted regain ownership soon possible.
There three scenarios besides normal completion transaction where Am79C974 controller will terminate cycles produces bus. These Preemption with without FRAME assertion Master Abort. Preemption When FRAME Deasserted Am79C974 controller generate multiple address phases during single ownership period
FRAME
ADDR
DATA
C/BE
0111
BE's
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-18
Figure Preemption When FRAME Deasserted
Am79C974
PRELIMINARY Preemption When FRAME Asserted central arbiter take Am79C974 controller away current operation takes long. This happen, example, when Am79C974 controller tries fill whole Ethernet transmit FIFO target inserts extra wait states every data phase. When taken away, Am79C974 con-
troller will finish current transfer then immediately release bus. Latency Timer configuration space Am79C974 controller always ZERO. Am79C974 controller will keep asserted regain ownership soon possible.
FRAME
ADDR
DATA
DATA
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-19
Figure Preemption When FRAME Asserted
Am79C974
Master Abort
PRELIMINARY configuration registers will cleared. SCSI, when master aborts, INTA will asserted, ABORT (bit status register offset 54h), set. either Ethernet SCSI master abort causes RMABORT (bit status register appropriate configuration space set.
Am79C974 controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error Am79C974 controller. Ethernet, Am79C974 controller will reset locations their H_RESET values. on-going network activity will stopped immediately.
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled Am79C974 controller.
18681A-20
Figure Master Abort
Am79C974
Ethernet Controller
Buffer Management Unit (BMU) buffer management unit micro-coded state machine which implements initialization procedure manages descriptors buffers. buffer management unit operates half speed input.
detection certain error conditions (MERR, UFLO, BUFF error). Reinitialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same Am79C974 controller LANCE. particular, upon restart, Am79C974 controller reloads transmit receive descriptor pointers with their respective base addresses. This means that software must clear descriptor bits reset descriptor ring pointers before restart Am79C974 controller. reload descriptor base addresses performed LANCE only after initialization, restart LANCE without initialization leaves LANCE pointing same descriptor locations before restart.
Initialization
Am79C974 initialization includes reading initialization block memory obtain operating parameters. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. DWORDs read during each period mastership. When SSIZE32 (BCR20, this results total arbitration cycles arbitration cycles SSIZE32 Once initialization block been completely read internal registers have been updated, IDON will CSR0, interrupt generated IENA set). this point, knows where receive transmit descriptor rings hence, normal network operations will begin. Am79C974 controller obtains start address Initialization Block from contents CSR1 (least significant bits address) CSR2 (most significant bits address). host must write CSR1 CSR2 before setting INIT bit. block contains user defined conditions Am79C974 operation, together with base addresses length information transmit receive descriptor rings. There alternative method initialize Am79C974 controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method used discretion programmer. registers written directly, INIT must set, initialization block will read thus overwriting previously written information. Please refer Appendix details this alternative method. initialization done writing directly registers, Polling Interval register (CSR47) must initialized addition those registers that loaded automatically from initialization block.
Buffer Management
Buffer management accomplished through message descriptor entries organized ring structures memory. There rings, receive ring transmit ring. size message descriptor entry DWORDs, bytes, when SSIZE32 size message descriptor entry words, bytes, when SSIZE32
Descriptor Rings
Each descriptor ring must organized contiguous area memory. initialization time (setting INIT CSR0), Am79C974 controller reads user-defined base address transmit receive descriptor rings, well number entries contained descriptor rings. Descriptor ring base addresses must 16-byte boundary when SSIZE32=1, 8-byte boundary when SSIZE=0. maximum 512, depending upon value SSIZE32) ring entries allowed when ring length through TLEN RLEN fields initialization block. However, ring lengths beyond this range 65535) writing transmit receive ring length registers (CSR76, CSR78) directly. Each ring entry contains following information: address actual message data buffer user host memory length message buffer Status information indicating condition buffer permit queuing de-queuing message buffers, ownership each buffer allocated either Am79C974 controller host. within descriptor status information, either (see section RMD), used this purpose. signifies that Am79C974 controller cur43
Re-Initialization
transmitter receiver sections Am79C974 controller turned initialization block (MODE Register DTX, bits; CSR15[1:0]). states transmitter receiver monitored host through CSR0 (RXON, TXON bits). Am79C974 controller should reinitialized transmitter and/or receiver were turned during original initialization, subsequently required activate them either section shut
Am79C974
PRELIMINARY base address both transmit receive descriptor rings into CSRs Am79C974 controller during subsequent operations. final step self-initialization process, base address each ring loaded into each current descriptor address registers address next descriptor entry transmit receive rings computed loaded into each next descriptor address registers. When SSIZE32 software data structures bits wide. following diagram, Figure illustrates relationship between Initialization Base Address, Initialization Block, Receive Transmit Descriptor Ring Base Addresses, Receive Transmit Descriptors Receive Transmit Data Buffers, case SSIZE32
rently ownership this ring descriptor associated buffer. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. device may, however, read from descriptor that does currently own. Software should always read descriptor entries sequential order. When software finds that current descriptor owned Am79C974 controller, then software must read "ahead" next descriptor. software should wait unOWNed descriptor until ownership been granted software (when LAPPEN (CSR3, then this rule modified. LAPPEN description). Strict adherence these rules insures that "Deadly Embrace" conditions avoided.
Descriptor Ring Access Mechanism
initialization, Am79C974 controller reads
24-Bit Base Address Pointer Initialization Block CSR2
IADR[23:16]
Descriptor Ring
desc. start desc. start
CSR1
IADR[15:0]
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block
MODE PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN TLEN RDRA[23:16] TDRA[15:0] TDRA[23:16]
Buffers
Data Buffer
Data Buffer
Data Buffer
DESCRIPTOR RINGS
Descriptor
DESCRIPTOR RINGS Ring
desc. start
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
18681A-21
Figure 16-Bit Data Structures: Initialization Block Descriptor Rings Am79C974
PRELIMINARY When SSIZE32 software data structures bits wide. following diagram illustrates, Figure relationship between Initialization Base Address, Initialization Block, Receive Transmit
Descriptor Ring Base Addresses, Receive Transmit Descriptors Receive Transmit Data Buffers, case SSIZE32
32-Bit Base Address Pointer Initialization Block CSR2
IADR[31:16]
Descriptor Ring
desc. start desc. start
CSR1
IADR[15:0]
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block
TLEN RLEN MODE PADR[31:0] PADR[47:32] LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Buffers
Data Buffer
Data Buffer
Data Buffer
DESCRIPTOR RINGS
Descriptor
DESCRIPTOR RINGS Ring
desc. start
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
18681A-22
Figure 32-Bit Data Structures: Initialization Block Descriptor Rings
Am79C974
PRELIMINARY DPOLL=0 (CSR4, TXON=1 (CSR0, poll time elapsed, Am79C974 controller does possess ownership current TDTE DPOLL=0 TXON=1 frame just been received, Am79C974 controller does possess ownership current TDTE DPOLL=0 TXON=1 frame just been transmitted. Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. microcode executing poll counting code when TDMD set, then demanded poll TDTE will delayed until microcode returns poll counting code. user change poll time value from default 65,536 clock periods modifying value Polling Interval register (CSR47). Note that non- default value desired, then strict sequence setting INIT CSR0, waiting IDON CSR0, then writing CSR47, then setting STRT CSR0 must observed, otherwise default value will overwritten. CSR47 section details.
Polling
there network channel activity there pre- post-receive pre- post-transmit activity being performed Am79C974 controller, then Am79C974 controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following: Am79C974 controller will current receive descriptor address stored internally vector appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). accesses will made following order: RMD1, then RMD0 current RDTE during arbitration, after that, TMD1, then TMD0 current TDTE during second arbitration. information collected during polling activity will stored internally appropriate CSRs. (i.e. CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52). UnOWNed descriptor status will internally ignored. typical receive poll product following conditions: Am79C974 controller does possess ownership current RDTE poll time elapsed RXON=1 (CSR0, Am79C974 controller does possess ownership next RDTE poll time elapsed RXON=1. RXON=0 Am79C974 controller will never poll RDTE locations. ideal system should always have least RDTE available possibility unpredictable receive event. (This condition requirement. this condition met, simply means that frames will missed system because there buffer space available.) typical system usually least RDTEs available possibility unpredictable receive event. Given that this condition satisfied, current next RDTE polls rarely seen hence, typical poll operation simply consists check status current TDTE. When there only RDTE (because RLEN ZERO), then there "next RDTE" ownership "next RDTE" cannot checked. there least RDTE, RDTE poll will rarely seen typical poll operation simply consists check current TDTE. typical transmit poll product following conditions: Am79C974 controller does possess ownership current TDTE
Transmit Descriptor Table Entry (TDTE)
after TDTE access, Am79C974 controller finds that that TDTE set, then Am79C974 controller resumes poll time count reexamines same TDTE next expiration poll time count. TDTE set, Start Frame (STP) set, Am79C974 controller will immediately request order reset this descriptor. (This condition would normally found following LCOL RETRY error that occurred middle transmit frame chain buffers.) After resetting this descriptor, Am79C974 controller will again immediately request order access next TDTE location ring. buffer length will reset. LANCE buffer length interpreted 4096-byte buffer. acceptable have length buffer transmit with acceptable have length buffer with start frame (STP) set, then microcode control proceeds routine that will enable transmit data transfers FIFO.
Am79C974
PRELIMINARY Am79C974 controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. (More than transmit data transfer possibly take place, depending upon state transmitter.) contents TMD0 TMD1 will stored Next Buffer Address (CSR64 CSR65), Next Byte Count (CSR66) Next Status (CSR67) regardless state bit. This transmit descriptor lookahead operation performed only once. Am79C974 controller does next TDTE (i.e. second TDTE this frame), then will complete transmission current buffer then update status current (first) TDTE with BUFF UFLO bits being set. This will cause transmitter disabled (CSR0, TXON=0). Am79C974 controller will have re-initialized restore transmit function. situation that matches this description implies that system been able stay ahead Am79C974 controller transmit descriptor ring therefore, condition treated fatal error. avoid this situation, system should always transmit chain descriptor bits reverse order.) Am79C974 controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer update status first descriptor (reset TMD1), then perform data access second buffer chain before executing another lookahead operation. (i.e. lookahead third descriptor.) Am79C974 controller queue frames transmit FIFO. Call them frame frame "Y", where after "X". Assume that frame currently being transmitted. Because Am79C974 controller perform lookahead data transfer past frame "X", possible Am79C974 controller completely transfer data from buffer belonging frame into FIFO even though frame been completely transmitted. this buffer data transfer, Am79C974 controller will write intermediate status (change ZERO) frame buffer, frame uses data chaining. last TDTE frame (containing ENP) been written, since frame been completely transmitted. Note that Am79C974 controller has, this instance, returned ownership TDTE host "normal" sequence.
this reason, becomes imperative that host system should never read Transmit ownership bits order. Software should always process buffers sequence, waiting ownership before proceeding. There should problems software which processes buffers sequence, waiting ownership before proceeding. error occurs transmission before bytes current buffer have been transferred, then TMD2 TMD1 current buffer will written; such case, data transfers from next buffer will commence. Instead, following TMD2/TMD1 update, Am79C974 controller will next transmit frame, any, skipping over rest frame which experienced error, including chained buffers. This done returning polling microcode where Am79C974 controller will immediately access next descriptor find condition OWN=1 STP=0 described earlier. described that case, Am79C974 controller will reset this descriptor continue like manner until descriptor with OWN=0 more transmit frames ring) OWN=1 STP=1 (the first buffer frame) reached. transmit operation, whether successful with errors, immediately following completion descriptor updates, Am79C974 controller will always perform another poll operation. described earlier, this poll operation will begin with check current RDTE, unless Am79C974 controller already owns that descriptor. Then Am79C974 controller will proceed polling next TDTE. transmit descriptor ZERO value, then Am79C974 controller will resume poll time count incrementing. transmit descriptor value ONE, then Am79C974 controller will begin filling FIFO with transmit data initiate transmission. This end-of- operation poll coupled with TDTE lookahead operation allows Am79C974 controller avoid inserting poll time counts between successive transmit frames. Whenever Am79C974 controller completes transmit frame (either with without error) writes status information current descriptor, then TINT CSR0 indicate completion transmission. This causes interrupt signal IENA CSR0 been TINbit CSR3 reset.
Am79C974
PRELIMINARY scriptor. case, lookahead will performed third buffer information gathered will stored chip, regardless state ownership bit. transmit flow, lookahead operations performed only once. This activity continues until Am79C974 controller recognizes completion frame (the last byte this receive message been removed from FIFO). Am79C974 controller will subsequently update current RDTE status with frame (ENP) indication set, write message byte count (MCNT) complete frame into RMD2 overwrite "current" entries CSRs with "next" entries.
Receive Descriptor Table Entry (RDTE)
Am79C974 controller does both current next Receive Descriptor Table Entry then Am79C974 controller will continue poll according polling sequence described above. receive descriptor ring length then there next descriptor polled. poll operation revealed that current next RDTE belong Am79C974 controller then additional poll accesses necessary. Future poll operations will include RDTE accesses long Am79C974 controller retains ownership current next RDTE. When receive activity present channel, Am79C974 controller waits complete address message arrive. then decides whether accept reject frame based active addressing schemes. frame accepted Am79C974 controller checks current receive buffer status register CRST (CSR41) determine ownership current buffer. ownership lacking, then Am79C974 controller will immediately perform (last ditch) poll current RDTE. ownership still denied, then Am79C974 controller buffer which store incoming message. Missed Frame Count register (CSR112) will incremented MISS will CSR0 interrupt will generated IENA=1 (CSR0) MISSM=0 (CSR3). Another poll current RDTE will occur until frame finished. Am79C974 controller sees that last poll (either normal poll, last-ditch effort described above paragraph) current RDTE shows valid ownership, then proceeds poll next RDTE. Following this poll, regardless outcome this poll, transfers receive data from FIFO begin. Regardless ownership second receive descriptor, Am79C974 controller will continue perform receive data transfers first buffer. frame length exceeds length first buffer, Am79C974 controller does second buffer, ownership current descriptor will passed back system writing ZERO RMD1 status will written indicating buffer (BUFF=1) possibly overflow (OFLO=1) errors. frame length exceeds length first (current) buffer, Am79C974 controller does second (next) buffer, ownership will passed back system writing ZERO RMD1 when first buffer full. Receive data transfers second buffer occur before Am79C974 controller proceeds look ahead ownership third buffer. Such action will depend upon state FIFO when status been updated first de48
Media Access Control
Media Access Control engine incorporates essential protocol requirements operation compliant Ethernet/802.3 node, provides interface between FIFO sub-system Manchester Encoder/Decoder (MENDEC). engine fully compliant Section ISO/ 8802-3 (ANSI/IEEE Standard 1990 Second edition) ANSI/IEEE 802.3 (1985). engine provides programmable enhanced features designed minimize host supervision, utilization, pre- post- message processing. These include ability disable retries after collision, dynamic generation frame-by-frame basis, automatic field insertion deletion enforce minimum frame size attributes, automatic retransmission without reloading FIFO, automatic deletion collision fragments, reduces bandwidth use. primary attributes engine are: Transmit receive message data encapsulation. Framing (frame boundary delimitation, frame synchronization). Addressing (source destination address handling). Error detection (physical medium transmission errors). Media access management. Medium allocation (collision avoidance). Contention resolution (collision handling). Transmit Receive Message Data Encapsulation engine provides minimum frame size enforcement transmit receive frames. When APAD_XMT (CSR, 11), transmit messages will padded with sufficient bytes (containing 00h) ensure that receiving station will observe information field (destination address, source address, length/type, data FCS) 64-bytes. When
Am79C974
PRELIMINARY ASTRP_RCV (CSR4, 10), receiver will automatically strip bytes from received message observing value length field, stripping excess bytes this value below minimum data size bytes). Both features independently over-ridden allow illegally short (less than bytes frame data) messages transmitted and/or received. this feature reduces utilization because bytes transferred into main memory. Framing (Frame Boundary Delimitation, Frame Synchronization) engine will autonomously handle construction transmit frame. Once Transmit FIFO been filled predetermined threshold (set XMTSP CSR80), providing access channel currently permitted, engine will commence byte preamble sequence (10101010b, where first transmitted engine will subsequently append Start Frame Delimiter (SFD) byte (10101011b) followed serialized data from Transmit FIFO. Once data been completed, engine will append (most significant first) which computed entire data portion frame. data portion frame consists destination address, source address, length/type, frame data. user responsible correct ordering content each fields frame. receive section engine will detect incoming preamble sequence lock encoded clock. internal MENDEC will decode serial stream present this engine. will discard first 8-bits information before searching sequence. Once detected, subsequent bits treated part frame. engine will inspect length field ensure minimum frame size, strip unnecessary characters enabled), pass remaining bytes through Receive FIFO host. stripping performed, engine will also strip received bytes, although normal computation checking will occur. Note that apart from stripping, frame will passed unmodified host. length field value greater, engine will attempt validate length against number bytes contained message. frame terminates suffers collision before 64-bytes information (after SFD) have been received, engine will automatically delete frame from Receive FIFO, without host intervention. Am79C974 controller ability accept runt packets diagnostics purposes proprietary networks.
Addressing (Source Destination Address Handling) first 6-bytes information after will interpreted destination address field. engine provides facilities physical, logical (multicast) broadcast address reception. Error Detection (Physical Medium Transmission Errors) engine provides several facilities which report recover from errors medium. addition, network protected from gross errors inability host keep pace with engine activity. completion transmission, following transmit status available appropriate areas: exact number transmission retry attempts (ONE, MORE, RTRY TRC). Whether engine Defer (DEF) channel activity. Excessive deferral (EXDEF), indicating that transmitter experienced Excessive Deferral this transmit frame, where Excessive Deferral defined 8802-3 (IEEE/ANSI 802.3). Loss Carrier (LCAR), indicating that there interruption ability engine monitor transmission. Repeated LCAR errors indicate potentially faulty transceiver network connection. Late Collision (LCOL) indicates that transmission suffered collision after slot time. This indicative badly configured network. Late collisions should occur normal operating network. Collision Error (CERR) indicates that transceiver respond with Test message within predetermined time after transmission completed. This failed transceiver, disconnected faulty transceiver drop cable, fact transceiver does support this feature disabled). addition reporting network errors, engine will also attempt prevent creation network error inability host service engine. During transmission, host fails keep Transmit FIFO filled sufficiently, causing underflow, engine will guarantee message either sent runt packet (which will deleted receiving station) invalid (which will also cause receiver reject message).
Am79C974
PRELIMINARY Medium Allocation IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990) requires that CSMA/CD monitor medium traffic watching carrier activity. When carrier detected, media considered busy, should defer existing message. 8802-3 (IEEE/ANSI 802.3) Standard also allows optional part deferral after receive message.
status each receive message available appropriate areas. Framing errors (FRAM) reported, although received frame still passed host. FRAM error will only reported error detected there integral number bytes message. engine will ignore additional bits message (dribbling bits), which occur under normal network operating conditions. reception additional bits will cause engine de-serialize entire byte, will result received message being modified. Am79C974 controller handle dribbling bits when received frame terminates. During reception, generated every serial (including dribbling bits) coming from cable, although internally saved value only updated eighth each byte boundary). framing error reported user follows: number dribbling bits there (FCS) error, then there Framing error (FRAM number dribbling bits there (FCS) error, then there also Framing error (FRAM number dribbling bits then there Framing error. There (FCS) error. Counters provided report Receive Collision Count Runt Packet Count network statistics utilization calculations. Note that engine detects received frame which pattern preamble (after first bits which ignored), entire frame will ignored. engine will wait network inactive before attempting receive additional frames. Media Access Management basic requirement stations network provide fairness channel allocation. 802.3/Ethernet protocols define media access mechanism which permits stations access channel with equality. node attempt contend channel waiting predetermined time (Inter Packet internal) after last activity, before transmitting media. channel multidrop communications media (with various topological configurations permitted) which allows single station transmit other stations receive. nodes simultaneously contend channel, their signals will interact causing loss data, defined collision. responsibility attempt avoid recover from collision, guarantee data integrity end-to-end transmission receiving station.
ANSI/IEEE 802.3 -1990 Edition, 4.2.3.2.1: Note: possible carrier sense indication fail asserted during collision media. deference process simply times interFrame based this indication possible short interFrame generated, leading potential reception failure subsequent frame. enhance system robustness following optional measures, specified 4.2.8, recommended when InterFrameSpacingPart1 other than ZERO: Upon completing transmission, start timing interpacket gap, soon transmitting carrier Sense both false. When timing interFrame following reception, reset interFrame timing carrier Sense becomes true during first interFrame timing interval. During final interval timer shall reset ensure fair access medium. initial period shorter than interval permissible including ZERO.
engine implements optional receive part deferral algorithm, with first part inter-frame-spacing time second part inter-framespacing interval therefore Am79C974 controller will perform part deferral algorithm specified Section 4.2.8 (Process Deference). Inter Packet (IPG) timer will start timing InterFrameSpacing after receive carrier de-asserted. During first part deferral (InterFrameSpacingPart1 IFS1) Am79C974 controller will defer pending transmit frame respond receive message. counter will reset ZERO continuously until carrier de-asserts, which point counter will resume count once again. Once IFS1 period elapsed, Am79C974 controller will begin timing second part deferral (InterFrame Spacing Part IFS2) Once IFS1 completed, IFS2 commenced, Am79C974 controller will defer receive frame transmit frame pending. This means that Am79C974 controller will attempt receive receive frame, since will start transmit, generate collision Am79C974 controller will guarantee complete preamble (64-bit) (32-bit)
Am79C974
PRELIMINARY sequence before ceasing transmission invoking random backoff algorithm. This transmit part deferral algorithm implemented option which disabled using DXMT2PD CSR3. part deferral after transmission useful ensuring that severe shrinkage cannot occur specific circumstances, causing transmit message follow receive message closely make them indistinguishable. During time period immediately after transmission been completed, external transceiver case standard connected device), should generate Test message nominal burst Times duration) pair (within after transmission ceases). During time period which Test message expected Am79C974 controller will respond receive carrier sense. ANSI/IEEE 802.3-1990 Edition, 7.2.4.6 (1):
prior bits being transmitted, Engine will abort transmission, append sequence immediately. sequence 32-bit Zeros pattern. Engine will attempt transmit frame total times (initial attempt plus retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled, dependent backoff time that Engine computes. single retry required, will Transmit Frame Status. more than retry required, MORE will set. attempts experienced collisions, RTRY will (ONE MORE will clear), transmit message will flushed from FIFO. retries have been disabled setting DRTY CSR15, Engine will abandon transmission frame detection first collision. this case, only RTRY will transmit message will flushed from FIFO. collision detected after times have been transmitted, collision termed late collision. Engine will abort transmission, append sequence LCOL bit. retry attempt will scheduled detection late collision, transmit message will flushed from FIFO. 8802-3 (IEEE/ANSI 802.3) Standard requires "truncated binary exponential backoff" algorithm which provides controlled pseudo random mechanism enforce collision backoff interval, before re-transmission attempted. ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.5:
conclusion output function, opens time window during which expects signal_quality_error signal asserted Control circuit. time window begins when CARRIER_STATUS becomes CARRIER_OFF. execution output function does cause CARRIER_ON occur, test occurs DTE. duration window shall least more than During time window Carrier Sense Function inhibited."
Am79C974 controller implements carrier sense "blinding" period within from de-assertion carrier sense after transmission. This effectively means that when transmit part deferral enabled (DXMT2PD cleared) IFS1 time from after transmission. However, since shrinkage below will rarely encountered correctly configured networks, since fragment size will larger than blinding window, then counter will reset worst case shrinkage/fragment scenario Am79C974 controller will defer transmission. addition, Am79C974 controller will restart "blinding" period carrier detected within IFS1 period, will commence timing entire IFS1 period. Contention Resolution (Collision Handling) Collision detection performed reported engine integrated Manchester Encoder/Decoder (MENDEC). collision detected before complete preamble/SFD sequence been transmitted, Engine will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed,
enforcing collision (jamming), CSMA/CD sublayer delays before attempting retransmit frame. delay integer multiple slot Time. number slot times delay before re-transmission attempt chosen uniformly distributed random integer range:
where (n,10)." Am79C974 controller provides alternative algorithm, which suspends counting slot time/IPG during time that receive carrier sense detected. This aids networks where large numbers nodes present, numerous nodes collision. effectively accelerates increase backoff time busy networks, allows nodes involved collision access channel whilst colliding nodes await reduction channel activity. Once channel activity reduced, nodes resolving collision time their slot time counters normal.
Am79C974
PRELIMINARY Power Reset (POR) circuit, which ensures that analog portions Am79C974 controller forced into their correct state during power prevents erroneous data transmission and/or reception during this time. External Crystal Characteristics When using crystal drive oscillator, following crystal specification used ensure less than ±0.5 jitter DO±. Table below.
Manchester Encoder/Decoder (MENDEC)
integrated Manchester Encoder/Decoder provides (Physical Layer Signaling) functions required fully compliant 8802-3 (IEEE/ANSI 802.3) station. MENDEC provides encoding function data transmitted network using high accuracy on-board oscillator, driven either crystal oscillator external CMOS level compatible clock. MENDEC also provides decoding function from data received from network. MENDEC contains
Table Crystal Specification
Parameter Parallel Resonant Frequency Resonant Frequency Error Change Resonant Frequency With Respect Temperature Crystal Load Capacitance Motional Crystal Capacitance (C1) Series Resistance Shunt Capacitance Drive Level 0.022 Unit
External Clock Drive Characteristics When driving oscillator from CMOS level external clock source, XTAL2 must left floating (unconnected). external clock having following characteristics must used ensure less than ±0.5 jitter DO±. Table Table Clock Drive Characteristics
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time (tHIGH/tLOW): XTAL1 Falling Edge Falling Edge Jitter: ±0.01% from -0.5 ±0.2 input (VDD/2)
MENDEC Transmit Path transmit section encodes separate clock data input signals into standard Manchester encoded serial stream. transmit outputs (DO±) designed operate into terminated transmission lines. When operating into terminated transmission line, transmit signaling meets required output levels skew Cheapernet, Ethernet IEEE-802.3. Transmitter Timing Operation fundamental mode crystal oscillator provides
basic timing reference MENDEC portion Am79C974 controller. crystal divided two, create internal transmit clock reference. Both clocks into MENDECs Manchester Encoder generate transitions encoded data stream. internal transmit clock used MENDEC internally synchronize Internal Transmit Data (ITXDAT) from controller Internal Transmit Enable (ITXEN). internal transmit clock also used stable rate clock receive section MENDEC controller.
Am79C974
PRELIMINARY oscillator requires external 0.01% timing reference. accuracy requirements, external crystal used tighter because allowance on-board parasitics must made deliver final accuracy 0.01%. Transmission enabled controller. long ITXEN request remains active, serial output controller will Manchester encoded appear DO±. When internal request dropped controller, differential transmit outputs idle states, dependent TSEL Mode Register (CSR15,
TSEL LOW: idle state yields "ZERO" differential operate transformercoupled loads.
Receiver Path principal functions Receiver signal Am79C974 controller that there information receive pair, separate incoming Manchester encoded data stream into clock data. Receiver section (see Receiver Block Diagram) consists parallel paths. receive data path ZERO threshold, wide bandwidth line receiver. carrier path offset threshold bandpass detecting line receiver. Both receivers share common bias networks allow operation over wide input common mode range.
TSEL HIGH: this idle state, positive with respect (logical HIGH).
Data Receiver
Manchester Decoder
IRXDAT* ISRDCLK*
Noise Reject Filter
Carrier Detect Circuit
IRXCRS*
*Internal signal
18681A-23
Figure Receiver Block Diagram
Input Signal Conditioning Transient noise pulses input data stream rejected Noise Rejection Filter. Pulse width rejection proportional transmit data rate, (which fixed Ethernet could different proprietary networks). inputs more negative than minus also surpressed. Carrier Detection circuitry detects presence incoming data frame discerning rejecting noise from expected Manchester data, controls stop start phase-lock loop during clock acquisition. Clock acquisition requires valid Manchester pattern 1010b lock onto incoming message. When input amplitude pulse width conditions DI±, internal enable signal from MENDEC controller (IRXCRS) asserted clock acquisition cycle initiated.
Clock Acquisition When there activity (receiver idle), receive oscillator phase locked internal transmit clock. first negative clock transition (bit cell center first valid Manchester "0") after IRXCRS asserted interrupts receive oscillator. oscillator then restarted second Manchester (bit time phase locked result, MENDEC acquires clock from incoming Manchester pattern times with 1010b Manchester pattern. internal serial receive data clock, ISRDCLK internal received data, IRXDAT, enabled time after clock acquisition cell IRXDAT HIGH state when receiver idle ISRDCLK). IRXDAT however, undefined when clock acquired remain HIGH change state whenever ISRDCLK enabled. time through cell
Am79C974
PRELIMINARY strobed ISRDCLK transferred controller section, prevents extra bit(s) message. Data Decoding data receiver comparator with clocked output minimize noise sensitivity inputs. Input error less than minimize sensitivity input rise fall time. ISRDCLK strobes data receiver output time determine value Manchester bit, clocks data IRXDAT following ISRDCLK. data receiver also generates signal used phase detector comparison internal MENDEC voltage controlled oscillator (VCO). Differential Input Terminations differential input Manchester data (DI±) should externally terminated 40.2 resistors optional common-mode bypass capacitor, shown Differential Input Termination diagram below. differential input impedance, ZIDF, common-mode input impedance, ZICM, specified that Ethernet specification cable termination impedance using standard resistor terminators. devices used, nearest usable value. differential inputs terminated exactly same pair.
Isolation Transformer Am79C974
controller portion Am79C974 controller sees first ISRDCLK transition. This also strobes incoming fifth MENDEC Manchester "1". IRXDAT make transition after ISRDCLK rising edge cell state still undefined. Manchester clocked IRXDAT output time cell Tracking After clock acquisition, phase-locked clock compared incoming transition cell center (BCC) resulting phase error applied correction circuit. This circuit ensures that phaselocked clock remains locked received signal. Individual cell phase corrections Voltage Controlled Oscillator (VCO) limited phase difference between phase-locked clock. Hence, input data jitter reduced ISRDCLK Carrier Tracking Message carrier detection circuit monitors inputs after IRXCRS asserted message. IRXCRS de-asserts times after last positive transition incoming message. This initiates reception cycle. time delay from last rising edge message IRXCRS de-assert allows last
40.2
40.2 0.01
18681A-24
Figure Differential Input Termination
Am79C974
PRELIMINARY Collision Detection detects collision condition network generates differential signal inputs. This collision signal passes through input stage which detects signal levels pulse duration. When signal detected MENDEC sets internal collision signal HIGH. condition continues approximately times after last LOW-to-HIGH transition CI±. Jitter Tolerance Definition MENDEC utilizes clock capture circuit align internal data strobe with incoming stream. clock acquisition circuitry requires four valid bits with values 1010b. Clock phase-locked negative transition cell center second pattern. Since data strobed time, Manchester transitions which shift from their nominal placement through time will result improperly decoded data. With this criteria error, definition Jitter Handling peak deviation approaching crossing cell position from nominal input transition, which MENDEC section will properly decode data. Attachment Unit Interface (AUI) (Physical Layer Signaling) (Physical Medium Attachment) interface which effectively connects MAU. differential interface provided Am79C974 controller fully compliant Section 8802-3 (ANSI/IEEE 802.3). After Am79C974 controller initiates transmission will expect data "looped-back" pair (when port selected). This will internally generate "carrier sense", indicating that integrity data path from intact, that operating correctly. This "carrier sense" signal must asserted least times before last transmitted (when using port). "carrier sense" does become active response data transmission, becomes inactive before transmission, loss carrier (LCAR) error will Transmit Descriptor Ring (TMD2, after frame been transmitted.
squelch number additional features including Link Status indication, Automatic Twisted-Pair Receive Polarity Detection/Correction Indication, Receive Carrier Sense, Transmit Active Collision Present indication. Twisted-Pair Transmit Function differential driver circuitry TXD± TXP± pins provides necessary electrical driving capability pre-distortion control transmitting signals over maximum length Twisted-Pair cable, specified 10BASE-T supplement 8802-3 (IEEE/ ANSI 802.3) Standard. transmit function data output meets propagation delays jitter specified standard. Twisted-Pair Receive Function receiver complies with receiver specifications 8802-3 (IEEE/ANSI 802.3) 10BASE-T Standard, including noise immunity received signal rejection criteria (`Smart Squelch'). Signals meeting these criteria appearing RXD± differential input pair routed MENDEC. receiver function meets propagation delays jitter requirements specified standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals offset carrier fade event worst case signal attenuation crosstalk noise conditions. Note that 10BASE-T Standard defines receive input amplitude external Media Dependent Interface (MDI). Filter transformer loss specified. T-MAU receiver squelch levels defined account insertion loss MHz, which typical type receive filters/transformers employed. Normal 10BASE-T compatible receive thresholds employed when (CSR15[9]) LOW. When (HIGH), Receive Threshold option invoked, sensitivity T-MAU receiver increased. This allows longer line lengths employed, exceeding target distance normal 10BASE-T (assuming typical cable). increased receiver sensitivity compensates increased signal attenuation caused additional cable distance. However, making receiver more sensitive means that also more susceptible extraneous noise, primarily caused coupling from co-resident services (crosstalk). this reason, recommended that when using Receive Threshold option that service should installed 4-pair cable only. Multipair cables within same outer sheath have lower crosstalk attenuation, allow noise emitted from adjacent pairs couple into receive pair, sufficient amplitude falsely unsquelch T-MAU.
Twisted-Pair Transceiver (T-MAU)
T-MAU implements Medium Attachment Unit (MAU) functions Twisted-Pair Medium, specified supplement 8802-3 (IEEE/ANSI 802.3) standard (Type 10BASE-T). T-MAU provides twisted pair driver receiver circuits, including on-board transmit digital predistortion receiver
Am79C974
Link Test Function
PRELIMINARY signal correctly wired receiver, when link beat pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. Negative link beat pulses defined received signals with negative amplitude greater than with pulse width This negative excursion followed positive excursion. This definition consistent with expected received signal reverse wired receiver, when link beat pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. polarity detection/correction algorithm will remain "armed" until consecutive frames with valid identical polarity detected. When "armed", receiver capable changing initial previous polarity configuration based polarity. receipt first frame with valid following H_RESET link fail, T-MAU will utilize inferred polarity information configure RXD± input, regardless previous state. receipt second frame with valid with correct polarity, detection/correction algorithm will "lock-in" received polarity. second subsequent) frame detected confirming previous polarity decision, most recently detected polarity will used default. Note that frames with invalid have effect updating previous polarity decision. Once consecutive frames with valid have been received, T-MAU will disable detection/correction algorithm until either Link Fail condition occurs H_RESET activated. During polarity reversal, internal signal will active. During normal polarity conditions, this internal signal inactive. state this signal read software and/or displayed when enabled control bits Configuration Registers (BCR4-BCR7). Twisted-Pair Interface Status Three internal signals (XMT, COL) indicate whether T-MAU transmitting, receiving, collision state with both functions active simultaneously. These signals internal signals behavior outputs depends output circuitry programmed. T-MAU will power Link Fail state normal algorithm will apply allow enter Link Pass state. Link Pass state, transmit receive activity will indicated assertion signal going active. T-MAU selected using PORTSEL bits CSR15, then when moving from T-MAU selection T-MAU will forced into LINK Fail state. Link Fail state, XMT, inactive.
link test function implemented specified 10BASE-T standard. During periods transmit pair inactivity, 'Link beat pulses' will periodically sent over twisted pair medium constantly monitor medium integrity. When link test function enabled (DLNKTST CSR15 cleared), absence link beat pulses receive data RXD± pair will cause TMAU into link fail state. link fail state, data transmission, data reception, data loopback collision detection functions disabled, remain disabled until valid data consecutive link pulses appear RXD± pair. During link fail, Link Status (LNKST pin) signal inactive. When link identified functional, Link Status signal asserted. LNKST displays Link Status signal default. Transmission attempts during Link Fail state will produce network activity will produce LCAR CERR error indications. order inter-operate with systems which implement Link Test, this function disabled setting DLNKTST CSR15. With link test disabled, data driver, receiver loopback functions well collision detection remain enabled irrespective presence absence data link pulses RXD± pair. Link Test pulses continue sent regardless state DLNKTST bit. Polarity Detection Reversal T-MAU receive function includes ability invert polarity signals appearing RXD± pair polarity received signal reversed (such case wiring error). This feature allows data frames received from reverse wired RXD± input pair corrected T-MAU prior transfer MENDEC. polarity detection function activated following H_RESET Link Fail, will reverse receive polarity based both polarity previous link beat pulses polarity subsequent frames with valid Transmit Delimiter (ETD). When Link Fail state, T-MAU will recognize link beat pulses either positive negative polarity. Exit from Link Fail state made reception consecutive link beat pulses identical polarity. entry Link Pass state, polarity last link beat pulses used determine initial receive polarity configuration receiver reconfigured subsequently recognize only link beat pulses previously recognized polarity. Positive link beat pulses defined received signal with positive amplitude greater than (LRT HIGH) with pulse width This positive excursion followed negative excursion. This definition consistent with expected received
Am79C974
PRELIMINARY Collision Detect Function Activity both twisted pair signals RXD± TXD± constitutes collision, thereby causing signal activated. (COL used control circuits) will remain active until colliding signals changes from active idle. However, transmission attempt Link Fail state results LCAR CERR indication. stays active times collision. Signal Quality Error (SQE) Test (Heartbeat) Function function disabled when 10BASE-T port selected. Jabber Function Jabber function inhibits twisted pair transmit function T-MAU TXD± active excessive period ms). This prevents node from disrupting network `stuck-on' faulty transmitter. this maximum transmit time exceeded, T-MAU transmitter circuitry disabled, (CSR4, signal asserted. Once transmit data stream T-MAU removed, "unjab" time will elapse before T-MAU re-enables transmit circuitry. Power Down T-MAU circuitry made into power savings mode. This feature useful battery powered duty cycle systems. T-MAU will into power down mode when H_RESET active, coma mode active, T-MAU selected. Refer Power
Savings Modes section descriptions various power down modes. three conditions listed above resets internal logic T-MAU places device into power down mode. this mode, Twisted-Pair driver pins (TXD±, TXP±) driven LOW, internal T-MAU status signals (LNKST, RCVPOL, XMT, COL) signals inactive. Once H_RESET ends, coma mode disabled, T-MAU selected. T-MAU will remain reset state Immediately after reset condition removed, T-MAU will forced into Link Fail state. T-MAU will move Link Pass state only after link beat pulses and/or single received message detected pair. snooze mode, T-MAU receive circuitry will remain enabled even while SLEEP driven LOW. T-MAU circuitry will always into power down mode H_RESET asserted, coma mode enabled, T-MAU selected. 10BASE-T Interface Connection Figure shows proper 10BASE-T network interface design. Refer Technical Manual (PID #18738A) more design details, refer Appendix list compatible 10BASE-T filter/ transformer modules. Note that recommended resistor values filter transformer modules same those used (Am79C980) IMR+ (Am79C981).
Filter Transformer Module 1.21 Filter
61.9 TXD+ TXP+ TXD422 61.9
RJ45 Connector
Am79C974
TXPRXD+ RXD-
Filter
18681A-25
Figure 10BASE-T Interface Connection
Am79C974
PRELIMINARY Link beat pulses transmitted during snooze mode. output active when SLEEP asserted, then Am79C974 controller will wait until input asserted. Next, Am79C974 controller will deassert finally, will internally enter either coma snooze sleep mode. Before sleep mode invoked, Am79C974 controller will perform internal S_RESET. This S_RESET operation will affect values registers configuration space. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay assertion SLEEP until three cycles after completion valid operation.
Ethernet Power Savings Modes
Am79C974's Ethernet controller supports hardware power savings modes. Both entered driving SLEEP LOW. interface section effected SLEEP. particular, access configuration space remains possible. None configuration registers will reset SLEEP. accesses Am79C974's Ethernet controller will result target abort response. first power saving mode called coma mode. coma mode, Am79C974 controller means network automatically wake itself Coma mode enabled when AWAKE BCR2 reset. Coma mode default power down mode. second power saving mode called snooze mode. snooze mode, enabled setting AWAKE BCR2 driving SLEEP LOW, T-MAU receive circuitry will remain enabled even while SLEEP driven LOW. LNKST output only pins that continues function. LNKSTE must BCR4 enable indication good 10BASE-T link there link beat pulses valid frames present. This LNKST used drive and/or external hardware that directly controls SLEEP Am79C974 controller. This configuration effectively wakes system when there activity 10BASE-T link. Snooze mode used only T-MAU selected network port.
Software Access
Ethernet Configuration Registers Am79C974 controller supports 64-byte header portion configuration space predefined specification revision 2.0. None device specific registers locations used Ethernet controller. layout configuration registers header region shown table below. registers required identify Am79C974 controller function implemented. Additional registers used setup configuration Am79C974 controller system.
Am79C974
Device Status Base-Class Reserved Sub-Class Header Type Programming Latency Timer Base Address Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Interrupt Interrupt Line
Offset Revision Reserved
Vendor Command
configuration registers accessible only configuration cycles. They accessed right after Am79C974 controller powered-on, even read operation serial EEPROM still on-going. multi-byte numeric fields follow little endian byte ordering. Command register only register cleared H_RESET. S_RESET well asserting SLEEP have effect value configuration registers. write accesses Reserved locations have effect, reads from these locations will return data value ZERO. When Am79C974 controller samples IDSELA IDSELB input asserted during configuration cycle, will acknowledge cycle asserting DEVSEL output. content AD[31:00] during address phase configuration cycles must meet format shown below:
device. Am79C974 controller functions single function devices, indicated Header Type registers both configuration spaces (bit FUNCT Therefore, Am79C974 controller ignores AD[10:8] during address phase configuration cycle. AD[31:11] typically used generate IDSELA IDSELB signals. Am79C974 controller ignores upper address bits. configuration registers accessed with 8-bit, 16-bit 32-bit transfers. active bytes within DWORD determined byte enable signals. E.G. read Sub-Class register performed reading from offset with only being active. Resources Am79C974 controller uses separate blocks space, SCSI controller Ethernet controller. This section discusses address block used Ethernet controller. PCnet-SCSI's Ethernet Controller Resource Mapping Am79C974's Ethernet controller several resources. These resources bytes space that begin Am79C974's Ethernet controller base address. Ethernet controller allows modes slave access. Word mode treats Ethernet controller Resources two-byte entities spaced two-byte address intervals. Double Word mode treats Ethernet controller Resources four-byte entities spaced four-byte address intervals. selection DWIO mode accomplished several ways:
Don't Care
Don't Care
DWORD Index
AD[1:0] must both ZEROs, since Am79C974 controller bridge device. only recognizes configuration cycles Type defined specification revision 2.0). AD[7:2] specify selected DWORD configuration space. AD[7:6] must both ZERO, since Am79C974's Ethernet controller does implement device specific registers locations 255. Since AD[1:0] AD[7:6] must ZERO, lower bits address configuration cycle equal offset DWORD counting from beginning configuration space. AD[10:8] specify eight possible functions
Am79C974
H_RESET function.
PRELIMINARY DWIO mode setting unaffected S_RESET setting STOP bit.
EEPROM programming DWIO mode BCR18. Automatic determination DWIO mode DWORD (double-word) write access offset 10h. Ethernet controller mode setting will default after H_RESET (i.e. DWIO Following H_RESET operation, PREAD operation EEPROM will executed. EEPROM programmed with DWIO position EEPROM checksum correct, then EEPROM read will result setting DWIO mode ONE. EEPROM programming absent, failed, contained ZERO DWIO position, then software invoke DWIO mode performing Double Word write a
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