Digital Subscriber Controller(DSCTM) Circuit DISTINCTIVE CHARACTE
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Am79C30A/32A
Digital Subscriber Controller(DSCTM) Circuit
DISTINCTIVE CHARACTERISTICS
Combines CCITT I.430 S/T-Interface Transceiver, D-Channel LAPD Processor, Audio Processor (DSC device only), IOM-2 Interface single chip Special operating modes allow realization CCITT I.430 power-compliant terminal equipment T-Interface Transceiver Level Physical Layer Controller Supports point-to-point, short extended passive configurations Provides multiframe support Certified protocol software support available CMOS technology, compatible D-channel processing capability Flag generation/detection generation/checking Zero insertion/deletion Four 2-byte address detectors 32-byte receive 16-byte transmit FIFOs
BLOCK DIAGRAM
SBP/IOM-2 Interface CAP1 CAP2 SBIN SCLK BCL/CH2STRB* SBIOUT
AINA AREF AINB EAR1 EAR2
Audio Interface
Main Audio Processor (MAP) (Am79C30A Only)
Peripheral Port (PP)
Line Interface Unit (LIU) Channel
LOUT1 LOUT2 LIN1 LIN2
B-channel Multiplexer (MUX)
D-Channel Data Link Controller (DLC)
XTAL1 XTAL2 MCLK
Oscillator (OSC)
Channel Microprocessor Interface (MUX) RESET
Microprocessor Interface
09893H-1
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
Publication# 09893 Rev: Amendment/0 Issue Date: December 1998
Interface
DISTINCTIVE CHARACTERISTICS (continued)
Audio processing capability (DSC circuit only) Registers implementation software-based speaker phone algorithms Dual audio inputs Earpiece loudspeaker drivers Codec/filter with selection Programmable gain equalization filters Programmable sidetone level Programmable DTMF, single tone, progress tone, ringer tone generation Programmable on-chip microphone amplifier software compatible with Am79C32A ISDN Data Controller (IDCTM) Circuit. Am79C32A used data-only applications.
GENERAL DESCRIPTION
Am79C30A Digital Subscriber Controller (DSC) Circuit Am79C32A ISDN Data Controller (IDC) Circuit, shown Block Diagram, allow realization highly-integrated Terminal Equipment ISDN. Am79C30A/32A fully compatible with CCITT-I-series recommendations reference points, ensuring that user device design which conform international standards. Am79C30A/32A provides 192-Kbit/s full duplex digital path over four wires between located subscriber's premises PABX linecard. physical layer functions procedures implemented accordance with CCITT Recommendation I.430, including framing, synchronization, maintenance, multiple minal contention. Both point-to-point point-to-multipoint configurations supported. Am79C30A/32A processes ISDN basic rate stream, which consists Kbit/s), Kbit/s), Kbit/s) channels. channels routed from different sections Am79C30A/32A under software control. channel partially processed DSC/IDC circuit passed microprocessor further processing. Main Audio Processor (MAP) uses Digital Signal Processing (DSP) implement high performance codec/filter function. interface supports loudspeaker, earpiece, separate audio inputs. Programmable on-chip gain provided simplify output level microphones. user alter frequency response gain receive transmit paths. Tone generators included implement ringing, call progress, DTMF signals. Peripheral Port (PP) provided allow channels routed off-chip processing other peripherals. This configurable either industry-standard IOM-2 port, serial port (SBP). design process simplified availability certified protocol software packages, which provide complete system solutions through Layer
Am79C30A/32A Data Sheet
CONNECTION DIAGRAMS View
44-Pin PLCC AREF EAR2 EAR1 AINB AINA AVSS Am79C30A LIN1 LIN2
CAP1 CAP2 AVCC RESET
LOUT1 LOUT2 AVSS XTAL1 XTAL2 MCLK SCLK SBOUT
BCL/CH2STRB
44-Pin PLCC RSRVD RSRVD RSRVD RSRVD RSRVD AREF Am79C32A LIN1 LIN2
RSRVD RSRVD AVCC RESET
SBIN
LOUT1 LOUT2 AVSS XTAL1 XTAL2 MCLK SCLK SBOUT
BCL/CH2STRB
Note: marked orientation purposes.
RSRVD Reserved pin; should connected externally signal supply.
Am79C30A/32A Data Sheet
SBIN
CONNECTION DIAGRAMS (continued) View
44-Pin TQFP AREF EAR2 EAR1 AINB AINA AVSS LIN1 LIN2
CAP1 CAP2 AVCC RESET
Am79C30A
LOUT1 LOUT2 AVSS DVSS XTAL1 XTAL2 MCLK SCLK SBOUT
BCL/CH2STRB
44-Pin TQFP RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD Am79C32A LIN1 LIN2
RSRVD RSRVD AVCC RESET
SBIN
LOUT1 LOUT2 AVSS DVSS XTAL1 XTAL2 MCLK SCLK SBOUT
BCL/CH2STRB
Note: marked orientation purposes.
Am79C30A/32A Data Sheet
SBIN
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
AM79C30A/32A
OPTIONAL PROCESSING Blank Standard Processing
TEMPERATURE RANGE Commercial (0°C +70°C)
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044) 44-Pin Thin Plastic Quad Flat Pack (PQT044)
SPEED OPTION Applicable DEVICE NAME/DESCRIPTION Am79C30A/32A Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device
Valid Combinations AM79C30A AM79C32A
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Reference Appendix Figures specific mechanical dimensions packages.
Am79C30A/32A Data Sheet
DESCRIPTION* Line Interface Unit (LIU)
Hook-Switch (Input) signal indicates hook-switch hook. This signal generated with mechanical switch wired ground with pull-up resistor VCC. change state causes interrupt. LIN1, LIN2 Subscriber Line Input (Differential Inputs) LIN1 LIN2 inputs interface subscriber reference point) isolation transformer. LIN2 positive input; LIN1 negative input. These pins compatible. LOUT1, LOUT2 Subscriber Line Output (Differential Outputs) LOUT1 LOUT2 line driver output signals interface subscriber line reference point isolation transformer resistors. LOUT2 positive S-interface driver (sources current during High mark), LOUT1 negative S-interface iver multi-point applications, must maintain same polarity Interface. These pins compatible.
EAR1, EAR2 Earpiece Interface (Differential Outputs) EAR1 EAR2 outputs from receive path codec/filter. These differential outputs directly drive minimum load ohms. LS1, Loudspeaker Interface (Differential Outputs) push-pull outputs which directly drive minimum load ohms.
Microprocessor Interface (MPI)
A2-A0 Address Line (Inputs) signals select source destination registers read write operations data bus. Chip Select (Input) must read write Am79C30A/ 32A. Data transfer occurs over bidirectional data lines (D7-D0). D7-D0 Data (Bidirectional with High-Impedance State) eight bidirectional data lines used exchange information with microprocessor. least significant (LSB) most significant (MSB). High data line corresponds logic corresponds logic These lines inputs when both active outputs when both active. When inactive both inactive, D7-D0 pins high-impedance state. Interrupt (Output) active output informs external microprocessor that Am79C30A/32A needs interrupt service. updated once every remains active until Interrupt Register (IR) read Am79C30A/32A reset. RESET Reset (Input) Reset active High signal which causes Am79C30A/32A immediately terminate present activity initialize reset condition. When reset returns Low, Am79C30A/32A enters Idle mode. MCLK output remains active while RESET held High.
Main Audio Processor (MAP)
pins analog, therefore compatible. AINA, AINB Analog (Inputs) These analog inputs allow separate analog (audio) inputs transmit path codec/filter.Input signals either these pins must referenced AREF. AREF Analog Reference (Output) This nominal 2.25-V reference voltage output biasing analog inputs. When disabled, this high impedance. CAP1, CAP2 Capacitor/Resistor (CAP1, Input; CAP2, Output) external resistor capacitor connected series between these pins. These components needed integrator Analog-to-Digital Converter (ADC).
Note: signal levels compatible unless otherwise stated.
Am79C30A/32A Data Sheet
Read (Input) active read signal conditioned indicates that internal information transferred onto data bus. number internal registers user accessible. contents accessed register transferred onto data after High transition input. Write (Input) active write signal conditioned indicates that external information data transferred internal register. contents data loaded High transition input.
Peripheral Port programmed IOM-2 mode, SBOUT functions data output except special case IOM-2 Slave mode when becomes input during part IOM-2 frame. SCLK Serial Data Clock (Input/Output) When programmed mode, SCLK outputs 192-kHz data clock, which inverted under software control. When programmed IOM-2 Master mode, SCLK outputs 1.536-MHz data clock. IOM-2 Slave mode, SCLK functions clock input. SCLK defaults high-impedance state upon reset, becomes active after connection made programmed IOM-2 Master mode. Serial Frame Sync (Input/Output) mode, outputs 8-kHz frame synchronization signal. output IOM-2 Master mode, input IOM-2 Slave mode. output, active 8-bit periods. defaults high-impedance state upon reset, becomes active after connection made programmed IOM-2 Master mode. mode, active signal state during Idle Active Data Only Active Voice Data modes. BCL/CH2STRB Clock/SBP Channel Strobe (Output, Three-state) mode, this provides strobe during 8-bit times second 64-kbit/s data channel. IOM-2 Master mode, this provides 768-kHz clock connection non-IOM-2 devices port. IOM-2 Slave mode, this high-impedance.
Oscillator (OSC)
MCLK Master Clock (Output) MCLK output available system clock microprocessor. MCLK derived from 12.288-MHz crystal programmable divider Am79C30A/32A which provides following MCLK output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536, 0.768, 0.384 MHz. XTAL1, XTAL2 External Crystal (Output, Input) XTAL1 XTAL2 connected external parallel resonant crystal on-chip oscillator. XTAL2 also connected external source instead crystal, which case XTAL1 should left disconnected. frequency must 12.288 MHz, ppm.
Peripheral Port (PP)
SBIN Serial Data (Input/Output) When Peripheral Port programmed mode, SBIN operates input serial data. When Peripheral Port programmed IOM-2 mode, SBIN functions data input except special case IOM-2 Slave mode, when becomes open-drain output during part IOM-2 frame, when deactivated. SBOUT Serial Data (Input/Output) When Peripheral Port programmed mode, SBOUT operates output serial data. When
Power Supply Pins
PLCC/TQFP Packages AVCC AVSS DVSS DVCC +5-V analog power supply, Analog ground Digital ground +5-V digital power supply,
Note: best performance, decoupling capacitors should installed between close chip possible. separate supplies analog digital power ground connections.
Am79C30A/32A Data Sheet
OPERATIONAL DESCRIPTION Overview Power Modes
minimization power consumption factor design Terminal Equipment ISDN, DSC/IDC circuit employs basic approaches power management: power consumption DSC/IDC circuit itself managed using four basic power modes which allow unused functional blocks disabled. INIT register programmed select Active Voice Data, Active Data Only, Idle, Power-Down mode, depending upon which DSC/ device resources required time. power consumption controlling micro-processor system controlled driving processor clock with DSC/IDC circuit MCLK output. wide range MCLK operating frequencies selected, special Clock Speed-Up function provided which increases speed MCLK upon occurrence event, without processor intervention. Control MCLK frequency Clock Speed-up accomplished programming INIT INIT2 registers, described later.
Idle mode reduces DSC/IDC circuit power consumption disabling MUX, DLC, functional blocks. Peripheral Port also disabled, except that IOM-2 activation request interrupt possible, SCLK outputs still activated. SCLK outputs high impedance upon RESET, become active after connection programmed. read-only registers cleared when DSC/IDC circuit enters Idle mode.
Power-Down Mode
Power-Down mode consumes least power DSC/IDC power options, differs from Idle mode that clocks, including XTAL oscillator, stopped. Most functional blocks disabled, except those required recognize external events that will force DSC/IDC circuit return Idle mode. Power-Down mode available unless Power-Down Enable INIT2 register; INIT2 register description further details. Entering Power-Down Mode Power-Down mode entered appropriate programming INIT INIT2 registers. Selection Power-Down mode causes DSC/IDCcircuit begin internal countdown least MCLK cycles after which MCLK XTAL1 outputs both stopped held High, XTAL2input will disregarded. purpose this countdown cycle allow microprocessor time housekeeping operations before clock stopped. interrupt causes during countdown, Power-Down mode bits INIT register will reset countdown will canceled. enabled state other than countdown, MCLK stopped oscillator continues run. This allows identify incoming signal either generate interrupt force DSC/IDC circuit Idle mode when activation complete, move state stop oscillator once line goes idle. Exiting Power-Down Mode DSC/IDC circuit will exit Power-Down mode enter Idle mode following events occur: DSC/IDC circuit receives hardware reset RESET pin. pins both pulled same time, would occur during normal write operation from microprocessor circuit. data will transferred this operation. hookswitch changes state, hookswitch interrupt enabled.
Active Voice Data Mode
Active Voice Data mode functional blocks DSC/IDC circuit available. Device registers accessed through MPI, available, running, Peripheral Port available, connections made, Secondary Tone Ringer activated, operational (DSC circuit only).
Active Data Only Mode
Active Data Only mode similar Active Voice Data mode, except that (DSC circuit only) disabled reduce system power consumption. This increases amount power available Secondary Tone Ringer microprocessor system during phases call setup teardown, during data-only telephone call.
Idle Mode
Idle mode RESET default mode DSC/IDCcircuit operation, represents operational state which power consumption reduced, microprocessor system operational program DSC/IDC circuit registers perform other required background tasks. Idle mode also entered appropriate programming INIT register. Idle mode, MCLK output available drive microprocessor system, available programming DSC/IDC registers, available initiate respond interface activity. hookswitch interrupt also available Idle mode.
Am79C30A/32A Data Sheet
receiver enabled, detects incoming signal Interface, achieves activation indicated transition state Both transition interrupt must enabled Power-Down mode exited. enabled, restart oscillator that identify activity interface. activity determined noise, will stop oscillator continue monitor line without interrupt returning Idle mode. IOM-2 Interface enabled clock master SBIN input goes Low. This indicates that slave device wants activate IOM-2 Interface communicate with circuit. Both IOM-2 timing request interrupts must enabled Power-Down mode exited. IOM-2 Interface enabled clock slave SCLK input goes High. This indicates that master device activating IOM-2 Interface circuit must wake order monitor data. Both IOM-2 timing request interrupts must enabled Power-Down mode exited.
There events that will trigger clock speed-up function: receive FIFO threshold been reached; second packet begins received while data from prior packet still receive FIFO. second packet case requires provision interrupt; register section further information. clock speed-up function allows user program very slow MCLK frequency using INIT2 when D-channel activity minimal. burst activity seen channel exceeds programmed threshold receive FIFO threatens overrun receive FIFO status buffers, MCLK will instantly toggle back higher frequency programmed INIT register. This eliminates latency incurred interrupt serviced change clock speed, allows overall system power reduced during typical voice connections. Note that automatic clock speed-up will function unless least associated interrupts enabled processor informed that clock speed been altered.
DSC/IDC circuit awakened condition other than RESET, MCLK output will restored previously programmed frequency, will generate shortened spurious output cycles. DSC/IDC circuit revived RESET, MCLK will default normal 6.144-MHz rate. DSC/IDC circuit provides minimum MCLK cycles prior activating interrupt when exiting Power-Down mode.
Global Register Functions
INIT Register (INIT) default Address Indirect Hex, Read/Write
Table
INIT Register
MCLK Frequency Control
MCLK frequency selection bits INIT register unchanged from Revision However, additional MCLK frequencies available programming bits INIT2 register. shortened spurious clock pulses that might disrupt external microprocessor will result when MCLK frequency changed. order reduce probability errant software disrupting system operation, INIT2 register requires consecutive writes before value will entered into register. Note that there will MCLK countdown case entering Power-Down mode INIT2 programmed cause MCLK STOP, there will shortened spurious MCLK pulses.
Function Idle mode Active Voice Data mode Active Data Only mode Power-Down mode
output enabled output disabled MCLK frequency 6.144 MCLK frequency 12.288 MCLK frequency 3,072 MCLK frequency 6.144 MCLK frequency 4.096 MCLK frequency 6.144 MCLK frequency 6.144 MCLK frequency 6.144
MCLK Clock Speed-up Function
programmable automatic MCLK speed-up option provided that will force hardware reset INIT2 bits 3-0, which will cause MCLK frequency restored value programmed INIT register.
receiver abort disabled receiver abort enabled transmitter abort disabled transmitter abort enabled
Am79C30A/32A Data Sheet
INIT2 Register (INIT2) default Address Indirect Hex, Read/Write special write procedure must followed order modify contents INIT2 Register, since INIT2 Register includes control bits which could result stopping microprocessor clock. This procedure greatly reduces probability errant software disabling system, described follows: Write INIT2 address Command Register. Write Data Register (INIT2 updated). Write INIT2 address Command Register. Write Data Register (INIT2 updated). writes must take place without intervening indirect accesses DSC/IDC circuit.
RESET Operation
Am79C30A/32A reset driving RESET High. When power first supplied DSC/IDC circuit, reset must performed. This initializes DSC/IDC circuit default condition defined Table
Table
Name D7-D0 MCLK SBOUT SCLK
Reset Conditions
State Following RESET High Impedance 6.144 Logical High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance
Table
INIT2 Register
Function
LS1, EAR1 EAR2 AREF LOUT1 LOUT2
Reserved, must written READs undefined Power-Down disabled; writing INIT Register will DSC/IDC circuit into Idle mode Power-Down enabled; writing INIT Register will DSC/IDC circuit into Power-Down mode Multiframe Interrupt filter disabled Multiframe Interrupt filter enabled (see section detailed description) Clock speed-up option disabled Clock speed-up option enabled; set, this register will cleared when FIFO receive threshold second packet received interrupt triggered MCLK frequency determined INIT Register MCLK frequency 1.536 MCLK frequency MCLK frequency MCLK stopped High state Reserved Reserved Reserved
Receive Transmit Abort Commands
microprocessor option INIT Register bits abort receive transmit D-channel packets. When microprocessor sets these bits, Am79C30A/32A aborts respective operation. frame abort sequence defined greater detail later. (See Data Link Controller section page 36.)
Interrupt Handling
Am79C30A/32A generates either interrupt only interrupt every Once asserted, remains active until microprocessor responds interrogating Am79C30A/32A's Interrupt Register (IR) (see Table Reading response activated deactivates clears event causing interrupt occurs while being read microprocessor, effect event held until microprocessor completed read cycle. reset clears conditions causing interrupts. Bits set, advise microprocessor that respective buffer ready reading writing. empty buffer, D-channel Transmit buffer must serviced within D-channel Receive buffer full, buffer must serviced within This prevent erroneous data transfers causing transmitter underrun receiver overrun errors. then
Am79C30A/32A Data Sheet
buffers must accessed within 122.4 This prevent erroneous data transfers. Only interrupt used signal accessibility both channels Interface. Since data transfer must occur synchronously Interface, data access either both must made within the122.4 limit. Note that even though only single interrupt issued, either both S-Interface channels must serviced. bits set, indicate that been associated status error register. interrupts generated Am79C30A/32A
individually disabled. case interrupt also masked setting PPIER DMR1, DMR2, DMR3, LMR2, MCR4, control mask conditions that affect pin. activated only interrupts that disabled. Interrupt Register reflects status enabled interrupts. disabled setting INIT Register logical Am79C30A/32A facilities that allow microprocessor read status registers (status update inhibited during status read) time during functional operation.
Am79C30A/32A Data Sheet
Table
Format Interrupt Register (IR), Read Only
Interrupt Mask DMR1 DMR1
Interrupt Generated/Action Required D-channel transmit threshold interrupt/load D-channel Transmit buffer D-channel receive threshold interrupt/read D-channel Receive buffer D-channel status interrupt/read DSR1 Source DSR1 DSR1 DSR1 Cause Valid Address (VA) Address (EOA) When closing flag received receive error occurs When closing flag transmitted DMR3 Cause Current received packet been aborted Non-integer number bytes received Collision abort detected error Overflow error Underflow error Overrun error Underrun error Receive packet lost
DMR3 DMR1 DMR3
D-channel error interrupt/read DSR2 Source DSR2 DMR2 DMR2 DMR2 DMR2 DMR2 DMR2 DMR2 DMR2 DMR3 MCR4
byte available buffer empty interrupt/read write buffers status interrupt/read Source Cause Change state Change state from/to Change state from/to change state Cause Last byte received packet Receive byte available Last byte transmitted Transmit buffer available Start second packet Cause S-data available Q-bit buffer empty Multiframe change state (in/out sync) Monitor receive, data available Monitor transmit, buffer available Monitor received Monitor abort received channel data change channel data change IOM-2 timing request
LMR2 LMR2 LMR2 LMR2
D-channel status interrupt/read DSR2 Source DSR2 DSR2 DSR2 DSR2 DSR2 DMR3 DMR3 DMR3 DMR3 EFCR
Multiframe interrupt/read MFSB PPSR Source MFSB MFSB MFSB PPSR PPSR PPSR PPSR PPSR PPSR PPSR PPIER PPIER PPIER PPIER PPIER PPIER PPIER
Am79C30A/32A Data Sheet
FUNCTIONAL DESCRIPTION Microprocessor Interface (MPI)
Am79C30A/32A connected general purpose 8-bit microprocessor MPI. MCLK from Am79C30A/32A used clock microprocessor. interrupt-driven interface containing circuitry necessary access internal programmable registers, status registers, coefficient RAM, transmit/receive buffers. External Interface External connections shown Table
Direct Registers
Access Direct Registers Am79C30A/32A controlled state input pins, defined below Table
Indirect Registers
read from write Indirect Registers, indirect address command first written Command Register (CR). more data bytes then transferred from selected register through Data Register (DR). Registers within certain groups accessed quickly using internal circuitry which automatically increments indirect value. Table bytes transferred numbers number bytes which read written after been loaded. Whenever loaded, previous commands automatically terminated.
Table
Name D7-D0 A2-A0 RESET
External Interface
Function Data Address Line Read Enable Write Enable Chip Select Initialization Interrupt
Direction Bidirectional Inputs Input Input Input Input Output
Table
Direct Register Access Guide
Mode
Register(s) Accessed Command Register (CR) Interrupt Register (IR) Data Register (DR) Data Register (DR) D-channel Status Register (DSR1) D-channel Error Register (DER) (2-byte FIFO) D-channel Transmit buffer (DCTB) 16-byte FIFO) D-channel Receive buffer (DCRB) 32-byte FIFO) Bb-channel Transmit buffer (BBTB) Bb-channel Receive buffer (BBRB) Bc-channel Transmit buffer (BCTB) Bc-channel Receive buffer (BCRB) D-channel Status Register (DSR2) access logical
Note: signals must never both under normal operating conditions.
Am79C30A/32A Data Sheet
Table
Operation Block Register INIT INIT Initialization Register Initialization Register Status Register Priority Register Mode Register Mode Register Multiframe Register Multiframe S-bit/Status Register Multiframe Q-bit buffer Control Register Control Register Control Register Control Register filter Coefficient Register filter Coefficient Register Gain Coefficient Register Gain Coefficient Register Gain Coefficient Register Sidetone Gain Coefficient Register Frequency Tone Generator Register Amplitude Tone Generator Register Mode Register Mode Register Mode Register Secondary Tone Ringer Amplitude Secondary Tone Ringer Frequency Transmit Peak Register Receive Peak Register First Received Byte Address Registers Second Received Byte Address Registers Transmit Address Register D-channel Receive Byte Limit Register D-channel Transmit Byte Count Register
Indirect Register Access Guide
Register Number Indirect Name INIT INIT2 LMR1 LMR2 Perform MFSB MFQB MCR1 MCR2 MCR3 MCR4 Perform Coeff. Coeff. Coeff. Coeff. Coeff. Coeff. FTGR1, FTGR2 ATGR1,ATGR2 MMR1 MMR2 Perform 1-10 MMR3 STRA STRF PEAKX PEAKR Perform 15-16 FRAR SRAR1, DRLR DTCR Mode Address byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred MCR1, LSB, MSB.h7 LSB, MSB.h7 LSB, LSB, LSB, LSB, FTGR1, ATGR1, byte transferred byte transferred bytes loaded 1-10 byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred FRAR1, SRAR1, LSB, LSB, LSB, Byte Sequence byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred
Am79C30A/32A Data Sheet
Table
Operation Block Register D-channel Mode Register D-channel Mode Register
Indirect Register Access Guide (Continued)
Register Number Indirect Name DMR1 DMR2 Perform DRCR RNGR1 (LSB) RNGR2 (MSB) FRAR4 SRAR4 DMR3 DMR4 Perform 12-15 EFCR PPCR1 PPSR PPIER MTDR MRDR CITDR0 CIRDR0 CITDR1 CIRDR1 PPCR2 PPCR3 Mode Address Byte Sequence byte transferred byte transferred bytes loaded LSB, byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred FRAR4, SRAR4, DMR3, DMR4 byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred byte transferred
D-channel Receive Byte Count Register Random Number Generator Register Random Number Generator Register First Received Byte Address Register Second Received Byte Address Register D-channel Mode Register D-channel Mode Register Address Status Register Extended FIFO Control Register Peripheral Port Control Register Peripheral Port Status Register Peripheral Port Interrupt Enable Register Monitor Transmit Data Register Monitor Receive Data Register Transmit Data Register Receive Data Register Transmit Data Register Receive Data Register Peripheral Port Control Register Peripheral Port Control Register
Line Interface Unit (LIU)
connects four-wire Interface through pair isolation transformers, transmit receive direction, shown Figure receiver section consists differential receiver, circuitry timing recovery, circuitry detecting High marks, frame recovery circuit frame synchronization. receiver converts received pseudo-ternary coded signals binary before delivering them other blocks Am79C30A/32A. also performs collision detection (Eand D-bit comparison) CCITT recommenda-
tions several connected same Interface. transmitter consists binary pseudo-ternary encoder differential line driver which meets CCITT recommendations Interface. Am79C30A/32A establish multiframe synchronization, receive bits, transmit bits synchronized received frame. External Interface connected both point-to-point point-to-multipoint configurations CCITT reference point. point-to-point configuration consists connected PABX linecard.
Am79C30A/32A Data Sheet
point-to-multipoint configuration have multiple connected Line Code Pseudo-ternary coding used both transmitting receiving over Interface. this type coding, binary represented space (zero voltage), binary represented High mark mark. consecutive binary represented alternate marks reduce offset line. mark followed, either immediately separated spaces, mark same polarity, defined code violation. Code violations used identify boundaries frame.
Note: defines "Any Signal" frame with least three marks above receive threshold.
(bit Multiframe Register) multiframe change state (bit Multiframe bit/Status buffer) set. Note that S-bit data received, compiled, transferred user after attaining synchronization start next multiframe. S-Bit Reception default operation DSC/IDC circuit that will receive pass multiframe data user 5-bit increments four times multiframe, regardless value data. After multiframe synchronization been requested established microprocessor read Multiframe bit/Status buffer (MFSB) once S-bit available (MFSB set. S-data available logical when Am79C30A/32A received five bits (one S-interface frame) synchronized setting -bit logical transferred them into MFSB. Once S-bit available set, MFSB must accessed within 1.25 succeeding data will lost. Subsequent original definition DSC/IDC circuit, CCITT defined structure multiframe bits, which specifies five 4-bit channels. Furthermore, idle code these channels been defined 0000. enhanced mode multiframe reception been included, which enabled setting INIT2 This enhanced mode reduces processor overhead generating interrupt only upon reception non-zero S-channel word. INIT2 will automatically cleared hardware when five received data bits MFSB long (interrupt enable) set. This allows subsequent valid all-zero words received. Furthermore, when first five bits multiframe loaded into MFSB, register will set, which allows identification position received words within multiframe.
Frame Structures both transmit receive directions, bits grouped into frames bits each. frame structure identical both point-to-point point-to-multipoint configurations. Each frame transmitted consists several groups bits. Multiframing multiframing enabled, Am79C30A/32A recognizes establishes multiframe synchronization based monitoring (Q-bit control) (M-bit control) bits. Am79C30A/32A also receives compiles bits, transmits bits synchronized received frame. Establishment Multiframe Synchronization When enable multiframe synchronization (bit Multiframe Register) either state monitors (Q-bit control) (M-bit control) bits. When three consecutive multiframes with bits bits defined Table received, multiframe synchronized
Line Drivers Binary Pseudo-ternary Coder
Decoder
Frame Recovery
Slicer Timing Recovery Balanced Receiver
09893H-2
Figure
Block Diagram
Am79C30A/32A Data Sheet
Table
Frame Number etc. NT-to-TE Control
Multiframing Structures
NT-to-TE NT-to-TE SC11 SC21 SC31 SC41 SC51 SC12 SC22 SC32 SC42 SC52 SC13 SC23 SC33 SC43 SC53 SC14 SC24 SC34 SC44 SC54 SC11 SC21 TE-to-NT Bit)
Transmission bits microprocessor load Multiframe Q-bit buffer (MFQB) once Q-bit buffer empty (bit Multiframe bit/Status buffer) set. Q-bit buffer empty logical reset when data that been written Multiframe Q-bit buffer transferred LIU. Q-bit buffer empty cleared logical when Multiframe S-bit/Status buffer read. After multiframing been requested established, Am79C30A/32A transfers data written into Q-bit Register LIU, synchronized multiframe, irrespective receipt valid Q-control bits. microprocessor does reload Q-bit Register retransmissions, Q-bit pattern repeated next multiframe. multiframing enabled multiframe synchronization established, transmits value loaded MFQB bits. default value MFQB logical which satisfies CCITT recommendations. When synchronization achieved, contents MFQB bits transmitted according Table
Loss Multiframe Synchronization Am79C30A/32A continuously monitors (Q-bit control) bits ensure multiframe synchronization. Once multiframe synchronization established, multiframe synchronization lost three consecutive invalid multiframes received, longer state multiframing disabled. When loss multiframe synchronization occurs, Multiframe Register logical Multiframe bit/Status buffer logical Am79C30A/32A also terminates reception bits transmission bits until multiframing synchronization re-established.
hookswitch circuitry circuit provides attached microprocessor with converting external mechanical hookswitch into software status condition capable generating interrupt. Debounce glitch rejection provided internal circuit. logic rejects glitches less than provides debounce status reporting disabled after RESET. enabled following: taking device Idle mode, write Control Register (MCR3-MCR1), unmasking interrupt.
Am79C30A/32A Data Sheet
Registers contains registers shown Table
Table
Registers Status Register Priority Register Mode Registers Multiframe Register Multiframe S-bit/Status Register Multiframe Q-bit buffer
Registers
No./Registers Mnemonic LMR1, LMR2 MFSB MFQB
where LSB. interrupts microprocessor when activation been achieved (that when moves state upon receipt INFO During reset Even thou Status iste read-only, default value upon power-up given uncertain state (Hookswitch State). Following RESET, State reflects pin, producing power-up value either 40H. D-Channel Priority Register (LPR), Read/Write contains priority level D-channel access. default value after reset D-channel access procedure Am79C30A/ uses priority level programmed LPR. priority mechanism defined CCITT I-series recommendations fully implemented programmed microprocessor conform priority class Layer-2 frame transmitted.The possible programmable priority levels. priority levels numbered 0-15. Priority Level corresponds counting eight echo channel, priority Level corresponds counting echo channel, priority Level corresponds counting twelve etc. circuit automatically handles transitions between programmed priority level associated value priority incremented following successfully transmitted packet, decremented when higher count been satisfied. format shown Table
Status Register (LSR), Read Only Address Indirect format shown Table
Table
Status Register
Generates Interrupt
Logical Binary values through represent activation circuitry's current state through respectively) Change state Change state from/to Change state from/to state change state
LMR2 LMR2 LMR2 LMR2
Table
Bits
Priority Register
Description
When microprocessor reads LSR, bits cleared. other bits retain current status LIU. bits defined such that state (see CCITT I.430 state matrix tables) coded
D-channel access priority level Reserved, reads logical
Am79C30A/32A Data Sheet
Mode Register (LMR1), Read/Write Address Indirect LMR1 defined Table
Table
Logical Enable transmit Enable transmit Disable transmit Disable transmit Activation request from Enable receiver/transmitter Reserved; must logical
Mode Register
Logical (default value) Disable transmit Disable transmit Enable transmit Enable transmit activation request transition Disable receiver/transmitter Reserved; must logical
Notes: bits LMR1 (bits should enabled during activation procedure Am79C30A/32A respond with INFO LMR1 used transfer signals PH-AR Expiry Timer from microprocessor (see CCITT I.430 state diagram-activation request). PH-AR defined being logical Expiry Timer defined transition from logical logical This must until LIU, reflected LSR, state receiver been enabled minimum LMR1 primarily used disable receiver when terminal does require access Interface signals. This cleared reset must written logical order receive activation from Interface, request activation.
Mode Register (LMR2), Read/Write Address Indirect LMR2 used select operations found Table
Table
Logical
Mode Register
Logical (Default Value) D-channel loopback Am79C30A/32A disable D-channel loopback disable D-channel back-off enable change state interrupt disable change state interrupt disable interrupt disable change state interrupt disable Reserved; must logical
D-channel loopback Am79C30A/32A enable D-channel loopback enable D-channel back-off disable change state interrupt enable change state interrupt enable interrupt enable change state interrupt enable Reserved; must logical
Am79C30A/32A Data Sheet
three D-channel loopback controls defined LMR2 bits explained below: D-channel loopback Am79C30A/32A enable:
D-channel loopback enable: Am79C30A NT/PABX
Am79C30A
NT/PABX This local loopback provided local testing. Data incoming channel ignored. data from microprocessor processed then looped back microprocessor. D-channel back-off disable:
This remote loopback provided maintenance purposes from NT's perspective. transmits D-channel bits Am79C30A/32A where they internally looped (with Data Link Controller) transmitted back incoming D-channel data accessed microprocessor; however, microprocessor cannot send data outgoing channel. difference between transmitted D-channel bits Am79C30A/32A (normally detected error which halts transmission) ignored, thereby allowing transmission continue.
Am79C30A
NT/PABX
This loopback provided maintenance purposes from TE's perspective. Am79C30A/32A transmits D-channel bits where they looped transmitted back Am79C30A/32A channel. operation normal except differences between channels halt transmission.
Multiframe Register (MF), Read/Write Address Indirect Table
Logical Enable Multiframe sync Enable S-data available interrupt Enable Q-bit buffer empty interrupt Enable Multiframe change state interrupt First subframe used, reads logical Multiframe synchronized (read only)
Multiframe Register
Logical (Default Value) Disable Multiframe sync Disable interrupt Disable interrupt Disable interrupt first subframe used, reads logical Multiframe synchronized (read only)
Am79C30A/32A Data Sheet
Multiframe S-bit/Status Buffer (MFSB), Read Only Address Indirect
logical channels available shown Figure They are: From/to channels
Table
Multiframe S-Bit/Status Buffer
Generates Interrupt
From/to channel From/to channels From/to channels specific application, programmed microprocessor route three ports.Programmable bidirectional reversal provided both data channels Control Registers (MCR1, MCR2, MCR3), Read/Write Addresses Indirect 41H, 42H, support three bidirectional paths. contents Control Registers MCR1, MCR2, MCR3 direct flow data between eight logical channels (see Figure These three MCRs programmed connect B-channel ports together writing appropriate channel code into MCR. These MCRs have same format, where bits indicate port bits indicate port each these three registers, channel codes found Table used both ports
Description
S-data available Q-bit buffer empty
Multiframe change state
MFSB reset default value 40H. Multiframe Q-bit Buffer (MFQB), Write Only Address Indirect
Table
Multiframe Q-Bit Buffer
Description (default (default (default (default Q-bit value when multiframing enabled synchronization achieved (default used
Table
Code 0000 0001 0010
Register Channel Codes
Channel connection (default value) (LIU) (LIU) (MAP) (MPI) (MPI) channel channel channel
Multiplexer (MUX)
contains registers found Table
0011 0100 0101
Table
Register Control Registers
Registers
Mnemonic MCR1, MCR2, MCR3, MCR4
0110 0111 1000
No./Registers
Multiplexer used selectively route 64-Kbit/s full-duplex channels between (Line Interface Unit), (Main Audio Processor), (Microprocessor Interface), (Peripheral Port).
example, connect B1(LIU) with (MPI) (LIU) with (MAP), contents MCRs would Port Port
Register Channel Connection MCR1 MCR2 MCR3 (LIU) (LIU) connect (MPI) (MAP) connect
Am79C30A/32A Data Sheet
Peripheral Port
B-channel
09893H-3
Figure
Logical Channels will overwrite data from connecting port lower priority MCR, example:
Port Port
Therefore, this example, MCR1 provides data link from Interface MCR2 sets voice connection across Interface. loopback channel, same channel code used port port example, loopback MCRs would
Port Port
Register Channel Connection MCR1 MCR2 MCR3 connect (LIU) (MPI) (MPI) (MAP)
Register Channel Connection MCR1 MCR2 MCR3 (LIU) Loopback (LIU) Loopback (MAP) Loopback
final data transfers are: (LIU) receives (MPI), (MAP) receives (MPI), (MPI) receives (MAP). Therefore, data transfer from (LIU) (MPI) lost arrangement proposed MCR2.
MCR3 higher priority than MCR2. MCR2 higher priority than MCR1. multiple connections made same port, data from connecting ports highest priority
Am79C30A/32A Data Sheet
Control Register (MCR4), Read/Write Address Indirect Control Register (MCR4) prevent interrupt generation masking output MCR4 format shown Table
Table
Logical Reserved, must logical
Control Register
Logical (Default Value) Reserved, must logical
Enable Bc-channel byte available interrupt Disable interrupt Reverse order (LSB transmitted/received first) Reverse order (LSB transmitted/received first) Reserved, must logical Reserved, must logical reversal (MSB transmitted/received first) reversal (MSB transmitted/received first) Reserved, must logical Reserved, must logical
Am79C30A/32A Data Sheet
Main Audio Processor (MAP)
(Am79C30A only) Overview MAP, illustrated Figure implements audio-band analog-to-digital (ADC) digital-to-analog (DAC) conversions together with wide variety audio support functions. Analog interfaces provided handset earpiece, handset mouthpiece, microphone, loudspeaker. programmable analog preamplifier included front converter. codec filter functions implemented using digital signal processing (DSP) techniques provide operational stability programmable features. There programmable digital gain stage transmit path receive path allow precise signal level control. Sidetone attenuation programmable, programmable equalization filters present both receive transmit paths order modify frequency response either both paths. Tone generation capability included allow generation ringing signals, DTMF tones, call progress signals. operation described detail following sections.
Audio Inputs audio input port consists inputs (AINA AINB) which selectable, time, register programming. Signals applied these inputs must AC-coupled. Earpiece Loudspeaker Drivers earpiece loudspeaker drivers each consist amplifiers with differential, low-impedance outputs. receive path signal routed either these outputs, both outputs simultaneously. Alternatively, receive path routed outputs while Secondary Tone Ringer (STR) routed outputs. drivers drive loads S130 ohms between EAR1 EAR2 pins, while drivers drive loads ohms between pins. maximum capacitive-loading between EAR1 EAR2 between outputs high-impedance when disabled. outputs high impedance when both Secondary Tone Ringer disabled.
CAP1 CAP2 AINA AINB AREF Analog Sidetone Gain* EAR1 EAR2
Notes: Minimum ASTG dB** dB** dB** dB** dB** Default Maximum
PEAKX Decimators, Digital Loopback DTMF GEN. Sidetone Gain* COMP* channel
Transmitter Receiver
Digital Loopback Interpolators, GER*
channel from EXP*
STR*
Step
PEAKR Tone* Ringer Tone* Gen.
*Programmable **These registers also programmed infinite attenuation break signal path desired.
09893H-4
Figure
Main Audio Processor Block Diagram
Am79C30A/32A Data Sheet
Programmable Analog Preamplifier programmable analog preamplifier included front converter adjustable 6-dB increments from existing gain stage transmit path used finer adjustment transmit gain. This preamplifier eliminates need external operational amplifier when interfacing electret-type handsets circuit. Analog Sidetone Analog sidetone takes analog input transmitter sums into single-ended input output buffer. summing point after output selection switch. analog sidetone path programmable attenuation between plus infinity (off). Default infinity. Programming four bits Extended FIFO Control Register, EFCR.6-3. programming values given Table
Receiver
receiver performs series operations described follows: expander converts input µ-law data digital linear data. most significant transferred from first. default value µ-law. filter programmable gain filter that allows user program gain 0.5-dB steps. default value Sidetone Gain (STG) programmable constant multipliers which allow user program gain 0.5-dB steps (default value 0.5-dB steps (default value respectively. provides volume control (for hearing impaired) should programmed normal operation. sidetone gain path provides feedback from transmitter. filter provided correct speaker attenuation distortion user-programmable filter similar filter transmitter. series interpolators increases sampling frequency. converts digital signal analog audio output signal. PEAK Hold Registers Logic form microprocessor accessible peak hold registers will provided allow support software based speaker phone solution. These registers, transmit path (PEAKX) receive path (PEAKR), will provide compressed maximum (peak) absolute value data path since register last read. With appropriate software, this used implement hands-free function. Refer block diagram location these registers processing path. following assumptions made: blocks used gain/attenuators, without modification their range resolution. data presented compressed A-law format, without alternate inversion. sign presented. data extraction point transmit path after filter. data extraction point receive path immediately following expander. compressed data from transmit receive paths presented using same compression algorithm.
Table
0000 0001 -27.0 0010 -25.5 0011 -24.0 1000 -16.5 1001 -15.0 1010 -13.5 1011 -12.0
Analog Sidetone
0100 -22.5 0101 -21.0 0110 -19.5 0111 -18.0 1100 -10.5 1101 -9.0 1110 -7.5 1111 -6.0
Signal Processing
Transmitter
transmitter performs series operations described below. converts incoming analog signal sampling rate kHz. Band Pass filter series decimators reject 60-Hz line frequencies while reducing sampling rate kHz. filter 8-tap user-programmable filter tuning microphone. default flat with unity gain. filter programmable gain filter that allows user program gain 0.5-dB steps. default value µ-law A-law digital compression algorithm converts linear output filter A-law code. default algorithm µ-law code. (sign bit) transferred first from) MUX.
Am79C30A/32A Data Sheet
peak registers double-buffered read asynchronously operation register. They cleared read. peak registers default "don't care" values when part reset. initial read operation required clear register before using first time. PEAKX register indirect address 70H, while PEAKR register indirect address 71H. Both accessed back-to-back read data register operations loading command register with 72H. Tone Generators contains three tone generators which enabled Mode Register bits Only three tone generator bits register time. more than set, three bits considered zero tone generation disabled. tone generators are:
DTMF generator used generate single frequency outputs. obtain single frequency DTMF generator, load zero code into frequency registers.
Tone Generation
This generator provides call progress tones receive path, where added incoming speech (Figure Block
Tone Ringer
This generator provides tone aler signals output through receive path loudspeaker earpiece (Figure Block program DTMF tone generators, frequency values amplitude values must written Frequ ency gisters (FTGR1, FTGR2) 8-bit Amplitude Tone Generator Registers (ATGR1, ATGR2), respectively. Tone Generator Tone Ringer frequency programmed FTGR1. Tone Generator uses amplitude programmed ATGR1 while Tone Ringer uses amplitude programmed ATGR2. Common frequency values listed Table FTGR codes obtain DTMF dialing output frequencies listed Table
DTMF Generator
This generator provides tone injection sampling rate into transmit sidetone paths (Figure Block DTMF frequencies generated guaranteed ±1.2% deviation.
Table
FTGR VALUE FTGR FREQ 1209
DTMF Codes
1336 1477 1633
Am79C30A/32A Data Sheet
output frequency DTMF tone generator approximately equals:
64000 DTMF Frequency -integer 8192
ATGR registers allow user program gain 2-dB steps. Example ATGR codes obtain amplitude gains listed Table implies level dBm0. gain values rounded nearest
where decimal equivalent value programmed into FTGR register. This allows DTMF generator supply common dual tone call progress signals such Busy Dial tones.
Table
Amplitude Gain Coefficients
Code
Gain (dB)
Table
Tone Ringer Tone Generator Frequency Coefficients
Code
Frequency (Hz) 2666 2000 1600 1333 1142 1000
Note: amendment Table following page 100.
Secondary Tone Ringer
Secondary Tone Ringer included, which able ring phone using outputs while voice conversation progress outputs. louder than Tone Generator, used with without enabling order provide flexible control system power consumption. available INIT register programmed Idle Power-Down mode. amplitude frequency square-wave output waveform programmable STRA STRF registers, respectively. both outputs from receive path simultaneously enabled, priority given connection. available both circuits. legal value must programmed STRF register before enabled.
Note: These coefficients apply DTMF generator.
Am79C30A/32A Data Sheet
Programmable Gain Coefficients GER, Sidetone gain coefficients each bits length. consecutive register locations correspond gain coefficient. transferred first from) microprocessor. Sample coefficients filter listed Table gain values rounded nearest Table
Code Gain (dB) -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 Gain (dB) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.4 14.0 14.5 15.0 15.5 15.9 16.6 16.9 17.5 18.0
Gain Coefficients
Code
Note: coefficient 0008 provides attenuation infinity when gain enabled.
Am79C30A/32A Data Sheet
Example coefficients filters listed Tables gain values rounded nearest
Table
Gain (dB) -11.5
Gain Coefficients
Code
Table
Gain (dB) 10.0 10.5 11.0 11.5 12.0
Gain Coefficients
Code
-11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5
Am79C30A/32A Data Sheet
Table
Gain (dB) -18.0 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5
Gain Coefficients
Code
Overflow/Underflow Precautions When Using Programmable Gains Care must taken that point signal processing path, combination gains filters and/or tones does result signal that larger than full scale. Full scale defined digital representation maximum analog signal that allowed into transmitter receiver with filters gain stages their default settings (e.g., A-Law, transmitter full scale ±1.25 receiver full scale ±2.5 VP). Likewise, desirable that peak signal kept close full scale possible point signal processing path order minimize digital truncation effects A/D, D/A, DSP. Consider following example: programmed infinite attenuation, programmed while programmed filter programmed exhibit gain Assume analog full scale receiver full scale code possible from MUX. After equivalent analog signal will ±1.25 However, after signal will 1.25 Even though filter will have gain signal will clipped after distorted codes between full scale below full scale intermediate result output GER. very careful when programming tone ringers/generators. example, DTMF tones programmed tone generated that equivalent full scale signal transmit path. This means headroom left other DTMF tone. Therefore, DTMF generator should never programmed exceed full scale signal quality maintained. receive path, similar caution should exercised order prevent combination Tone Generator, Sidetone, from clipping signal. Extended Programming Ranges Some applications will require greater flexibility programming MAP's internal gain attenuation blocks. example, applications such software-based hands-free utilizing PEAKX PEAKR registers need attenuation well gain within transmit path. preceding gain tables specifically detail this capability, implementation these gain filter blocks, capable performance beyond these recommended ranges. ASTG implemented limited their stated range step size.) Table lists guaranteed ranges, while Table shows limits design.
Note: coefficient 9008 provides attenuation infinity when and/or enabled.
Am79C30A/32A Data Sheet
Table
Recommended Ranges
Recommended guaranteed plus infinite steps plus infinite steps plus infinite steps plus infinite steps
where each Coefficient Register pair following format:
Byte
(i=0,1,2,3). filter coefficients programmed using 16-byte transfer with format shown Table
Table
Limits design
Design Ranges
-84.3 14.0 plus infinite steps over most range -24.1 24.1 plus infinite steps over most range -84.3 14.0 plus infinite steps over most range -84.3 14.0 plus infinite steps over most range
Table
Byte
Filter Format
Value
example, hands-free application using electret requiring gain transmit path optimum performance. typical implementation would gain. user would then have programmable range utilizing Selection these gain points course, application specific, will depend performance requirements system. Listings optimized programming values various levels included Appendix Values listed recommended tables still correct will perform stated. There need convert extended values unless greater resolution required. Programmable Filter Coefficients Equations frequency domain transfer function equation filters
Note: AmMAPsoftware, which calculates filter coefficients, available from Advanced Micro Devices. Contact your local Sales Office more information.
Test Facilities Three capabilities provided operation verification.
where: (wT) sin(wT) (-1) frequency input signal sample period seconds (0.125 0,1,.7) user-defined coefficients. Each coefficient defined following equation:
Analog Loopback
Signals sent AINA AINB sent back EAR1/EAR2 LS1/LS2 looping path MUX. should Ba-to-Ba loopback writing MCR1, MCR2, MCR3. other connections overriding Ba-to-Ba should programmed. This test allows analog digital tested using local signal source.
Digital Loopback
This loopback mode connects interpolator output decimator input place output. This mode allows verification from Interface micro-
Am79C30A/32A Data Sheet
processor that digital circuitry functional. Note that digital patterns received after loopback will identical transmitted patterns. gain approximately
Digital Loopback
This loopback mode connects analog output path analog input path, internal circuit. outputs both inputs will disabled. This mode allows verification from Interface microprocessor that analog digital circuitry functional. digital patterns received after loopback will identical transmitted patterns. bits mode Register define enable/disable options various configurations follows. Registers contains programmable registers found Table
Following reset, registers FTGR, MMR1, MMR2, MMR3, STRA, STRF default hex. other registers affected reset must programmed microprocessor before being enabled. When registers disabled, after reset, will have response shown Table
Table
Filter filter filter filter filter filter Sidetone gain
Default Values
Default Response Disabled Flat) Disabled Flat) Disabled Gain) Disabled Gain) Disabled Gain) Disabled (-18 Gain)
Table
Register X-filter Coefficient Register
Registers
Bytes Mnemonic STGR FTGR ATGR STRA STRF PEAKX PEAKR
R-filter Coefficient Register GX-Gain Coefficient Register GR-Gain Coefficient Register GER-Gain Coefficient Register Sidetone-Gain Coefficient Register Frequency Tone Generator Register Amplitude Tone Generator Register mode Registers Secondary Tone Ringer Amplitude Secondary Tone Ringer Frequency Transmit Peak Register Receive Peak Register
Note: necessary complete transfers multi-byte registers. instance, total bytes must transferred update filter.
Am79C30A/32A Data Sheet
Mode Register (MMR1) Read/Write Address Indirect
Table
Logical A-Law coefficient loaded from register coefficient loaded from register coefficient loaded from register coefficient loaded from register coefficient loaded from register
Mode Register
Logical (Default Value) µ-Law bypassed; gain bypassed; gain bypassed; gain bypassed; response flat bypassed; response flat gain Digital loopback disabled
Sidetone gain coefficient loaded from register Digital loopback enabled
Note: remove sidetone path completely, necessary enable function setting MMR1 program STGR coefficient 9008 (hex).34
Mode Register (MMR2) Read/Write Address Indirect
Table
Logical AINB selected LS1/LS2 selected DTMF enabled Tone generator enabled Tone ringer enabled High pass filter disabled auto-zero function disabled Reserved, must Logical
Mode Register
Logical (Default Mode) AINA selected EAR1/EAR2 selected DTMF disabled Tone generator disabled Tone ringer disabled High pass filter enabled auto-zero function enabled Reserved, must Logical
Note: most applications, MMR2 bits should always written logical This enables 50-60 rejection filter internal offset cancellation circuits operate normally. They both disabled when system test conditions require transmission frequency signals.
Am79C30A/32A Data Sheet
Mode Register (MMR3) Read/Write Address Indirect
Table
Function
Mode Register
Reserved, must written 0-dB pre-amplifier gain, 1.250-V maximum peak input voltage +6-dB pre-amplifier gain, 0.625-V maximum peak input voltage +12-dB pre-amplifier gain, 0.312-V maximum peak input voltage +18-dB pre-amplifier gain, 0.156-V maximum peak input voltage +24-dB pre-amplifier gain, 0.078-V maximum peak input voltage Reserved; undefined Reserved; undefined Reserved; undefined MUTE AINA AINB inputs disabled MUTE OFF, AINA AINB enabled Digital Loopback enabled; output looped input; EAR, disabled Digital Loopback disabled simultaneously enabled enabled MMR2 Secondary Tone Ringer enabled Secondary Tone Ringer disabled
Secondary Tone Ringer Amplitude Register (STRA) Read/Write Address Indirect
Table
Secondary Tone Ringer Amplitude
Peak-to-Peak Output Voltage Silent Reserved Reserved Reserved Reserved Reserved 0.22 0.31 0.44 0.62 0.88 1.25 1.77 2.50 3.53 5.00 Bits Reserved; must written 0.25 16.0 31.25 62.5 125.0 Relative Output Approximate Power into ohms
Am79C30A/32A Data Sheet
Secondary Tone Ringer Frequency Register (STRF), Read/Write; Address Indirect STRF Read/Write register controlling frequency secondary tone ringer. codes reserved should used. coefficients defined Table Table
Counter Value Frequency (Hz) Reserved Reserved 12000.0 9600.0 8000.0 6857.1 6000.0 5333.3 4800.0 4363.6 4000.0 3692.3 3428.6 3200.0 3000.0 2823.5 2666.7 2526.3 2400.0 2285.7 2181.8 2087.0 2000.0 1920.0 1846.2 1777.8 1714.3 1655.2 1600.0 1548.4 1500.0 1454.6 1411.8 1371.4 1333.3 1297.3 1263.2 1230.8 1200.0 1170.7 1142.9 1116.3 1090.9 1066.7 1043.5 1021.3 1000.0 979.6 960.0 941.2 923.1 905.7 888.9 872.7 857.1 842.1 Counter Value
Frequencies Secondary Tone Ringer
Frequency (Hz) 727.3 716.4 705.9 695.7 685.7 676.1 666.7 657.5 648.7 640.0 631.6 623.4 615.4 607.6 600.0 592.6 585.4 578.3 571.4 564.7 558.1 551.7 545.5 539.3 533.3 527.5 521.7 516.1 510.6 505.3 500.0 494.9 489.8 484.9 480.0 475.3 470.6 466.0 461.5 457.1 452.8 448.6 444.4 440.4 436.4 432.4 428.6 424.8 421.1 417.4 413.8 410.3 406.8 403.4 400.0 396.7 Counter Value Frequency (Hz) 369.2 366.4 363.6 360.9 358.2 355.6 352.9 350.4 347.8 345.3 342.9 340.4 338.0 335.7 333.3 331.0 328.8 326.5 324.3 322.2 320.0 317.9 315.8 313.7 311.7 308.7 307.7 305.7 303.8 301.9 300.0 298.1 296.3 294.5 292.7 290.9 289.2 287.4 285.7 284.0 282.4 280.7 279.1 277.5 275.9 274.3 272.7 271.2 269.7 268.2 266.7 265.2 263.7 262.3 260.9 259.5 Counter Value Frequency (Hz) 247.4 246.2 244.9 243.7 242.4 241.2 240.0 238.8 237.6 236.5 235.3 234.2 233.0 231.9 230.8 229.7 228.6 227.5 226.4 225.4 224.3 223.3 222.2 221.2 220.2 219.2 218.2 217.2 216.2 215.3 214.3 213.3 212.4 211.5 210.5 209.6 208.7 207.8 206.9 206.0 205.1 204.3 203.4 202.5 201.7 200.8 200.0 199.2 198.4 197.5 196.7 195.9 195.1 194.3 193.6 192.8
Am79C30A/32A Data Sheet
Table
Counter Value Frequency (Hz) 827.6 813.6 800.0 786.9 774.2 761.9 150.0 738.5
Frequencies Secondary Tone Ringer (Continued)
Frequency (Hz) 393.4 390.2 387.1 384.0 381.0 378.0 375.0 372.1 Counter Value Frequency (Hz) 258.1 256.7 255.3 254.0 252.6 251.3 250.0 248.7 Counter Value Frequency (Hz) 192.0 191.2 190.5 189.7 189.0 188.2
Counter Value
Data Link Controller (DLC)
Overview 16-Kbit/s D-channel time-multiplexed within frame structure Interface. data carried channel encoded using Link Access Protocol D-channel (LAPD) format shown Figure channel used carry either end-to-end signaling low-speed packet data. Further information concerning LAPD protocol found CCITT recommendations. controls multiplexing demultiplexing D-channel data between Interface DLC. performs processing Level-1 partial Level-2 LAPD protocol, including flag detection generation, zero deletion insertion, Frame Check Sequence (FCS) processing error detection, some addressing capability. High level protocol processing done external microprocessor. microprocessor process address field LAPD frame depending programmed state DLC. status held status registers relevant interrupts generated under user program control. addition transmit receive data FIFOs, contains 16-bit pseudo-random number generator (RNG) used CCITT D-channel address allocation procedure.
last byte aborted packet read from D-channel Receive buffer. Receive-Abort interrupt masked setting DMR2 logical With exception Packet-Reception-in-Progress bit, other bits associated with packet reception updated after receive packet abort. receive frame aborted time setting INIT logical Similarly, transmit frame aborted setting INIT logical When transmit frame aborted, seven consecutive transmitted Interface followed logical DSR1 logical Seven consecutive followed will continue transmitted long INIT DSR1 will after each sequence seven consecutive followed Level-2 Frame Structure D-channel Level-2 frame structure conforms formats shown Figure frames start with flag sequence consisting followed followed packet consists Level-2 frame minus flag bytes. transmitted first bytes except FCS. flag preceding packet defined opening flag. Therefore, byte following opening flag, definition, cannot abort another flag. closing flag defined flag that terminates packet. This flag followed another flag(s), interframe fill consisting flags, address field next packet. latter case, closing flag packet opening flag next packet. receiver recognize interframe fill consisting logical flags. transmitter follows closing flag with interframe fill consisting (mark Idle) DMR4 logical (flag Idle) DMR4 logical CCITT I-series D-channel access protocol specifies mark Idle. When collision detected (mismatch bit), complete frame must retransmitted. transfer across Interface, S-Interface frame structure impressed upon D-channel frame structure (LAPD). Zero Insertion/Deletion When transmitting, examines frame content between opening closing flags. ensure
D-channel Processing
Random Number Generator (RNG) accessible microprocessor operates following manner. Low-to-High transition reset signal, cleared, then started. stops when 16-bit counter read microprocessor, when loaded microprocessor. Writing counter loads this byte does start RNG. starts when counter loaded microprocessor. Frame Abort aborts incoming D-channel frame when seven contiguous logical received. When this occurs, End-of-Receive-Packet interrupt issued processor. logical when
Am79C30A/32A Data Sheet
that flag sequence repeated within flag boundaries frame, logical automatically inserted after each sequence five contiguous logical When receiving, examines frame content between opening closing flags automatically discards first logical which directly follows five contiguous logical D-Channel Address Recognition address field, shown Figure allows three types addresses: 1-byte address signified first address byte being logical 2-byte address signified first address byte being logical second address byte being logical More than 2-byte address signified both first second address bytes being logical
case LAPD operating environments, address 2-byte address where first byte analogous Service Access Point Identifier (SAPI) second byte analogous Terminal Endpoint Identifier (TEI) defined CCITT recommendations. able recognize D-channel addresses three types outlined above. Note that only first bytes more than 2-byte address checked DLC. There four First Received Byte Address Registers (FRARs) which hold values used match against first byte incoming address. Similarly, there four Second Received Byte Address Registers (SRARs) which hold values used match against second byte incoming address. FRAR4 defaults hex; SRAR4 defaults hex. This default analogous broadcast address defined CCITT recommendations. type address recognition which enabled shown Table
OCTET
SAPI
OCTET
FLAG 01111110 OCTET FLAG 01111110 OCTET
ADDRESS bits ADDRESS bits
CONTROL bits
bits
FLAG 01111110 bits FLAG 01111110
09893H-4
Minimum Packet
CONTROL bits
INFORMATION bits
General
Notes: Address Field Extension SAPI Service Access Point Identifier Frame Check Sequence
Command/Response Field Terminal Endpoint Identifier
Figure
Level-2 Frame Structure Formats
Am79C30A/32A Data Sheet
Table
DMR4 DMR1 Bits
.Address Recognition
Type address recognition FRAR1 FRAR3 FRAR4 SRAR1 SRAR2 SRAR3 SRAR4 FRAR1:SRAR1 FRAR2:SRAR2 FRAR3:SRAR3 FRAR4:SRAR4 Address recognition disabled 2-byte address Second received byte-only address First received byte-only address
DMR4 logical FRARs ignored when matching first incoming address byte. DMR4 logical bits FRARs used when matching first incoming address byte. FRAR analogous defined CCITT recommendations. address recognition mechanism four FRAR/SRAR addresses individually enabled/disabled DMR1 bits 4-7. First Received Byte-Only Address Recognition DMR4 logical DMR4 logical only first byte incoming address compared with values stored enabled FRARs. interrupt generated there address match Valid Address interrupt enabled. address matches, packet will received. Second Received Byte-Only Address Recognition DMR4 bits logical compares only value second byte incoming address with values stored enabled SRARs. interrupt generated there address match Valid Address interrupt enabled. address matches, packet will received. 2-Byte Address Recognition DMR4 logical first byte incoming address compared with values stored enabled FRARs, second byte incoming address compared with value stored corresponding SRAR. interrupt generated match found both incoming address bytes with FRAR/SRAR pair Valid Address interrupt enabled. address matches, packet will received. Disabling Address Recognition DMR1 bits logical address recognition disabled addresses rec38
ognized received. this case, Am79C30A/32A receives first bytes following opening flag (the incoming address), then issues Address interrupt Address interrupt enabled.
Operation
Transmit Receive FIFOs Transmit Receive FIFOs configured Normal Extended mode operation.Normal mode fully backwards compatible with Revision prior circuit, activated upon RESET EFCR programmed logical Normal mode Transmit Receive FIFOs each bytes length. Extended mode FIFO operation activated programming EFCR logical increasing depth Transmit Receive FIFOs bytes bytes, respectively. setting EFCR logical also alters available programmable FIFO threshold values DMR4 bits Receiving D-Channel Packets receiver controls flow D-channel data D-channel Receive buffer termination receive packet. packets contained D-channel Receive buffer. After receiving opening flag sequence 01111110) byte data which abort flag channel, sets Packet-Reception-in-Progress status (bit D-channel Status Register (DSR1). then receives first bytes (the address bytes). address recognition enabled, Am79C30A/32A issues Valid Address interrupt match between programmed values received address detected. match detected address recognition enabled, ignores packet. address recognition
Am79C30A/32A Data Sheet
disabled, Am79C30A/32A receives first bytes, issues Address interrupt, receives packet. Both Valid Address Address interrupt Interrupt Register logical D-channel Status Register (DSR1) logical Valid Address/End Address interrupt disabled DMR3 There internal 3-byte delay which holds first D-channel address bytes until interrupt been issued. Note that incoming address bytes cannot read however, until D-channel Receive Byte Available D-channel Receive Threshold interrupt set. After address received, continues receive D-channel bytes into D-channel Receive buffer FIFO. issues interrupt when data available D-channel Receive buffer. This interrupt disabled setting DMR3 logical also issues interrupt when receive threshold DMR4 reached. This interrupt disabled programming logical into DMR1 polling, microprocessor then read D-channel bytes. 3-byte delay incurred during address recognition maintained. Therefore, receives Frame Check Sequence (FCS) before issuing interrupt signal last byte packet been received appropriate status bits have been updated. DMR3 set, bytes packet transferred into D-channel Receive buffer along with data. issues interrupt when last byte packet read from DCRB. This interrupt disabled setting DMR3 logical After received, receiver detects closing flag sequence 01111110) then terminates packet issuing Receive Packet interrupt (bit DSR1) returns looking opening flags. also terminates packet when abort, overflow, overrun error condition detected. Receive Packet interrupt disabled setting DMR1 logical D-channel Receive Byte Count Register (DRCR) 16-bit wide, two-word deep FIFO that used record number bytes incoming D-channel packets. Each count terminated end-of-packet condition. Thus, DRCR informs microprocessor number bytes, including address bytes, which have been received. counter updated when last byte packet placed D-channel Receive buffer. When bytes included data transferred D-channel Receive buffer, bytes included byte count; bytes included transfer, they included byte count. opening flag closing flag included byte count.
D-channel Error Address Status Registers also double buffered. Reading last byte packet causes byte propagate output FIFO updates D-channel Status Interrupt Registers accordingly. Reading DRCR causes next count associated byte propagate output FIFOs updates D-channel Status Interrupt Registers accordingly. this reason important read ASR, DER, DSR1 prior reading DRCR. When receive error occurs, End-of-Packet interrupt generated packet terminated. When last byte associated packet read from D-channel Receive buffer, appropriate bits error interrupt generated. error interrupts individually masked setting corresponding bits DMR2 logical There 16-bit D-channel Receive Byte Limit Register (DRLR). received byte count compared with DRLR. When byte count currently received D-channel packet exceeds limit value, receiver overflow detected, packet terminated, End-of-Packet interrupt issued. D-channel Error Register (DER) logical overflow interrupt issued when last byte associated packet read from D-channel Receive buffer. Overflow Error interrupt masked setting DMR2 logical minimum packet length bytes 2-byte address packet (not including flags). packet length less than above, interrupt issued logical when last byte associated packet read from D-channel Receive buffer. error interrupt masked setting DMR2 logical packet reception progress D-channel Receive buffer full, microprocessor maximum respond D-channel Receive Data Available interrupt. microprocessor fails then overrun error occurs when data byte overwritten. When this happens, packet terminated. logical when last byte associated packet read from D-channel Receive buffer. Overrun Error interrupt masked setting DMR2 logical Error indication given packets have been received serviced user third packet received DSR2 When this error occurs, third packet terminated (not received). Error indication given receiver abort (the reception seven contiguous number bits received between flags integer multiple eight received packet does contain integral number bytes),
Am79C30A/32A Data Sheet
interrupt generated when last byte associated packet read from D-channel Receive buffer. incoming stream (including FCS) through generation compare block. Upon receipt closing flag, result checked must (MSB first) 0001110100001111. other pattern indicates error, logical when last byte associated packet read from D-channel Receive buffer. receiver does assume packet byte-aligned. architecture supports shared flags between packets, interframe fill consisting logical (Mark idle), interframe fill consisting flags (Flag idle). Mark idle defined least more contiguous Flag idle defined more than consecutive flag characters, including closing flag. DSR2 logical while Mark idle being detected. DSR2 logical while Flag idle being detected. receiver D-channel packet aborted time during reception setting INIT Transmitting D-Channel Packets Transmitter activated when (second byte) 16-bit D-channel Transmit Byte Count Register (DTCR) loaded microprocessor. Next, starts counting number consecutive E-channel until number defined priority mechanism detected. After sequence transmitter will begin packet transmission. Address bytes transmit packet handled ways: they loaded into transmit buffer loaded into Transmit Address Register (TAR). There 16-bit which loaded microprocessor. bytes loaded into transmitted first followed MSB. LAPD operation, contains SAPI, contains TEI. This 16-bit address (loaded first) transmitted within address field D-channel packet enabled setting DMR1 logical enabled, DTCR should loaded with number bytes transmitted excluding address, flags, FCS. disabled, DTCR should loaded with number bytes transmitted excluding flags FCS, microprocessor must load address transmitted first bytes D-channel packet data. issues interrupt when position avail-able D-channel Transmit buffer. This interrupt disabled setting DMR3 logical also issues interrupt microprocessor request D-channel data bytes when D-chan-
Transmit buffer empties threshold specified D-channel FIFO mode register. This interrupt disabled setting DMR1 logical D-channel Transmit buffer empty, microprocessor respond D-channel transmit buffer interrupt. microprocessor fails load data bytes this time frame, underrun interrupt generated packet transmission terminated with transmitted abort. Underrun interrupt masked setting DMR2 logical Transmission also terminated when collision detected loss synchronization occurs. D-channel Transmit Byte Count Register decremented each time byte data transferred from D-channel Transmit buffer DLC. count represents number bytes left transferred, excluding flags. transmit abort (INIT set, transmit byte count frozen indicates number bytes left transfer, number bytes transmitted. last byte packet determined D-channel Transmit Byte Count decrementing zero. When this occurs, DSR2 logical After last byte packet transmitted, adds closing flag. Then issues interrupt (bit DSR1) signify packet transmission. This interrupt masked setting DMR3 logical reset either reading DSR1 when D-channel Transmit Byte Count Register loaded next packet. Once D-channel Transmit Byte Count decremented second packet loaded into D-channel Transmit FIFO. D-channel Transmit Byte Count Register loaded prior end-of-transmit packet interrupt, second packet transmitted back-to-back with previous packet. End-of-Transmit Packet interrupt between packets. D-channel Transmit Byte Count Register loaded after end-of-packet interrupt, second packet transmitted once priority mechanism been resatisfied. Collision Detection Network Terminator echoes transmitted D-channel data back E-channel bits S-interface frame. there difference between data transmitted data echoed back, collision occurred. alerts microprocessor this event asserting interrupt line (INT) setting collision occurs during transmission abort sequence, interrupt still issued. collision detect interrupt masked setting DMR2 logical
Am79C30A/32A Data Sheet
D-Channel Receive Transmit Errors
Non-Integer Number Bytes
non-integer number bytes occurs when number D-channel bits received between opening closing flags divisible eight. received packet consists non-integer number bytes, sets D-channel Error Register (DER) logical when last byte associated packet read from D-channel Receive buffer.
Underflow
received D-channel (including FCS) packet less than bytes 2-byte address packet, underflow error condition occurs, sets logical when last byte associated packet read from D-channel Receive buffer.
Overrun
D-channel overrun error occurs when receiver buffer full, another byte received. This happen D-channel Receive buffer fills, read within When this error occurs, sets logical terminates packet.
Frame Check Sequence Error
received packet, including 16-bit Frame Check Sequence, received perfectly, sets logical when last byte associated packet read from Receive buffer.
Underrun
D-channel underrun error occurs when empty D-channel buffer transmitted. This happen D-channel Transmit buffer loaded within D-channel Transmit buffer Empty interrupt being asserted When this error occurs, sets logical terminates packet.
Receive Packet Abort
seven contiguous received while receiving packet, packet will terminated. will logical when last byte associated packet read from D-channel Receive buffer.
Overflow
Overflow occurs when total number D-channel bytes within packet (including, only when enabled, Frame Check Sequence bytes) exceeds limit contained D-channel Receive Byte Limit Register. (See Receiving D-channel Packets section.) When overflow occurs, terminates packet, sets logical when last byte associated packet read from D-channel Receive buffer.
Receive Packet Lost
Receive Packet Lost occurs when outstanding packets have been received serviced (the microprocessor read DCRB register), third packet received. When this error occurs, DSR2 logical incoming packet terminated (not received).
REGISTERS
contains following registers.
Registers First Received Byte Address Registers Second Received Byte Address Registers Transmit Address Register (16-bit) D-channel Receive Byte Limit Register (16-bit) D-channel Receive Byte Count Register (16-bit) (2-word FIFO) D-channel Transmit Byte Count Register (16-bit) Random Number Generator Registers D-channel mode registers Address Status Register (2-byte FIFO) Extended FIFO Control Register D-channel Transmit buffer Register D-channel Receive buffer Register D-channel Status Register D-channel Status Register D-channel Error Register (2-byte FIFO) Number Registers Mnemonic FRAR SRAR DRLR DRCR DTCR RNGR EFCR DCTR DCRB DSR1 DSR2
Am79C30A/32A Data Sheet
Transmit Address Register (TAR) Read/Write Address Indirect This register contains address packet transmitted enabled (DMR1 First Received Byte Address Register (FRAR1-FRAR4) Read/Write Address Indirect FRAR1-FRAR3 81H, FRAR4 These registers contain value match against first byte incoming address. DMR1 bits disabled, these registers ignored. Second Received Byte Address Register (SRAR1-SRAR4) Read/Write Address Indirect SRAR1-SRAR3 82H, SRAR4 These registers contain value match against first byte incoming address. DMR1 bits disabled, these registers ignored. D-Channel Receive Byte Count Register (DRCR) Read Address Indirect This register determines maximum number bytes received packet. D-Channel Receive Byte Limit Register (DRLR) Read/Write Address Indirect This register contains total number received bytes. D-Channel Transmit Byte Count Register (DTCR) Read/Write Address Indirect This register contains total number transferred bytes. Random Number Generator Register (RNGR1, RNGR2) Read/Write Address Indirect RNGR1 8AH, RNGR2 These registers control operation Random Number Generator. When read, they display random number generated chip. D-Channel Transmit Buffer Register (DCTB) -Write D-channel transmit FIFO. D-Channel Receive Buffer Register (DCRB) Read D-channel receive FIFO. D-Channel Mode Register (DMR1) Read/Write Address Indirect DMR1 controls enable/disable options DLC. under sole control microprocessor does generate interrupts. DMR1 defined Table Table
Logical Enable D-channel Receive Threshold interrupt (see Enable Transmit Address Register Enable Receive Packet interrupt (see DSR1 Enable FRAR1/SRAR1 Enable FRAR2/SRAR2 Enable FRAR3/SRAR3 Enable FRAR4/SRAR4
D-Channel Mode Register
Logical Disable interrupt (default value) Disable Transmit Address Register (default value) Disable interrupt (default value) Disable FRAR1/SRAR1 (default value) Disable FRAR2/SRAR2 (default value) Disable FRAR3/SRAR3 (default value) Disable FRAR4/SRAR4
Enable D-channel Transmit Threshold interrupt (see Disable interrupt (default value)
Am79C30A/32A Data Sheet
D-Channel Mode Register (DMR2) Read/Write Address Indirect DMR2 used enable/disable interrupts generated (see definition page 41). DMR2 controlled microprocessor does generate interrupts. DMR2 defined Table Table
Logical Enable Receive Abort interrupt (see Enable Non-integer Number Bytes Received interrupt (see Enable Collision Abort Detected interrupt (see Enable Error interrupt (see Enable Overflow Error interrupt (see Enable Underflow Error interrupt (see Enable Overrun Error interrupt (see Enable Underrun Error interrupt (see
D-Channel Mode Register
Logical (Default Value) Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt
D-Channel Mode Register (DMR3) Read/Write Address Indirect
Table
Logical
D-Channel Mode Register
Logical (Default Value)
Enable Valid Address/End Address interrupt (default value) (see DSR1 Disable interrupt Enable Valid Transmit Packet interrupt (default value) (see DSR1 Disable interrupt Enable Last Byte Received Packet interrupt (see DSR2 Enable Receive Byte Available interrupt (see DSR2 Enable Last Byte Transmitted interrupt (see DSR2 Enable Transmit buffer Available interrupt (see DSR2 Enable Received Packet Lost interrupt (see DSR2 Enable transfer FIFO Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable transfer FIFO (default value)
Am79C30A/32A Data Sheet
D-Channel Mode Register (DMR4) Read/Write Address Indirect Table
Interframe Fill Address Recognition Transmitter Threshold
D-Channel Mode Register
Function byte (EFCR byte (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR byte (EFCR byte (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR bytes (EFCR Mark Idle (default value) Flag Idle 2-byte (default value) First Received Byte only Second Received Byte only Disable FRAR compare (default value) Enable FRAR compare
Control Receiver Threshold
Compare
Note: receiver transmitter thresholds only changed when Am79C30A/32A Idle mode.
Address Status Register (ASR) Read Only Address Indirect Table
Logical FRAR1/SRAR1 address recognized FRAR2/SRAR2 address recognized FRAR3/SRAR3 address recognized FRAR4/SRAR4 address recognized Reserved
Address Status Register
Logical (Default Value) FRAR1/SRAR1 address match FRAR2/SRAR2 address match FRAR3/SRAR3 address match FRAR4/SRAR4 address match Reserved
Am79C30A/32A Data Sheet
D-Channel Status Register (DSR1) Read Only DSR1 format shown Table Table
Logical Valid Address (VA) address decode logic enabled End-of-Address (EOA) address decode logic disabled receive packet Packet reception progress Loopback operation Am79C30A/32A Loopback operation D-channel back-off operation valid transmit packet Current transmit packet been aborted
D-Channel Status Register
Logical (Default Value) valid address packet Packet being received loopback operation Am79C30A/32A loopback operation D-channel back-off operation end-of-transmit packet transmission transmit packet abort
DSR1 bits generate interrupts set/reset under conditions shown Table addition hardware reset Idle mode). Table
Generate Interrupt Yes, DMR3 Yes, DMR1 Yes, DMR3 bytes after opening flag decoded address recognition disabled When closing flag received byte after opening flag packet, valid When operation progress When operation progress When operation progress When closing flag transmitted
DSR1 Interrupts
Reset When microprocessor reads DSR1 associated DRCR When microprocessor reads DSR1 associated DRCR When flag abort received When operation progress When operation progress When operation progress When microprocessor reads DSR1 when DTCR loaded
When seven have been transmitted When microprocessor reads DSR1 when DTCR loaded
Am79C30A/32A Data Sheet
D-Channel Status Register (DSR2) Read Only DSR2 format illustrated Table Table
Logical Last byte received packet Receive byte available Receive packet lost Last byte transmitted Transmit buffer available Mark idle detected more contiguous
D-Channel Status Register
Logical (Default Value) last byte received packet Receive byte available Receive packet lost Last byte transmitted Transmit buffer available* Mark idle detected
Flag idle detected (more than contiguous flags) Flag idle detected Start second received packet FIFO Second packet FIFO
Note: *Following RESET, Transmit buffer Available (bit set, producing default value 10H.
DSR2 bits generate interrupts set/reset under conditions shown Table addition hardware reset Idle mode). Table
Generate Interrupt Yes, DMR3 Yes, DMR1 Yes, DMR3 Yes, DMR3 Yes, DMR3 Yes, EFCR When last byte received packet read from DCRB When DCRB contains more bytes data When outstanding packets received serviced, third packet received
DSR2 Interrupts
Reset When microprocessor reads DSR2 When DCRB empty When microprocessor reads DSR2
When last byte transmit packet transferred from When microprocessor reads DCTB DSR2 When DCTB available loaded with data byte When DCTB full When contiguous bits have been detected incoming channel When first zero detected incoming channel
When more than contiguous flags detected When non-flag character incoming channels, including closing flag detected incoming channel When start second packet receive FIFO When second receive packet present
Am79C30A/32A Data Sheet
D-Channel Error Register (DER) Read Only format illustrated Table Table
Logical Received Packet Abort Non-integer number bits have been received Collision Detected Error Overflow Error Underflow Error Overrun Error Underrun Error
D-Channel Error Register
Logical (Default Value) abort received Integer number bits received error error error error error error
bits when last byte associated packet read from D-channel Receive buffer. bits generate interrupts set/reset under conditions shown Table addition hardware reset). Table
Generates Interrupt
Interrupts
Reset When microprocessor reads associated DRCR When microprocessor reads associated DRCR When microprocessor reads when DTCR loaded When microprocessor reads associated DRCR When microprocessor reads associated DRCR When microprocessor reads associated DRCR When microprocessor reads associated DRCR When microprocessor reads when DTCR loaded
Yes, DMR2 When seven consecutive received within packet (DSR1 Yes, DMR2 Upon error condition after closing flag been received Yes, DMR2 section collision detection Yes, DMR2 error occurs Yes, DMR2 error occurs Yes, DMR2 error occurs Yes, DMR2 error occurs Yes, DMR2 error occurs
Extended FIFO Control Register (EFCR) Read/Write Address Indirect
Function Bits reserved, must written Bits control attenuation analog sidetone path (ASTG) Start Second Received Packet FIFO interrupt disabled Start Second Received Packet FIFO interrupt enabled Normal mode FIFO operation Extended mode FIFO operation
Table
Am79C30A/32A Data Sheet
Peripheral Port (PP)
Overview purpose Peripheral Port allow external peripherals connected DSC/IDC circuit. There basic modes operation, Serial Port mode, IOM-2 Terminal mode. Within IOM-2 Terminal mode, DSC/IDC circuit configured combination IOM-2 timing/control master slave. definition Peripheral Port pins depends operating mode port, described Table Serial Port (SBP) Mode mode operation backwards compatible with Revision circuit serial port entered either following device RESET programmed PPCR1. mode, SCLK output provides 192-kHz data clock programmable polarity. SBIN SBOUT pins support three 8-bit serial data channels, designated output provides 8-kHz serial frame sync pulse eight periods width, coincident with channel. mode timing illustrated Figure
Following RESET, SCLK outputs will default high-impedance state, which will maintained until connection programmed until Peripheral Port programmed IOM-2 mode). SCLK will remain high-impedance state Peripheral Port explicitly disabled. SCLK signals synchronized received S-interface frame. there S-interface frame synchronization, SCLK signals will free-run respectively. DSC/IDC circuit programmed Idle mode, output driven SCLK continues run. Power-Down mode, both SCLK outputs high-impedance. IOM-2 Terminal Mode Overview IOM-2 Interface standard encompasses both Linecard mode Terminal mode. Terminal mode defined provide four functions, follows: Connection multiple Layer-2 devices Layer-1 device this case, Layer-1 device Interface LIU). Provision connection non-IOM-2 devices included. Programming control Layer-1 Layer-2 devices that have microprocessor interface, example, U-interface transceiver.
Table
SBIN SBOUT SCLK BCL/CH2STRB
Operation versus Peripheral Port Modes
IOM-2 Deactivated IOM-2 IOM-2 IOM-2 IOM-2 Reverse Reverse Reverse Reverse Deactivated Deactivated Activated Activated IN/OD OD/IN
Port IOM-2 Disabled Activated
Input
Output
High Impedance
Open Drain Output
Note: *The Am79C30A non-Layer-1 component when operated Slave mode; however, microprocessor interface. result, required change direction pins certain times order communicate with both upstream Layer-1 device downstream peripheral devices. IOM-2 Slave mode, direction data flow reversed with respect circuit during Sub-frame during deactivated state. rule that upstream Layer-1 device only uses Sub-frame does reverse pins. non-Layer-1 component that does contain microprocessor interface (i.e., program circuit over Monitor channel Sub-frame uses Sub-frame talk Layer-1 device Sub-frame talk circuit. does reverse pins.
Am79C30A/32A Data Sheet
SCLK SBIN SBOUT 41.7
Note: SBIN sampled rising edge SCLK. SBOUT changed falling edge SCLK.
09893H-6
Figure
Serial Port Mode Timing 16-kbits/s channel signaling data packets. Command/Indicate channels, labeled C/I0, C/I1, provide status command devices connected monitor channels. Command/Indicate channel first IOM-2 subframe consists four bits, providing states each direction. second subframe channel bits, providing states each direction. 64-kbits/s intercommunication channels, labeled IC2, provide additional interdevice communications bandwidth.
Inter-chip communication between devices bus, instance, data flow between circuit external speech encryption device. Connection multiple DLCs channel, including access arbitration. This function referred channel. IOM-2 Terminal mode consists three IOM-2 subframes, each containing bits. This 12-byte frame repeated kHz, resulting aggregate data rate kbits/s. frame structure illustrated Figure contains following channels: 64-kbits/s data channels, labeled device programming channels, labeled Monitor Each channel associated pair handshake bits that control data flow.
data transmitted IOM-2 Interface SBOUT transmitted first, with exception D-channel data, which transmitted first. receiver operates compatible SBIN pin.
MR,MX SBIN/ SBOUT channel channel channel
09893H-7
MR,MX MON1
MON0
Figure
IOM-2 Terminal Mode Frame Structure
Am79C30A/32A Data Sheet
DSC/IDC Circuit IOM-2 Terminal Mode Implementation
Data Channels
channels physically first 8-bit time slots after frame sync pulse. When making connection these channels, IOM-2 channels correspond channels respectively. When IOM-2 mode, connection channel provides access intercommunication channels selected PPCR1.
through LIU. D-channel data received from Interface also output IOM-2 Interface. D-channel data received from IOM-2 Interface disregarded. however, enabled, control logic will arbitrate D-channel data flow between Interface either IOM-2 Interface based access procedures. When Peripheral Port configured IOM-2 slave, will transmit receive D-channel data from IOM-2 Interface. This will dedicated path feature disabled, with access arbitrated according access procedures feature enabled. used this situation, there D-channel data flow between LIU.
Command/Indicate Channels
Peripheral Port supports channels first second IOM-2 subframes. Peripheral Port monitors these channels, generates interrupt time received data changes stable frames. received data read from Receive Data Register transmit data written Transmit Data Register When feature enabled, C/I0 transmit access IOM-2 Interface controlled CITDR0 Access Request.
Monitor Channels
Support Monitor channels provided one-at-a-time basis. Peripheral Port Control Register selects which Monitor channels utilized time.
IOM-2 control bits reside last byte IOM-2 Terminal mode frame (channel byte bits their definitions shown Figure
Channel
peripheral Port configured IOM-2 master with disabled, will transmit receive D-channel data from Interface
Data Upstream (output)
TBA2 TBA1 TBA0
Data Downstream (input)
Notes: (Bus Accessed): indication other devices that being accessed. When accessed, when free. This driven zero device that gets address match TBA2-0 bits. TBA2-0 bits (TIC Address): address used arbitration control Assumes Open-Drain such that device with highest zero content address highest priority. Lowest priority address, which also default, 111. E-bits (Echo): D-channel Echo bits from S-bus. Will supported DSC. (Stop/Go): used indicate availability S-bus D-channel. When D-channel clear transmission. When D-channel transmission should halted. (Available/Blocked): supplementary D-channel control. indicates D-channel available, D-channel blocked. Optional, will supported DSC.
Figure
Control Bits Definitions
Am79C30A/32A Data Sheet
MASTER Mode
timing master (FSC SCLK outputs) control master (can communicate with downstream devices). configuration timing master control slave covered within this mode. presence provides C/I0 access downstream devices. control slave applications, disable IOM-2 channel communications.
MON0, C/10, IC1, IC2, MON1, C/I1, S/G(out), TIC(in) SBOUT
upstream
SBIN
Downstream
Downstream
downstream
Figure
IOM-2 Master Mode Operation
Am79C30A/32A Data Sheet
SLAVE Mode Reversal Enabled
timing slave (FSC SCLK inputs) control master (can communicate with other downstream devices MONI C/I1). C/I0 arbitration provided capability.
Utransceiver IC1, IC2, MON1, C/I1
MON0, C/I0, S/G(in), TIC(out) SBOUT SBIN
upstream
Downstream
Downstream
downstream
Figure IOM-2 Slave Mode Operation with Reversal
Am79C30A/32A Data Sheet
SLAVE Mode Reversal Disabled
timing slave (FSC SCLK inputs) control master (cannot communicate with other downstream devices). C/I0 arbitration provided capability.
Master SBOUT MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) SBOUT SBIN SBIN
upstream
Downstream
Downstream
downstream
Figure IOM-2 Slave Mode Operation without Reversal
Am79C30A/32A Data Sheet
Intelligent
Either Slave mode used implement Intelligent configuration. diagram below depicts this configuration using Slave mode with reversal disabled. U-transceiver operates IOM-2 master device, programmed mode outputting 1536-kHz DCL. indicates D-channel request according procedure using line (BAC=0). S-transceiver surveys received channel idle, enables send D-channel frame U-transceiver driving S-transceiver also sets transmitted E-channel bits S-Interface zero (inversion received bits) prevent connected from transmitting data into D-channel. When completes D-channel transmission, releases setting BAC=1. S-transceiver then mirrors incoming bits into E-channel, thus behaving normal with transparent D-channel handling.
U-transceiver Master DOUT/DD MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) SBOUT SBIN DIN/DU
upstream
D-channel E-channel S-transceiver LT-S
Interface
downstream
Figure IOM-2 Intelligent Configuration
Am79C30A/32A Data Sheet
Monitor Channel Procedures Monitor channel operates event-driven basis; although data transfers synchronized frame sync, flow data controlled handshake procedure using outgoing incoming bits. Thus, actual data rate fixed, dependent upon response speed transmitter receiver. Figure illustrates sequence events monitor handshake procedure.
byte data been transmitted, indicated Monitor Transmit Data Register being empty end-of-transmission (EOM) being PPCR1, outgoing deactivated response incoming going inactive, left inactive.
First Byte Reception
time receiver sees first byte, indicated inactive-to-active transition incoming outgoing definition inactive. Outgoing activated response activation incoming data byte loaded into Monitor Receive Data Register, Monitor channel receive data available interrupt generated. Outgoing remains active until next byte received end-of-message detected (incoming held inactive more frames).
Idle State
outgoing incoming bits held inactive more frames indicates that Monitor channel Idle outgoing direction.
Start Transmission
PPCR1 register programmed select monitor channels. Data then loaded into monitor Transmit Data Register, causing first data byte presented well inactive-to-active transition outgoing Monitor channel transmit buffer available interrupt also generated when data placed bus, indicating that next data byte written buffer. Outgoing remains active, data repeated until inactive-to-active transition incoming received.
Subsequent Reception
Data received into buffer each falling edge incoming Monitor channel receive data available interrupt generated. Note that data actually valid time incoming became inactive, frame prior becoming active. Outgoing deactivated time data read reactivated frame later. reception data terminated reception end-of-message indication, which incoming remaining inactive more frames.
Subsequent Transmission
Following detection first inactive-to-active transition incoming following bytes transmitted will presented coincident with active-to-inactive transition outgoing IOM-2 specification defines general case (Figure 12a) which transmitter waits inactive-to-active transition incoming maximum speed case (Figure 12c) which transmitter achieves higher transmission rate anticipating falling edge incoming DSC/IDC circuit Monitor channel transmitter implements maximum speed case follows: second byte placed onto start frame following transition incoming (High Low), Monitor channel transmit buffer available interrupt generated. Simultaneously, outgoing returned inactive frame, then reactivated. Note that frames outgoing inactive signifies message. Outgoing data byte remain valid until incoming goes inactive. next byte transmitted during next frame, meaning frame after incoming goes inactive. this manner, transmitter anticipating incoming returning active, which will frame time after deactivated, unless abort signaled from receiver. After last
End-of-Transmission (EOM)
transmitter sends response request being PPCR1. Once set, transmitted soon Monitor Transmit Data Register becomes empty. This normally done when last byte message been transmitted. DSC/IDC circuit transmits simply reactivating after deactivating response going inactive. request PPCR1 automatically cleared when been transmitted, indicating that monitor transmitter available message.
Abort
abort signal from receiver transmitter indicating that data been missed. receiver sends abort holding inactive more frames response going active. interrupt generated when abort received.
Flow Control
transmitter held until Monitor Receive Data Register read, since held active until receive byte read. transmitter will start next transmission cycle until goes inactive.
Am79C30A/32A Data Sheet
Transmitter First Byte Receiver General Case Byte Last Byte
Transmitter Byte Receiver
Abort Request Abort Request from Receiver
Transmitter First Byte Receiver First Byte Second Byte Third Byte Second Byte Third Byte
Maximum Speed Case Figure Monitor Handshake Timing
09893H-8
Am79C30A/32A Data Sheet
IOM-2 Activation/Deactivation IOM-2 Interface includes activation/deactivation capability (see Figure 13). Activation deactivation initiated from either upstream downstream components bus. When deactivated, upstream device holds clock outputs Low, downstream devices force their open drain data outputs High-Z state (seen High system external pullup resistor). activation/deactivation procedure combination software handshakes channel, hardware indications clock data lines. IOM-2 specification describes both hardware software protocols detail; hardware operation supported Am79C30A IOM-2 implementation outlined Figure
DSC/IDC Circuit Upstream Device (Clock Master)
Deactivation
Am79C30A operating upstream device initiated controlled microprocessor. series software handshakes channel must performed before hardware deactivation take place. upstream device must issue deactivation request command channel wait deactivation indication from downstream units. Once this received, deactivation confirmation command must sent channel upstream device. upstream device will then stop clocks hold them Low. Am79C30A, IOM-2 clocks (SCLK,SFS, BCL/CH2STRB) stopped forced when microprocessor clears activation/deactivation Peripheral Port Control
SBIN goes Timing Request Interrupt generated
Idle (clks off)
pend (clks off)
Software clears Activation
Software sets Activation
Software sets Activation
ACTIVE (clks
Am79C30A Upstream Device Idle (clks off) (SBIN
Software sets Activation SBIN output forced (SBIN (clks off)
SBIN output forced
Clock received from upstream; Timing Request interrupt generated (SBIN (clks Software sets Activation ACTIVE (clks (SBIN data)
Timeout (clks off)
Clocks stopped upstream device
Am79C30A Downstream Device
09893H-9
Notes: This diagram shows only portions IOM-2 activation/deactivation procedures that affected Am79C30A hardware. C/I-channel software handshakes shown.
Figure
IOM-2 Activation/Deactivation
Am79C30A/32A Data Sheet
Register Number (PPCR1). When this cleared, data output (SBOUT) also forced High-Z (seen High system external pullup resistor), Am79C30A begins monitoring data input (SBIN) presence timing request from downstream units.
allow processor complete activation procedure sending proper commands over channel. When activation originated from upstream device, Am79C30A will generate IOM-2 timing request interrupt (bit PPSR) when IOM-2clocks become active indicated SCLK input going High. Am79C30A will begin normal IOM-2 transmission/reception soon SCLK appears; intervention from microprocessor required. However, processor must respond interrupt perform normal channel software handshakes before activation will complete.
Activation
Activation initiated locally processor remotely downstream units. activate locally, processor sets activation/deactivation PPCR1 (starting clocks), then proceeds through software activation protocol C/Ichannel. remote activation, upstream device receives request from downstream device data input pin. When data input (SBIN) goes Low, Am79C30A will generate IOM-2 timing-request interrupt, Peripheral Port Status Register (PPSR). processor must respond this interrupt, restart IOM-2 clocks setting activation/deactivation PPCR1. Once clocks running, downstream device request full activation channel using IOM-2 software protocol. DSC/IDC Circuit Downstream Device (Clock Slave)
Operation
C/I0 Channel Arbitration Software control IOM-2 Accessed (BAC) will added CITDR0, which currently reserved. will referred BAR, "Bus Access Request" bit. This will used gain access C/I0 channel when supp enabled (PPCR3.3=1). should whenever C/I0 data available transmit. When CITDR0.7=1, will arbitrate access C/I0 channel with other devices IOM-2 interface using address programmed into PPCR3.2-0. control logic will check line determine another downstream device currently owns bus. zero, will wait. Once detected BAC, logic will place DSC's address open drain output. will then sample this output with IOM-2 received data strobe timing check conflict with other downstream devices. received address contents PPCR3.2-0 match, logic will output indicating other downstream devices that taken control C/I0 channels. After sets output logic will compare address line with PPCR3.2-0 more frame ensure ownership bus. miscompare occurs, will output return beginning arbitration. Once access gained, C/I0 channels possession DSC. This allows complete C/I0 communication with Layer device without interruption from other downstream devices. (Since used arbitration both C/I0 channel communication, gaining access implicitly gives access other). After completes C/I0 communication, software should CITDR0.7=0 allow other downstream devices access C/I0 channels. logic will output back long
Deactivation
Deactivation normally initiated upstream device described above. When deactivation request received downstream device over channel, processor must respond sending deactivation indication over channel. upstream device will then send deactivation confirmation command over channel stop IOM-2 clocks. Am79C30A will detect that clock stopped (defined clock pulse received force itself deactivated state. deactivated state, SBIN, SBOUT both forced High-Z state, SCLK input monitored rising edge that would indicate activation request from upstream device.
Activation
Once again, activation originate from either upstream downstream device. activate interface from downstream device, processor sets activation/deactivation PPCR1 register. Thi
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