This application note overview discussion Linear Technology SPICE macr

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Getting Most from SPICE Library Walt Jung
This application note overview discussion Linear Technology SPICE macromodel library. assumes little prior knowledge this software library history. However, does assume familiarity with both analog simulation program SPICE many derivatives), modern amps, including bipolar, JFET, MOSFET amplifier technologies.
Some Preliminary SPICE Facts Life past years, SPICE simulations have really begun capture high level attention part analog circuit designers. Perhaps this more affordable high performance computers, perhaps time simulation upon event, bottom line that vendors making macromodels amps available their customers. analog circuit designer, there better fate simulations, viewing this situation terms which model use. Designers longer need worry about whether third party supplier's model really Speaking terms ultimate potential, know actual part better than people designed produced that original source vendor. only possible caveat this scenario that vendor supplying model needs fully understand only real part, they must also understand SPICE modeling issues. Without both types understanding firmly place, user with real part that works well model which doesn't. such case, simulation will little value; simulation runs verify circuit performance won't match actual part's bench performance. Fortunately, this type problem seems diminishing. this were rapid increase attention models
would taking place. However, necessarily peaceful bliss analog designs, yes, still need actually build breadboards check circuit designs lab. go-go project managers "Simulate don't have time fool with breadboard handbuilt prototypes." Rarely will this ramrod approach truly wise move, future, except specialized circumstances. While certainly true that computers, that they really tasks many ways, that simply enough cases. SPICE simulation tool) only upon information into analyze circuit. Model quality issues aside moment, honestly that have fully sufficient characterization data every single relevant connection point/load that your circuit will ever see? understand parasitic issues will face? these, then maybe that need just good model, SPICE. More likely, there will always some uncertainties, breadboarding will remain only advisable choice relatively complex circuits, particularly those never built before. This then leaves question model quality degree functionality answered. presently available models enough? Just they trusted types simulations that performed? Hopefully, most these answers will more apparent this note, contains many different examples. Nevertheless, vendor other model supplier) likely ever stand say, guarantee this model when used with simulator ABC, simulated performance will within actual part connected within corresponding circuit."
registered trademarks trademark Linear Technology Corporation.
AN48-1
Application Note
Forget SPICE simply doesn't work that way, likely never will. What SPICE good predictive analysis, worst case limit testing, design feasibilities, etc. even then will always have limitations; will never better than information obviously this impacts macromodels well other circuit elements. This sound first like questionable reward, bear mind just worst case design performance limit board with several dozen components. Traditionally, this been only difficult, very often didn't done (except production line "hot patches"). Logically then, manufacturers offering macromodels place caveats performance limitations them, which should understood user. These caveats don't make models useless, they define nature extent what they achieve. following model disclaimer typical, excerpted from model library: perhaps first thing understand about SPICE macromodels that they invariably come with caveats. Such macromodel facts life. But, like many other things design engineering, macromodel good bad, dependent upon what need with Indeed, circuit requirements differ, either considerations drive given application. LTC, feel that overall performance macromodel what make break Therefore, modeling been directed towards getting maximum real world performance models, that performance which many ways like actual device. But, also means models which sacrifice general utility maximize single aspect performance, whatever. Background SPICE Macromodels Circuit designers generally like work quickly efficiently with SPICE simulations, macromodel approach fundamentally very attractive, good reason. Rather than using full transistors, macromodels various controlled sources supported within SPICE, they also minimize/simplify junctions much possible. This approach increase simulation speed several fold over full circuit using 30-40 actual transistor models. also work well (within limitations) given well designed macromodel. macromodeling start about years ago, what classic topological approach Boyle, Cohn, Pederson, Solomon.1 model topology described this seminal work become known generically Boyle macromodel. With recent advances computing hardware, modeling linear circuit design taken last years. This course re-focused attention modeling techniques general, Boyle architecture particular. Now, armed with better macromodels their designs, analog circuit architects able many cases move more quickly toward better designs.
Note Boyle, G.R., Cohn, B.M., Pederson, D.O., Solomon, J.E., "Macromodeling Integrated Circuit Operational Amplifiers," IEEE Journal Solid-State Circuits, Vol. SC-9, December 1974.
"This library macromodels being supplied users circuit designs. While models reflect reasonably close similarity corresponding devices performance terms, their suggested replacement breadboarding. Simulation should used forerunner supplement traditional testing. Users should very carefully note following factors regarding these models: Model performance general will reflect typical baseline specs given device, certain aspects performance modeled fully. While reasonable care been taken their preparation, cannot responsible correct application computer systems. Model users hereby notified that these models supplied with direct implied responsibility part their operation within customer circuit system. Further, Linear Technology Corporation reserves right change these models without prior notice. cases, current data sheet information given real device your final design guideline, only actual performance guarantee. further technical information, refer individual device data sheets. Your feedback suggestions these (and future) models will appreciated!
AN48-2
Application Note
4.4k 4.6pF 4.4k 30pF
GCMVE 1.2nS GAVA 230µS 100k GBVB
2.4k 2.4k 27.5E-6 1.6pF 7.3M 52.7 52.8
200µ
GCV6
-VEE EQUATIONS: BASIC BOYLE MODEL IEE/C2 (FOR RO2) 1/(2 (IS1/IS2) NODE (GND) DEFAULT COMMON SPICE.
LTAN48 TA01
Figure Boyle Macromodel
Short Course Boyle Macromodel While Boyle model topology become default macromodel standard, also received criticism performance aspects doesn't handle. Unfortunately, this criticism been well focused, couched meaningful perspective. example, many critics Boyle model often fault what doesn't original most basic form, simply ignore more recent enhancements (which, ironically, aren't hard find). such case Boyle based macromodels with many useful enhancements those produced MicroSim Parts2 program. And, following discussions show, basic Boyle model been usefully enhanced expanded other regards. Boyle macromodel shown Figure essentially just originally described 1974 paper. This example model amp, which bipolar input stage. model parameters noted figure, when run, this macromodel duplicates characteristics device quite well. Comparison actual parameters modeled done detailed contrast paper's appendix parameters, those this figure. Note that typical numbers have been added this model more closely
real device. will later apparent, this nodal convention used throughout amplifiers. Listing (see listings application note) sample macromodel 8741 amp. This model produced macromodel program amps, with input data taken from Boyle paper appendix (Note: there actual "8741"; this particular model done exercise). Comparison first portions this model with values Figure shows good correlation.3 Some equations basic Boyle macromodel noted Figure they found within text paper itself. parameters modeled gain bandwidth product (GBP), slew rate (SR), phase margin, gain (AVD), CMRR, input offset voltage (VOS), input bias current (IB), input offset current
Note MicroSim, vendor PSpiceTM, ProbeTM, PartsTM. Fairbanks, Irvine, 92718, (714) 770-3022. Note This comparison Listing 8741 macromodel with Boyle original valid only code within sections "INPUT" portions "INTERMEDIATE." will noticed, there only slight differences here (due rounding). Because different type voltage/current limiting used macromodel, there major differences RO2, those portions following, which show code after "OUTPUT."
AN48-3
Application Note
(IOS), output current limiting (ISC), output voltage limits (VSAT output resistance (ROUT), power supply quiescent current (IQ). (Note: diode/VCCS diode/ voltage source elements this figure around associated with voltage current limiting original Boyle model. Inasmuch these networks heavily used macromodels, they discussed detail. functional replacements current voltage limiting will discussed following section). Gain-Normalized Input Stage Operation There very important design distinction Boyle model topology which allows extremely flexible with regard adaptations other input transistor types. Referring Figure simplified schematic-form Boyle type model, this feature lies fact that input differential transistor pair Q1/Q2 are, fact, macromodel design parameters operate differential gain unity. case bipolar types shown, original Boyle design equations establish this
presumption that gain from amplifier's inputs differential output definition unity. original model, this unity gain, gain-normalized operating condition Q1/Q2 provided inclusion emitter resistances, RE1/RE2. These resistors force differential topology this gain (once given current IEE). This gain normalization step adds great usefulness model, simplifying design expressions slew rate gain bandwidth product. result, leads substitution other input devices within this architecture with relative ease. Speaking more broadly, input stage gain-normalization step provides specifically implementing variants structure, without major topology changes. noted, original paper allowed bipolar pairs basic design equations. However, model topology viewed more generally, fundamental fact about that virtually differentially operated transconductance pair used front end. From signal point (the differential outputs Q1/Q2),
4.4k
4.4k 4.6pF
52.7
52.8
2.4k
2.4k
27.5E-6 BASIC BOYLE MODEL IEE/C2 (FOR R02) 1/(2 (IS1/IS2)
NODE (GND) DEFAULT COMMON SPICE. EXTENDED JFET MOSFET ISS/C2 R02) 1/(2 VT01- VT02
LTAN48 TA02
Figure Input Gain-Normalized Macromodel
AN48-4
Application Note
remaining path model essentially same, with basic design equations holding. example, case PFET type amplifier, Q1/Q2 replaced Pchannel FETs J1/J2; PMOS types, they become devices M1/M2, With other variations this type macromodel topology, provisions made transconductance adjustments stage, such that differential pair used operates unity gain. This either through transconductance parameters transistors themselves, associated degeneration resistances (RS1/RS2 devices would correspond RE1/RE2 bipolars). course, whatever type transconductance devices used, suitable biasing steps must made. Note that this general concept allows many variations original Boyle model exist. basic Boyle model design equations Figure then viewed dictate model's performance. This easily extended include various types mentioned. example, shown extended equations, PFET PMOS expression will follow same form, with replacing IEE. corresponding expression these amplifiers similar, with substituting RC1. creating different input stage amp, different input transistor types accommodated SPICE transistor model parameters J1/J2, M1/M2, etc. specific transistor model parameters these devices then determine amplifier input VOS, IOS. While this input stage gain normalization step makes input flexible, does have basic trade-off. Because input transistors operated current/gain levels generally unlike those used actual amp, noise properties generally uncorrelated (note that noise will have very high voltage gain first stage, distinctly unlike this model). result this, input noise performance gain-normalized model will usually track real accurately. Please note however that this factor unique Boyle type models, just true other models with input stage gain normalization. APPROACH SPICE MACROMODELS approach macromodels been aimed towards achieving design improvements within models, with balanced array simulation enhancements. Attention been directed towards practical, useful macromodels which emulate catalog devices both their specifications well general functionality. This approach been rooted building Boyle macromodel topology, enhancing where appropriate. degree another, this been done each case family four amplifier macromodel topologies supported. macromodels produced original form appropriate member from family macromodel programs. These programs implement algorithms otherwise support features customized macromodels. given program, output consists SPICE compatible ASCII file, form specific macromodel. With this approach, macromodels produced virtually fast spec sheet definition data keyed noted, program produces ASCII macromodel, Figure header portion sample macromodel produced programs. Note that header includes information form SPICE comment lines (those lines* prefixed), addition actual code macromodel itself. this case header LT1022 (top line). line two, date/time stamp general model type listed. next four lines specs used within model recorded. This information comprises macromodel specifications, format generally consistent across four families
Linear Technology LT1022 model Written: 05-10-1990 15:08:03 Type: PFET input, internal comp. Typical specs: Vos=1.0E-04, Ib=1.0E-11, Ios=2.0E-12, GBP=8.0E+06Hz, Phase mar.= deg, (low)=2.5E+01V/us, (high)=5.0E+01V/us, Av=112.0dB, CMRR= 92.0dB, Vsat(+)=1.8V, Vsat(-)=1.8V, Isc=+/-30mA, Rout= 50ohms, 5mA. (input clamp *optional*) LTAN48 TA20 Connections: V+V-O
Figure Header Portion Sample
AN48-5
Application Note
RNLB CXC1 DSUB RXC2 RXC1 RPLA
DDM4 DDM2 DDM3 NOTES: INPUT ELEMENTS CIN, RB1/2, DDM1/2/3/4 WILL VARY WITH DEVICE. (NET) CONNECTS CA/CB EXT. COMP. DEVICES. COMPENSATION ELEMENTS (NET); (NET) SHOWN EXTENDED FORM. OUTPUT LIMITING WILL VARY WITH DEVICE. DOTTED CIRCUITRY INDICATES ENHANCEMENTS. DDM1 GCMVE GAVA GPLVP GNLVP GPLVP 100k
CXC2
100k GBVB
RNLA
RNLB
LTAN48 TA03
Figure Bipolar Input Macromodel (Simple)
macromodel types. optional comment line completes main part header. macromodel header conveniently documents actual working parameters model. Obviously, programmed approach efficient method generating revised macromodels release public. also important additional feature that allows application engineers quickly respond field requests custom macromodel values parameter modeled. MACROMODEL FAMILY previously noted, macromodel families comprised four types models. There models bipolar input devices, P-channel JFET input devices, PMOS input devices. While there similarities across these four macromodel types, there also unique distinctions within each. follow-
sections detail each these macromodel types, illustrating common overall features well those unique each type device. Bipolar Input Macromodels Listing (see listing application note) macromodel LT1007 bipolar amp, which generally corresponds directly complete macromodel schematic Figure clarity, schematic shown forms; "simple" form Figure uses symbolic connections, while "detailed" form Figure follows actual listing. This schematic appears busy, because fact that shows possible options this topology. While
Note This generic schematic values this case, will those other amplifiers. Instead, actual values device under discussion noted model listing.
AN48-6
Application Note
DSUB
RPLA RPLB
RXC2
RXC1 CXC1
CXC2
DDM4
DDM2 DDM1 DDM3
RNLA RNLB
NOTES: INPUT ELEMENTS CIN, RB1/2, DDM1/2/3/4 WILL VARY WITH DEVICE. (NET) CONNECTS CA/CB EXT. COMP. DEVICES. COMPENSATION ELEMENTS (NET); (NET) SHOWN EXTENDED FORM. OUTPUT LIMITING WILL VARY WITH DEVICE. DOTTED CIRCUITRY INDICATES ENHANCEMENTS.
LTAN48 TA04
Figure Bipolar Input Macromodel (Detailed)
possible options need present within given device, most them fact used case LT1007. With regard schematic shown, many device specific conditional details which this macromodel handle will discussed this context. very front model, there optional differential input clamp diodes, with without series resistance, etc., similar comments apply CIN. These model enhancements employed specifically closely mimic device characteristics. example, with (real) LT1007 OP-27 type device shown, pair twodiode differential clamps used, DDM1-DDM4, without series resistance (RB1 These options
(and others) shown dotted Figure suggest multiple possibilities, will vary from device type another. Other enhancements used power consumption current source mimic current drain, reverse substrate diode, DSUB (which also given breakdown voltage simulate maximum supply voltage). Overall, general intent make macromodels behave more their real counterparts, these other functional details. Throughout this macromodel main signal flow path shown heavy lines, clarity. Controlled sources function they Figure passive components RO2, noted, both
AN48-7
Application Note
expanded from original Boyle single capacitor, more complex optional network(s). LT1007 uses both these networks, simulate multiple polezero roll-off characteristic actual device. This covered more detail following section, with performance examples. output stage this model entirely vis-a-vis Boyle model, discussed following section terms current/voltage limiters. Because reduced value used RS), small signal output resistance this model will usually dominated value RO2. This turn makes value higher, compared basic Boyle model, also makes larger (for same gain). limiter with series diodes similar offset voltage source threshold. however; fact local closed loop system, which depletes total current available from source when output voltage limit threshold reached. This allows clean limiting, with large internal currents. buffered biased diode resistance RPLB used control leakage D3B, which would otherwise cause gain errors amplifier LT1007/OP-27 family. This voltage limit technique found justified most amps with gains 120dB more. With active, LT1007's 150dB gain reached within fraction Current limiting this model symmetrical, that same current limit level both source sink currents. This typical amplifiers which bipolar output stages. CMOS output stages often asymmetrical, modified form this current limiter will shown under discussion PMOS input amplifier types. minimize loading effects current limiter, uses dedicated floating differential input buffer amplifier, ECL. This VCVS senses voltage drop across RS), which directly proportional output current. current limit threshold defined gain ECL, characteristics RCL, GCL. this instance, local loop closed when amplified output drives RCL, through either true case voltage limiter, when limit threshold reached controlled source this case GCL) depletes available current from Again, this allows clean current limiting, with large internal currents being produced. Because buffering ECL, this type current limiter very errors when below threshold. only errors with regard gain degradation, current limit very accurate. There also much more subtle advantage common these limiters, that fact that they achieved parallel feedback path. such, they will definition transparent below threshold, point already made above. However, useful side advantage this that this macromodel along quite well truth
Improved Voltage Current Limiting
original Boyle model Figure bias voltages along with diodes were used provide brute-force type output voltage limiting. While workable, this scheme produces large internal limit currents within model. also give rise gain errors very high gain precision amplifiers, parasitic diode leakages below limiter threshold. maximum output current simulation, diodes Figure provide current limiting indirectly sensing voltage drop across (the controlled source produces replica output voltage across which effectively places D1/D2 parallel with RO1). When conduct start limiting, this also produces very large currents limit, well some gain degradation below threshold. many macromodels, implemented forms voltage current limiting. These schemes buffered biased diodes, which allow both full amplifier gain below limit thresholds, well accurate limit thresholds output voltage current. They described now, used only within many macromodels, throughout family models. Voltage limiting model Figure described either negative positive swing, they similar. positive swing limiter, which composed D3A, D3B, RPLA, RPLB GPL, will described. This setup would appear first modified brute-force
AN48-8
Application Note
without either limiter (for special cases). fact, they disabled signal purposes very simply, commenting controlled source driving either GPL, GNL, GCL. This come handy, should ever necessary troubleshoot circuit and/or model errors.
Caution! Those tempted this should course know what they about! bear mind that macromodel without limiters capable very high voltages and/or currents! Perhaps more significant bonus this limiter design scheme that special "turbo" forms given model saved, such LT1007 model sans limiters. This will greatly speed analyses, long external circuit provides proper loop closure. device uses bias current compensation, model accounts this simply with higher remaining models used LT1007 diodes used various locations, with scaled specific use.
Phase/Frequency Response Extensions
performance area where modeling recently received strong attention regard frequency response. original Boyle model Figure dominant pole secondary pole Many amps popular have much more complex phase/frequency response. result, using basic Boyle model topology simulate their transient response inaccurate some applications. Solutions modeling additional poles zeros range from simple complex, depending upon what overall trade-off model designer chooses. example, number sequential pole/zero stages added model very fine emulation small signal transients. practice, this approach needs weighed carefully overall basis. under question here that possible greatly improve upon simple Boyle type models' phase/frequency response. However, what macromodel user needs know just response improved, also what price paid results worth possible drawbacks, specifically potential penalties terms additional memory required, longer simulation times, possible convergence issues. course these considerations basic, applicable model, types included. Nevertheless, should noted that these types problems exaggerate very quickly with multiple amplifier simulations (such active filters). entirely possible create more complex models which will even larger multi-amp circuits, when used standard environments with modest memory (~500K). Alternately, intermediate approach modeling some additional poles zeros taken, simply extending above mentioned compensation caps basic Boyle model with additional network elements.
Macromodel Embedded Models
bottom each macromodel listing section titled MODELS, which does fact define those transistor, diode, other models used local macromodel. case LT1007 amp, models Q1/Q2 are, noted, different terms (current gain), following reasons. VOS, input offset voltage amplifier input pair, modeled using slightly different transistor models, QM2. ratio their saturation currents will produce offset voltage, VOS, which kT/q* ln(IS1/IS2) With ratios shown Listing this produces typical 20µV offset LT1007C. Bias offset currents modeled using different input pair halves, IC1/(IB (IOS/2)) IC2/(IB (IOS/2)) values shown those which correspond currents 15nA 12nA (again LT1007C). gains listed appear high, however this by-product fact that actual LT1007
AN48-9
Application Note
25.30 25.20 25.10 (mA) 25.00 24.90 24.80 24.70 TIME (ms)
LTAN48 TA05
(r3) (r3)
V(55) 13.5
(mV)
V(55)
LTAN48 TA06
Figure LT1007 Test (Open Loop, ±15V)
(55) -VdB (50,51) Vp(55) -Vp(50,51) -180
Figure LT1007 Test VSAT ±15V)
V(55)
(mV)
100M FREQUENCY (Hz)
LTAN48 TA07
-100 TIME (µs)
LTAN48 TA08
Figure LT1007 Test Gain/Phase
Figure LT1007 Test Transient Response
Figure Composite Performance Points
this approach that used Figure RXC1/ CXC1 added extension, while RXC2/ CXC2 added. Speaking generally, these partspecific options, with defaults (i.e., extensions used) only course LT1007 under discussion full used, noted Listing contrast arbitrary additional pole/zero stages, this method viewed relatively limited, which truth However, advantage minimal added complexity, active stages added model. also fundamental virtue working well within overall Boyle topology, since extension Together, these controls allow more complex frequency responses simulated without additional active stages, with result minimal simulation overhead increases. model examples which LT1007/
LT1037 families, LT1028 LT1115, OP-27/ OP-37 families, option available with device families.
Macromodel Performance this point, some sample macromodel performance will shown illustrate points. these following SPICE displays, macromodels used were taken directly from current released diskette. purposes this application note, models were edited into form listings shown herein editing only header copyright notice sections brevity). These files were then used various simulations. Unless specified otherwise, test circuits ±15V power supplies, model tested input node (50), input node (51),
AN48-10
Application Note
output (55), signal source applied node (2). Unless otherwise specified, SPICE option default changes were made files used tests. 16MHz compatible computer used under 4.01, along with MicroSim's PSpice version 4.03 (DOS version). ramdisk used work disk simulations.
picture series Figure composite form illustrates various performance points LT1007 macromodel. terms limiting schemes employed, they shown Figure tests LT1007 display short circuit current, test operates amplifier comparator (open loop) ±15V supplies, with output driving value resistor (10). display dual trace load current I(R3) mirror -I(R3). This allows both current limits shown here, expanded scale. noted, both limits well within design current limit 25mA. display output voltage saturation, amplifier connected unity gain inverter ±15V supplies, driven with -18V +18V ramp. This overdrives amplifier input/output more than ±13.5V, extremes input sweep used evaluate output saturation. Both extremes display offset nominal limiting voltage ±13.5V, error shown expanded around zero, with range ±1%. Both limits well less than terms error. Gain phase response this particular model interesting, clearly shows effects C1/RXC1/ CXC1 C2/RXC2/CXC2 extensions frequency response. Shown Figure test composite plot inverting mode gain/phase operating with ±15V supplies. load resistance varied parameter, steps 100k, 10k, shown, gain varies slightly around nominal 146dB various loads, would expected output resistance. phase response shows multiple pole/zero characteristic just before unity gain crossover point, does real LT1007. While macromodel display dramatic terms phase change data sheet, still effective purpose. Figure test small signal transient test with LT1007 connected follower, emulating corresponding data sheet photo. test deceptively simple one, most would think voltage follower fairly straightforward circuit. Actually, real stress test macromodel, terms potential problems with convergence, memory usage, required simulation time, This particular simulation runs without mishap whatsoever, about 16MHz clone, using PSpice 4.03, with tweaking SPICE defaults. also runs with apparent problems demo simulations distributed SPICE macromodel diskette (using demo PSpice version 3.06).5 These performance tests summarize those aspects LT1007 macromodel previously discussed design features. should kept mind that many them also appear other models well, they will necessarily repeated with subsequent examples. Bipolar Input Macromodels With bipolar input stage amps, distinct application functional difference that they often designed single supply operation, often with supplies less. addition, they also designed micropower applications, with current drains 100µA amplifier, even less. large number such amplifiers, with macromodels supporting them using either model topologies. macromodels are, some senses, similar those using model topology. While true that there similarities, since both based Boyle model, there also many practical differences. Speaking those beyond obvious polarity differences, unique distinctions largely functional characteristics various amplifiers modeled. And, they turn brought about single supply and/or micropower operational features previously mentioned. These differences thrust modeling enhancements.
LT1013 Family Macromodels
terms historical accuracy, family SPICE macromodels amps beginnings 1988,
Note "DEMO1007.CIR" file SPICE diskette invites users this "simple" transient test with other models, compare relative performance. revealing such seemingly innocent test.
AN48-11
Application Note
with release macromodels input amps LT1013 LT1014.6 These models actually their roots MicroSim Parts program, Listing macromodel LT1013/LT1014, version available today. Close akin derivative models LT1013A LT1013D. Also related this model those LT1006 family, including LT1006, LT1006A, LT1006S8. enhancements that these models offer over original Parts version three-fold: Further discussion performance examples this specific model type found Design Note
LT1078/LT1178 Families Macromodels
More recent examples bipolar input amplifiers micropower families, 45µA quiescent current/amplifier LT1078, LT1079, LT1077; lower power (15µA quiescent) LT1178 LT1179. Figure dual schematic macromodel topology used these types amps. simulates those features previously noted, discussed below. purpose minimum repetition, only features which differ from models previously discussed addressed here. Figure simple version, while Figure shows detail, like actual macromodel listing. single supply amps have distinction input phase reversal protection since introduction LT1013/LT1014. This also includes more recent devices such LT1078 LT1178 families. simulation this macromodel, diodes DCM1 DCM2 provide
input common mode clamping circuitry
(DCM1/DCM2 VCMC);
different models input transistors
Q1/Q2 (which allows input bias offset currents, well offset voltage simulated);
Three controlled output saturation characteristic when operating near negative supply rail.
Note Jung, LT1013 Macromodel," Linear Technology Design Note July, 1988.
DSUB
DCM1
DCM2
GCMVE GAVA
V110
RO2B
RO2A
GBVB
VCMC
ECV110
NOTES: INPUT CLAMPING ELEMENTS RB1/2, DCM1/2, VCMC WILL VARY. MICROPOWER DEVICES HAVE ADDITIONAL NETWORK, RO2B/D5/D6. COMPENSATION ELEMENTS C1/C2 EXTENDED.
LTAN48 TA09
Figure Bipolar Input Macromodel (Simple)
AN48-12
Application Note
DSUB
DCM2
RO2B
DCM1
RO2A
VCMC
NOTES: INPUT CLAMPING ELEMENTS RB1, RB2, DCM1, DCM2, VCMC WILL VARY MICROPOWER DEVICES HAVE ADDITONAL NETWORK, RO2B, ROD5, ROD6. COMPENSATION ELEMENTS EXTENTED.
LTAN48 TA10
Figure Bipolar Input Macromodel (Detailed)
negative range input common clamp, voltages applied Q1-Q2 inputs. With diodes referenced slightly positive common mode clamp voltage, VCMC, they reverse biased normal voltages. Note that perspective here with regard negative supply rail, which also negative limit single-supply use. customizing macromodel, inclusion exclusion clamp diodes option, RB1/RB2 current limit resistor value, VCMC. these single supply devices, VCMC typically 0.4V, which allows linear common mode response hundred below ground, just like actual devices. Without this network, LT1078 macromodel will (mis)behave just like typical 324/358 amplifiers, with input stage saturation when inputs taken below GND. This will evident uncontrolled sign reversal output, hard positive rail saturation. feature added this model specifically micropower devices extra output network, RO2B D5/D6. ordinary dual supply applications, even
single supply uses where close simulation output voltage saturation highly critical, this network isn't needed. However, single supply amps such input devices which feature active pulldown linear negative swing operation, simulation within negative rail entirely possible. properly simulate this, model which displays characteristics similar real device when sinking current needed, which function this network.
LT1078 Macromodel Performance
LT1078 device which illustrates previously mentioned performance points. model, shown Listing compared schematic Figure actual values. composite pictures Figure illustrate various performance points. terms protection, model input diode clamp works effectively, shown Figure test overdriven input, single rail follower. Here, input V(2) swept from displayed output
AN48-13
Application Note
V(55), noted, clamped 0V/4V limits, there phase reversal when input taken well below (maximum input sink current 5V/100k).
V(55)
-2.0 -4.0 -6.0 -6.0 V(2)
Figure test shows output voltage V(55) into load, test output current limit. limit levels 150mV, which corresponds ±15mA, specified model. This display also shows effects RO2B/D5/D6 Class output stage used model, evident multiple slope rise/fall.
LTAN48 TA11
-4.0
-2.0
Figure LT1078 Test Supply, Overdriven Follower
V(55)
-100
single supply micropower amp, more difficult aspects model performance lies simulating supply rail saturation, while retaining micropower performance relatively high maximum current output. LT1078 typical supply current only 45µA, output resistance Yet, device also deliver ±15mA (just demonstrated). macromodel, output Class network allows concurrent micropower small signal characteristics, well this relatively high maximum current. importance small signal characteristics come play single supply applications, where output stage called upon sink current output voltages near rail). finer details output current sinking near negative rail shown Figure test This test voltage follower, with input V(2) swept from output stage model required sink 100µA, when output voltage V(55) close GND. noted, model linear with voltages above 100mV. lower voltages, saturates about 80mV while sinking 100µA, does real LT1078. P-Channel JFET (PFET) Macromodels
(mV)
-200 TIME (ms)
LTAN48 TA12
Figure LT1078 Test (Open Loop, ±15V)
(mV)
V(55)
V(2)
V(50)
-100 (mV)
LTAN48 TA13
Figure LT1078 Test Negative Saturation Characteristics Figure Composite Performance Points
Historically speaking, both junction MOSFET transistor types within Boyle type macromodel topology described Krajewska Holmes, early enhancement Boyle model.7 Krajewska topology modified Boyle type model with either type replacing bipolars original model. This enhancement took advantage gain-normalization referred previously.
Note Krajewska, Holmes, F.E., "Macromodeling FET/Bipolar Operational Amplifiers," IEEE Journal Solid-State Circuits, Vol. SC-14, December 1979.
AN48-14
Application Note
Junction input amps make important part overall field amps, they capable both medium higher speed performance have errors. modeling factors, chosen realize JFET amplifier type, specifically P-channel (PFET) input stage types, with part specific enhancements PFET macromodels. PFET macromodel shown schematic form Figures (simple detailed respectively). overall basis this model fundamentally similar that Krajewska, several adaptations added. fact become more complex models library, when features used. following discussions highlight various enhancements beyond basic Krajewska form Boyle model. Those model improvement areas previously discussed will covered detail. actual macromodel LT1056 representative PFET amp) shown Listing
PFET Macromodel Features
input side PFET macromodel J1/J2 front end, which number options possible within this stage. Input capacitance simulated CIN, series gate resistances RG1/RG2 optionally added. optional buffered clamping network around DCM1DCM4 quite complex, warrants some discussion. This circuit simulates anti-phase reversal common mode clamping present most (but all) PFET input amplifiers. actual parts which this clamp becomes active whenever input voltage approaches within less) negative supply rail. This prevents sign inversion typically seen most PFET input amps, when negative range exceeded.
RNLB
GOSIT
NOTE
RPLA
DSUB RXC2
CXC1
RXC1
CXC2
VCMP VCMN DCM3 DCM1
GCMVS GAVA GPLVP GNLVN GCLVI 100k
DCM4
DCM2 RCMN
GBVB
ECMNVCMN VCMC
ECMPVCMP
VCM2
ECLVCL
RNLA
NOTES: SECTIONS SHOWN DOTTED OPTIONAL. OUTPUT VOLTAGE/CURRENT LIMITING VARY. OPTIONAL CONTROLLED SOURCE ASYMMETRY. SOURCE RESISTANCE RS1/RS2 OPTIONAL. COMPENSATION ELEMENTS C1/C2 EXTENDED. RNLB
LTAN48 TA14
Figure P-Channel JFET Macromodel (Simple)
AN48-15
Application Note
GOSIT NOTE DSUB
RPLA RPLB
ECMP
DCM3 RCMP RCMN DCM4 DCM2 DCM1
ECMN
VCMC
VCM2
RNLA RNLB
NOTES: SECTIONS SHOWN DOTTED OPTIONAL. OUTPUT VOLTAGE/CURRENT LIMITING VARY. OPTIONAL CONTROLLED SOURCE ASYMMETRY. SOURCE RESISTANCE RS1/RS2 OPTIONAL. COMPENSATION ELEMENTS C1/C2 EXTENDED.
LTAN48 TA15
Figure P-Channel JFET Macromodel (Detailed)
circuit appears moderately complex, necessity. high performance this macromodel, clamping diodes DCM1 DCM3 bootstrapped, lowest leakage. VCVS followers ECMP ECMN, through resistances RCMP RCMN, reduce voltage seen these diodes zero potential inputs where clamp active. This necessary preserve bias currents J1/J2, normal operating range voltages (when clamp back biased). other words,
clamp must clamp effectively below voltage threshold, must introduce leakage errors which would ruin bias current characteristics seen input(s). Actually bootstrapping quite effective, with DCM1 DCM3 introducing less error. noted, this circuit option with PFET input amplifiers which employ type topology, which includes LT1056, LT1057, LT1058, LT1022, older
AN48-16
Application Note
industry standard parts such LF156-LF356 series, OP-15/OP-16 series, related duals. Since clamp circuit only needed simulations which need explore overvoltage inputs, comes commented within respective model files. P-channel JFETs J1/J2 have individual model characteristics calculated yield input stage unity gain, gate currents consistent with IB/IOS amplifier modeled, characteristics amp. these defined models JM2, respectively. gain-normalization input stage, JFET transconductance parameter BETA adjusted J1/J2, provide unity gain. Alternatively, source resistances RS1/ used gain normalization. This option that exercised time model created interest simplicity however, present models these resistances). modeled simply difference models. subtle detail which obvious (optional) voltage source VCM2, which appears within LT1056 model (and similar topologies). This bias voltage simulates negative input range change VOS, characteristic these amplifiers. inner stages model, overall gain frequency response capability characteristics similar prototype discussed previously, extensions both optionally used. These extensions used with LT1056. noted discussion gain-normalization, basic equations which govern this model quite close original Boyle expressions, with adaptations different circuit references. These summarized Figure Figure model tail current most simple JFET amplifier cases. However, many P-channel JFET amps just simple cases, sense that they don't slew symmetrically. asymmetric slewing JFET amplifiers, optional circuitry used described detail Appendix, employs VCCS GOSIT, connected shown. JFET amplifiers which have symmetric characteristics more straightforward signal path, where simply ISS/C2. remainder this model (the output stage with enhanced voltage/current limiters) similar macromodel.
PFET Macromodel Performance
performance LT1056 device, illustrated composite pictures Figure shows many behavior points this model type. rather unique aspects 355/356 other family relation PFET amps asymmetrical slewing. With LT1056, this pattern behavior shown Figure test This test, voltage follower ±15V supplies, slews twice fast negative going swings positive. measured rates +14V/µs, -28V/µs, SPICE result here compares well with data sheet. This transient test runs around 25s, with minor PSpice power supply ramping find bias point.8 command node minimized bias iterations, essential). demonstration voltage clamping circuit effect input currents shown Figure test this test LT1056 overdriven voltage follower, with sweep input -15V +15V. three part display shows input/output linearity (left), amplifier bias current (middle), clamping current circuit's input resistor (right). this specific test, LT1056 model edited uncomment "CMCLAMP" section activate limiter. left plot Figure test LT1056 shows only errors gain until limits reached. Note that positive limit LT1056 output swing limit positive 13.2V (the negative output limit -13.2). However, negative range limit this follower input clamp, occurs nearly sooner, just under -11V. This clamp threshold (relative -15V). middle plot, bias current stable
Note PSpice simulator used these tests internal bias point seek algorithm convergence. This routine lowers/raises supplies find suitable biasing condition circuit. necessity this will vary circuit circuit, general amplifier circuits with initial input conditions which start some extreme (such -10V, this case) slower biasing. ".IC" command used minimize this, desired.
AN48-17
Application Note
V(55)
TIME (µs)
LTAN48 TA16
Figure LT1056 Test Asymmetric Slew Rate
V(2) -V(55) (XU1. 1.0mA (R1) -50E -12)
(mV)
(pA)
-0.5
-1.0
1.0pA
LTAN48 TA17
Figure LT1056 Test Input Clamp, ±15V, Overdriven Follower Figure Composite Performance Points
over this range, indicating that overall follower loop active. right plot, current input resistor displayed entire input dynamic range. only within range where amplifier operating linearly, then rises rapidly about 400µA, clamp takes over. P-Type MOSFET (PMOS) Macromodel Family PMOS input macromodel shown schematic form Figures 10B, representative model LTC1050 shown Listing Like close-cousin PFET amplifier model Figure this PMOS model resembles corresponding model Krajewska,9 with regards some aspects input stage.
What been said model Figure generally true when PMOS transistors used (M1/M2 Figure replace J1/J2 Figure With this PMOS adaptation, diodes simulate bias currents device opposed fixed current sources Krajewska model). true JFET transistor models, model parameters these diodes provide IB/IOS characteristics. previously, simulates amplifier input capacitance. this PMOS input macromodel much remainder overall model similar, little changes
Note Krajewska, Holmes, F.E., "Macromodeling FET/Bipolar Operational Amplifiers," IEEE Journal Solid-State Circuits, Vol. SC-14, December 1979.
AN48-18
Application Note
RNLB DMG1 DMG2 DSUB RXC2 CXC1 CXC2 RXC1 GCMVS GAVA GPLVP GNLVN GCLVI 100k GBVB RPLA
ECLVCL
NOTES: SECTIONS SHOWN DOTTED OPTIONAL. OUTPUT VOLTAGE/CURRENT LIMITING VARY. SOURCE RESISTANCES RS1/RS2 OPTIONAL. COMPENSATION ELEMENTS C1/C2 EXTENDED.
RNLA
RNLB
LTAN48 TA18
Figure 10A. PMOS Macromodel (Simple)
equations (refer Figure again). Practically speaking, variation PMOS input stage model allows such useful device categories very chopper-stabilized units.10 Accurate rail-rail output limit characteristics also allow features single supply CMOS technologies realistically modeled.
PMOS Macromodel Features
area where emphasis fidelity actual devices influences model found this PMOS macromodel. While fact more complex, reason better match real parts. But, vendors
Note These models emulate actual chopper amplifiers terms ultra offset, high gain, also terms single (low voltage) supply operation, input/output ranges, etc. However, there actual commutation function, therefore effects clocking parasitics actual device aren't modeled.
haven't taken such steps modeling amps with PMOS inputs CMOS outputs. example, inspection some models released show such obvious deficiencies input transistors unlike what part actually modeled, and/or lack close attention output limiting levels. Obviously, such models can't simulate input output ranges with high degree fidelity, even though these factors critical single supply use. output current/voltage limiters used with PMOS model more complex form shown because several important performance issues. example, amplifiers emulated these PMOS models have rail-rail outputs, with level saturation voltages typical CMOS outputs. amplifiers also have 160dB gains, 140dB CMRRs, sub-microvolt levels, typical chopper stabilized amps. Many these performance characteristics made possible some model
AN48-19
Application Note
DMG1 DMG2 DSUB
RPLA RPLB
VOD1
VOD2
RNLA RNLB
NOTES: SECTION SHOWN DOTTED OPTIONAL. OUTPUT VOLTAGE/CURRENT LIMITING VARY. SOURCE RESISTANCES RS1/RS2 OPTIONAL. COMPENSATION ELEMENTS C1/C2 EXTENTED.
LTAN48 TA19
Figure 10B. PMOS Macromodel (Detailed)
features shown Figure such already discussed improved voltage limiters, very saturation voltages with minimal gain error. current limiting this model also some unique performance issues. Most current limit schemes used within macromodels symmetrical regarding sinking/sourcing output current, previously described macromodel limiter. most part this problem, since most amps also have symmetric limits.
However, some amplifier types limit symmetrically all, have skew times between sinking/sourcing current levels. case point those amplifiers which have CMOS common drain outputs, where upper device source less current than lower device sink. example LTC1050 under discussion source current, while sink 20mA. improved modeling method current limiting allows different degrees asymmetry incorporated.
AN48-20
Application Note
circuits Figure output current sampled value series resistor, RSO, typically current proportional voltage drop across scaled VCVS ECL, which course eliminates possible loading effects output. noted with model, this technique fact developed remove loading effects brute-force limiting, which cause gain errors very high gain amplifier such LTC1050. While being modeled with gain more than 120dB subject limiter-related loading errors, chopper-type amplifiers where gains typically 160dB more, become critical. Along with value RSO, gain plus diodes D1/D2 voltage sources VOD1/VOD2 selected provide separate ±current limit thresholds. gain common both current limits, voltage sources adjusted reflect desired threshold sinking/sourcing current. LTC1050 model, source sink currents 20mA, respectively. Should there model case equal currents, then diodes same voltage sources dropped.
V(2) V(55)
-0.5
-1.0 V(2) V(55)
(mV)
-6.0 -5.0 -4.0
-3.0 -2.0 -1.0
LTAN48 TA21
PMOS Macromodel Performance
performance LTC1050 illustrated composite pictures Figure test which demonstrates rail-rail response characteristics shown Figure test conditions this test unity gain inverter with single supply +5V, driven with input sweep +1V. This deliberately overdrives amplifier both dynamic range extremes. plots show input/output error highly magnified, relatively sensitive test saturation near rails. upper trace shows general behavior, while bottom trace shows error ±10mV scale. Even expanded scale input/output error hard see, about 12mV with output 100mV from either rail, 500µV 200mV, 12µV 300mV, essentially level lower voltages. noted previously, unique feature PMOS macromodel type ability have different ±output current limits. With LTC1050 model tested, this asymmetrical limiting shown Figure test this test conditions open loop comparator with
Figure 11A. LTC1050 Test Input/Output Linearity, Mode
I(R3)
(mA)
TIME (µs)
LTAN48 TA22
Figure 11B. LTC1050 Test ±5V) Figure Composite Performance Points
supplies load. noted, current load resistor +5mA/-20mA. Examples amps using this PMOS model LTC1050 series, related parts chopper stabilized family.
AN48-21
Application Note
REFERENCES Boyle, G.R., Cohn, B.M., Pederson, D.O., Solomon, J.E., "Macromodeling Integrated Circuit Operational Amplifiers," IEEE Journal Solid-State Circuits, Vol. SC-9, December 1974. Solomon, J.E., "The Monolithic Amp: Tutorial Study," IEEE Journal Solid-State Circuits, Vol. SC9, December 1974. Krajewska, Holmes, F.E., "Macromodeling FET/ Bipolar Operational Amplifiers," IEEE Journal SolidState Circuits, Vol. SC-14, December 1979. Jung, LT1013 Macromodel," Linear Technology Design Note July, 1988. Jung, SPICE Macromodel LT1012," Linear Technology Design Note November, 1989. Jung, "Questions Answers SPICE Macromodel Library," Linear Technology Application Note April, 1990. "LTC Macromodel Library Miscellaneous SPICE Files," available 5.25" 3.5" diskettes from: Linear Technology Corporation, 1630 McCarthy Blvd, Milpitas, CA., 408-432-1900. Jung, "Using Macromodels," Electronic Products, June, 1990 Jung, "Models Mimic Behavior Real Amps," Electronic Design, October 1990. Jung, "Using Macromodels," Electronic Engineering, November, 1990. Nagel, L.W., Pederson, D.O., "Simulation Program with Integrated Circuit Emphasis (SPICE)," University California Berkeley, ERL-M382, 1973. Nagel, L.W., "SPICE2: Computer Program Simulate Semiconductor Circuits," University California Berkeley, ERL-M520, 1975. Cohen, "Program Reference SPICE2, University California Berkeley, ERL-M592, 1976.
SPICE documents available from: EECS/ERL Industrial Support Office, Cory Hall, University California Berkeley, Berkeley, 94720
APPENDIX Improved JFET Model Slews Asymmetrically SPICE macromodels amps have been available some time, both bipolar(1, JFET(3) input stage device types. Interestingly however, much attention been given models available controlled slewing asymmetry. Dependent upon given amplifier design topology, large signal characteristics have various degrees slew rate (SR) asymmetry. therefore makes good sense have models which emulate real parts this regard. case point that available P-channel JFET input amps, many which have characteristic response which asymmetrical. fact, popular amps with topologies like original 355/356 types intrinsically faster negative going output swings than they positive. Similar comments apply such related devices OP-15, OP-16, etc. Since this type JFET device topology introduced, specified data sheet typically been lower dissimilar rates, i.e., slower, positive edge Thus, given with typical spec 14V/µs positive going edges, same will have corresponding negative about 28V/µs. Ironically, this quite common JFET amplifier slewing characteristic been well modeled thus far. Most macromodels currently available simply address asymmetric issue all. Others have means modeling seldom found used. means control built into original Boyle(1) model, addresses asymmetry common mode
AN48-22
Application Note
(CM) signals means common emitter (source) capacitor, (CS, JFET amps). However, using this capacitor alone general symmetry control mechanism leaves something desired, resulting slopes consistent. implemented means modeling asymmetry, shown Figure
(CE) GOSIT
produces current which adds/subtracts to/from fixed current, ISS. resulting current available charge/discharge compensation capacitor thus higher slewing slope than opposite. This true regardless whether amplifier operating inverting non-inverting input mode. option, still used further control slewing inputs (shown dotted). generating macromodel with asymmetrical lower slew rates input from data sheet. Also input ratio high-to-low Algorithms program used then calculate appropriate static value gain VCCS GOSIT, that proper slewing characteristic will produced model. representative example with these characteristics LT1056, high performance topologically much like LF156-LF356 OP-16 types (also produced LTC, with corresponding macromodels available). Some sample lines code taken directly from released LT1056 model shown below. These shown both asymmetric form released, (edited) symmetric case. Actually, only SPICE model element added produce asymmetric opposed symmetric, that VCCS, GOSIT. LT1056 example just below, taken from released library, produces +14V/µs -28V/µs, respectively. CLAMP 1.5000E-11 5.6000E-04 GOSIT 2.8000E-04 INTERMEDIATE When controlled source GOSIT omitted, model reverts simple symmetric slewing, where will ±(ISS)/C2. This shown below, with adjusted (symmetric) 14V/µs. Those lines code edited shown below bold. CLAMP 1.5000E-11 (symmetric) 14V/µs,
VOUT
EQUATIONS ASYMMETRIC SLEWING MODEL PARAMETERS INPUT: DATA SHEET (LOWER TWO) RATIO HIGH/LOW (TYPICAL 2/1)
1056 TYPE AMPLIFIER (356 TOPOLOGY), HIGHER 14V/ 28V/ WITH 30pF INTERMEDIATE GOSIT 14V/ 18.67V/
LTAN48 TA23
Figure Asymmetric Slewing JFET Macromodel Little Additional Complexity, Offers Controlled Slewing Response
circuit shown here simplified Boyle type model with P-channel JFET input devices, this type similar input structure) model typically used, simply ISS/C2, which symmetrical when zero. When common source capacitor added, signals adapted (corresponds Boyle paper). Unfortunately, this strategy works best amplifier inputs, well inverting inputs. method modeling asymmetrical employs added VCCS (shown dotted), which dynamically modifies total tail current available J1/J2. This controlled source, "GOSIT," driven differential output
AN48-23
Application Note
(1.4e7)*(3e -11) 420µA 4.2000E-04 comment GOSIT with first column GOSIT 2.8000E-04 INTERMEDIATE Also, similar desired, adjust BETA (only) parameter models JM1/JM2 BETA should adjusted inverse proportion change, this case 1/(420/560) 560/420 1.33 times, .MODEL 1.1000E BETA 1.267E-03 -1.000000E +00) Note again that this adjustment BETA applies both JM2, that other inline .MODEL parameters should changed. (There harm BETA changed, except GBP). non-inverting mode waveforms typical SPICE using LT1056 macromodel parallel results with actual LT1056 device shown Figure
OUTPUT
LTAN48 TA24
TIME
Figure LT1056 Mode, Macromodel
Figure LT1056 Mode, Photo
AN48-24
Application Note
Listing
Linear Technology 8741 model Written: 10-29-1990 12:55:37 Type: Bipolar input, internal comp. Typical specs: Vos=3.0E-04, Ib=2.6E-07, Ios=7.0E-10, GBP=1.2E+06Hz, Phase mar.= 73.2 deg, SR(-)=9.0E-01V/us, SR(+)=7.2E-01V/us, Av=112.4dB, CMRR=106.0dB, Vsat(+)=0.800V, Vsat(-)=2.300V, Isc=+26/-26mA, Rout= 566ohms, Iq=1.98mA. Boyle Appendix) Connections: V+V-O .SUBCKT 8741 INPUT 4.3521E+03 4.3521E+03 2.0000E-12 4.5288E-12 +2.3917E+03 +2.3917E+03 2.7512E-05 7.2696E+06 7.5000E-12 INTERMEDIATE 1.1516E-09 2.2978E-04 1.0000E+05 3.0000E-11 3.2110E+01 5.6500E+02 OUTPUT 1.0000E+00 3.2808E+01 1.0000E+00 1.0000E+01 VOD1 0.0000E+00 VOD2 0.0000E+00 1.0000E+00 2.1831E+00 RPLA 1.0000E+01 RPLB 1.0000E+03 1.0000E+00 3.6831E+00 RNLA 1.0000E+01 RNLB 1.0000E+03 1.9525E-03 DSUB MODELS .MODEL (IS=8.0000E-16 BF=5.2662E+01) .MODEL (IS=8.0928E-16 BF=5.2807E+01) .MODEL (IS=1.0000E-20) .MODEL (IS=8.0000E-16 BV=4.8000E+01) .MODEL (IS=1.0000E-16) .ENDS 8741 FINI 8741 [OAMM VN02 10/29/90]
Listing
.SUBCKT LT1007 6.6315E+02 6.6315E+02 200E-12 RXC1 CXC1 500E-12 4.000E-12 RXC2 4.00K CXC2 27.000E-12 5E-12 DDM1 DDM3 DDM2 DDM4 -2.6233E+01 -2.6233E+01 7.5030E-05 2.666E+06 1.579E-12 7.558E-10 1.5080E-03 1.000E+05 1.9176E+03 6.900E+01 2.828E+01 3.0909
AN48-25
Application Note
RPLA RPLB 3.0909 RNLA RNLB 2.625E-03 DSUB MODELS .MODEL (IS=8.0000E-16 BF=1.7857E+03) .MODEL (IS=8.0062E-16 BF=4.1667E+03) .MODEL (IS=1.000E-19) .MODEL (IS=8.000E-16) .MODEL (IS=1.000E-20) .ENDS LT1007 .SUBCKT LT1007CS X_LT1007CS LT1007 .ENDS LT1007CS FINI LT1007 FAMILY 328E-6 1.610 VLIM .MODEL D(IS=800.0E-18) .MODEL (IS=8.000E-16 BF=3.974E+02) .MODEL (IS=8.019E-16 BF=4.027E+02) .ENDS
Listing
.SUBCKT LT1078 INPUT 2.653E+04 2.653E+04 6.000E+02 6.000E+02 DCM1 DCM2 VCMC 4.000E-01 8.660E-12 4.958E+03 4.958E+03 2.412E-06 8.292E+07 1.579E-12 INTERMEDIATE 1.501E-10 3.770E-05 1.000E+05 3.000E-11 2.449E+02 OUTPUT 1.000E+02 RO2A 1.083E+03 RO2B 8.170E+02 1.490E+00 7.911E-01 4.259E-05 DSUB MODELS .MODEL (IS=8.000E-16 BF=1.992E+02)
Listing
.SUBCKT LT1013 8.661E-12 30.00E-12 EGND POLY(2) (3,0) (4,0) POLY(5) 2.475E9 -2E9 -2E9 113.1E-6 225.7E-12 12.03E-6 HLIM VLIM DCM1 DCM2 VCMC 100.0E3 8.841E3 8.841E3 4.519E3 4.519E3 16.63E6
AN48-26
Application Note
.MODEL (IS=8.012E-16 BF=2.008E+02) .MODEL (IS=3.718E-24) .MODEL (IS=8.000E-16) .ENDS LT1078 .SUBCKT LT1079 X_LT1079 LT1078 .ENDS LT1079 .SUBCKT LT1077 X_LT1077 LT1078 .ENDS LT1077 FINI LT1078 FAMILY [OAMM VP02 5/11/90] 1.0000E+00 2.9595E+00 RPLA 1.0000E+04 RPLB 1.0000E+05 1.0000E+00 2.9595E+00 RNLA 1.0000E+04 RNLB 1.0000E+05 4.4400E-03 DSUB MODELS .MODEL (IS=1.1000E-11 BETA=9.5964E-04 VTO=-1.000000E+00) .MODEL (IS=9.0000E-12 BETA=9.5964E-04 VTO=-9.998600E-01) .MODEL (IS=1.0000E-15) .MODEL (IS=8.0000E-16 BV=4.8000E+01) .MODEL (IS=1.0000E-16) .MODEL (IS=1.0000E-09) .ENDS LT1056 FINI LT1056 [OAMM VJ02 05/08/90]
Listing
.SUBCKT LT1056 INPUT VCM2 2.0000E+00 9.6458E+02 9.6458E+02 4.0000E-12 2.0000E+00 2.0000E+00 CLAMP DCM1 DCM2 VCMC 4.0E+00 ECMP RCMP 1E+04 DCM3 DCM4 ECMN RCMN 1E+04 CLAMP 1.5000E-11 5.6000E-04 GOSIT 2.8000E-04 INTERMEDIATE 1.3052E-08 1.0367E-03 1.0000E+05 3.0000E-11 7.8368E+01 4.9000E+01 OUTPUT 1.0000E+00 1.7377E+01 1.0000E+00 1.0000E+03
Listing
.SUBCKT LTC1050 INPUT 2.1221E+03 2.1221E+03 5.0000E-12 DMG1 DMG2 1.5000E-11 1.2000E-04 1.2857E-11 INTERMEDIATE 1.4902E-10 4.7124E-04 1.0000E+05 3.0000E-11 1.0664E+04 1.9900E+02 OUTPUT 1.0000E+00 1.7955E+02 1.0000E+00 1.0000E+01 VOD1 0.0000E+00
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
AN48-27
Application Note
VOD2 2.6932E+00 1.0000E+00 1.4332E+00 RPLA 1.0000E+01 RPLB 1.0000E+03 1.0000E+00 1.4332E+00 RNLA 1.0000E+01 RNLB 1.0000E+03 8.8000E-04 DSUB MODELS .MODEL PMOS (KP=1.8506E-03 VTO=-1.1000000E+00) .MODEL PMOS (KP=1.8506E-03 VTO=-1.1000005E+00) .MODEL (IS=1.0000E-20) .MODEL (IS=8.0000E-16 BV=1.9800E+01) .MODEL (IS=1.0000E-16) .MODEL DMG1 (IS=2.0010E-11) .MODEL DMG2 (IS=9.9998E-15) .ENDS LTC1050 FINI LTC1050 [OAMM VM02 5/11/90]
AN48-28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7487
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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LINEAR TECHNOLOGY CORPORATION 1991

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