Author: Peious Yoseph IC20 Data Handbook 1996 Application note

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Author: Peious Yoseph IC20 Data Handbook 1996 Application note

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AN458 Dual data pointers family
Author: Peious Yoseph IC20 Data Handbook 1996
Application note
Dual data pointers family
Author: Peious Yoseph
AN458
INTRODUCTION course redesign manufacturing process upgrade, members family have been enhanced with addition second `data pointer' (DPTR). Software take advantage additional data pointer both increase speed reduce code size. This application note starts reviewing operation original data pointer then shows data pointer fits Next, physical software identification dual data pointer parts explained. Finally, various software strategies (including assembly language, interrupts `C') taking advantage dual data pointers covered. DATA POINTER (DPTR) REVIEW original 8051 architecture, 16-bit DPTR register provides means addressing various portions memory space. instructions which DPTR address memory follows: MOVX @DPTR,A ;move data memory byte addressed DPTR MOVX A,@DPTR ;move data memory byte addressed DPTR 8051 architecture supports separate code (read-only) data memories with PSEN lines respectively. MOVX instructions access data memory (i.e., pin) which typically memory-mapped I/O. MOVC A,@DPTR ;move code memory byte addressed DPTR support read-only constants (ex: data tables, strings) MOVC instruction accesses code memory (i.e., PSEN pin) which typically EPROM. @A+DPTR ;branch address DPTR+A equal DPTR (neither DPTR changed). This often used implement `jump table' which DPTR points base table jump instructions indexed Instructions which manipulate DPTR follows: DPTR ;increment DPTR DPTR,#16 ;load DPTR with 16-bit immediate However, DPTR also manipulated virtue fact that like other registers such PSW, also accessible Special Function Register (SFR). SFRs accessible bytes variety instructions (such PUSH MOV) using `direct' addressing mode. 16-bits DPTR mapped into byte addresses, referred (high-byte, address 83H) (low-byte, address 82H). example, instruction: DPTR,#1234H ;load DPTR with 1234H functionally equivalent (but timing code size equivalent) sequence: DPH,#12H ;load high-byte DPTR (83H) with DPL,#34H ;load low-byte DPTR (82H) with
1996
Application note
Dual data pointers family
AN458
DUAL DATA POINTERS following family CPUs being upgraded with dual data pointers: 80C51, 80C52, 80C54, 80C58, 83C51FA, 83C51FB, 83C51FC, 83C575 Contact Philips Semiconductors determine dual data pointer conversion status these future products. shown Figure these upgraded CPUs still have logical DPTR, physical data pointers. References single logical data pointer (i.e., instructions that contain `DPTR' operand) mapped physical data pointers according state AUXR1 (address A2H). Similarly, references addresses (83H) (82H) access currently selected data pointer.
AUXR1#
Address RESET Value xxxxxxx0B Data Pointer Select DPTR0 DPTR1
BIT0 AUXR1
DPTR1 DPTR0 (83H) (82H) EXTERNAL DATA MEMORY
SU00816A
Figure AUXR1# Definition RESET, `0'. allow easy manipulation DPS, undefined bits AUXR1 written with value, always read Whether single dual data pointers determined runtime checking presence bit. special note 80C51 (and only 80C51) users. 80C51 with dual data pointers slightly different format AUXR1. shown Figure serves WUPD (Wake-Up from Power Down) mode selection bit. WUPD (along with DPS) RESET. Applications which power-down mode WUPD after RESET enable wakeup feature desired. defined allow easy manipulation described next section.
AUXR1#
WUPD
Address RESET Value xxxx00x0B
SU00817
Figure AUXR1# Definition (80C51)
1996
Application note
Dual data pointers family
AN458
ASSEMBLY LANGUAGE additional data pointer used speed code execution reduce code size number ways. example, many common `block' operations (such copy, compare, search, etc.) well served using data pointer `source' pointer other `destination' pointer. Block move using dual data pointers Destroys DPTR0, DPTR1, note: exits opposite entry state unless extra AUXR1 added 00A2 AUXR1 0A2H 0000 909000 DPTR,#SOURCE address SOURCE 0003 05A2 AUXR1 switch data pointers 0005 90A000 DPTR,#DEST address DEST 0008 LOOP: 0008 05A2 AUXR1 switch data pointers 000A MOVX A,@DPTR byte from SOURCE 000B DPTR increment SOURCE address 000C 05A2 AUXR1 switch data pointers 000E MOVX @DPTR,A write byte DEST 000F DPTR increment DEST address 0010 70F6 LOOP check terminator 0012 05A2 AUXR1 (optional) restore short bytes) fast clocks) manipulate AUXR1 SFR. However, note that instruction does directly force particular state, simply toggles simple routines, such block move example, only fact that toggled proper sequence matters, actual value. other words, block move routine works same whether entry. Observe that without last instruction (INC AUXR1), routine will exit with opposite state. 80C51, defined always read `0'. Thus, repeated INCs will propagate past cannot affect WUPD bit. certain situations (such fault recovery interrupts) toggling sufficient must known value without depending current state. 53A27E 43A201 AUXR1,#7EH AUXR1,#1 DPS=0 DPS=1
Each these instructions requires bytes clocks.
1996
Application note
Dual data pointers family
AN458
INTERRUPTS Another exploit additional data pointer dedicate more interrupt handlers. Traditionally (i.e., single data pointer), handler must save current value DPTR entry (typically registers stack), load DPTR with handlers value then reverse process exit. Now, typical foreground/background interrupt scheme, each handler given exclusive data pointer. Switching between data pointers using speeds interrupt response, cuts interrupt overhead reduces code size eliminating instructions needed share single data pointer. More general cases include those which there more than interrupt handlers and/or desired both data pointers more than handler. these cases, data pointers shared using traditional single data-pointer approach saving restoring DPTR. Note that this typically accomplished physical access instruction that supports `direct' addressing mode (such PUSH MOV) used. some cases necessary save state well. This occurs anytime routing that corrupt nested within (i.e., either interrupt subroutine call) routine that uses DPTR. Should necessary, AUXR1 (containing DPS) saved restored using instruction that supports `direct' addressing mode (such PUSH MOV). Applying these techniques block move example, contents both data pointers saved restored. Since this version clock move routine happens exit with equal value entry, state (i.e., contents AUXR1) need explicitly saved. Block move using dual data pointers This version saves restores data pointer state Destroys only 00A2 AUXR1 0A2H 0000 C083 PUSH save first 0002 C082 PUSH data pointer 0004 909000 DPTR,#SOURCE SOURCE address 0007 05A2 AUXR1 switch data pointers 0009 C083 PUSH save second 000B C082 PUSH data pointer 000D 90A000 DPTR,#DEST DEST address 0010 LOOP: 0010 05A2 AUXR1 switch data pointers 0012 MOVX A,@DPTR byte from SOURCE 0013 DPTR increment SOURCE address 0014 05A2 AUXR1 switch data pointers 0016 MOVX @DPTR,A write byte DEST 0017 DPTR increment DEST address 0018 70F6 LOOP check terminator 001A D082 restore second 001C D083 data pointer 001E 05A2 INCV AUXR1 switch data pointers 0020 D082 restore first 0022 D083 data pointer
1996
Application note
Dual data pointers family
AN458
COMPILER operation existing compilers affected additional data pointer. Assuming changed following RESET, existing programs will continue single data pointer. many cases, programs consist mixture assembly language. Using previously mentioned techniques, assembly language portion (ex: custom library entry, interrupt handler, etc.) upgraded take advantage second data pointer without affecting compiler's first. Applications written benefit most upgrading compiler that exploits dual data pointers. shown Figure noticeable (15-30%) speed-up obtained simply modifying block oriented (copy move) library routines. Further optimization code generators parameter passing conventions offers potential even greater performance improvement.
Single DPTR Dual SPTR
memcpy
memmov
memcmp
strcpy
strcmp
Dhrystone
SU00818
Figure Dual DPTR Performance Improvement
1996
Application note
Dual data pointers family
AN458
NOTES
1996
Application note
Dual data pointers family
AN458
Philips Semiconductors Philips Electronics North America Corporation reserve right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Applications that described herein these products illustrative purposes only. Philips Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors Philips Electronics North America Corporation Products designed life support appliances, devices, systems where malfunction Philips Semiconductors Philips Electronics North America Corporation Product reasonably expected result personal injury. Philips Semiconductors Philips Electronics North America Corporation customers using selling Philips Semiconductors Philips Electronics North America Corporation Products such applications their risk agree fully indemnify Philips Semiconductors Philips Electronics North America Corporation damages resulting from such improper sale. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors Philips Electronics North America Corporation register eligible circuits under Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 rights reserved. Printed U.S.A.
1996

Author: Peious Yoseph IC20 Data Handbook 1996 Application note

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