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John INTRODUCTION CDB5504 evaluation board requires simple modifi


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CDB5504 CAPTURE INTERFACE
John INTRODUCTION
CDB5504 evaluation board requires simple modification interface with CAPTURE board. CAPTURE board requires SCLK input signal collect data. However, SCLK CS5504 digital input only. CDB5504 interface with CAPTURE board, SCLK signal needs created. possible solution derive SCLK from XOUT signal. frequency XOUT within specifications SCLK signal serial port accept continuous clock. CAPTURE board designed ignore extra clock signals SCLK line when using continuous serial clock. Using XOUT SCLK input signal simple modification evaluation board. easy implement, requiring extra components. following steps describe modifications. source SCLK signal XOUT CS5504. Install jumper CS5504 from U1-6 U1-18. (Make sure that adjustments made CAB5504 adapter board. U1-18 translates U1-21 bottom evaluation board.) resistor needs removed reduce load upon XOUT. Next 74HC125 buffer needs modified. U3-3 isolated from circuit, there aren't devices driving SCLK node. Finally U3-8 isolated, allowing active able drive SCLK output signal CAPTURE board. Figure schematic modified evaluation board. following check list summarizes modifications.
REMOVE JUMPER U1-6 U1-18 ISOLATE U3-3 ISOLATE U3-8
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved)
AN45REV1
6.8V 6.8V External VREF AIN2R28 100k AIN2+ 100k AIN1R30 100k AIN1+ 100k
MODIFICATIONS CDB5504 INTERFACING CDBCAPTURE
AGND DGND 10nF 10nF TP10 VREF+ VREFCONV TP11 TP12 100k 100k SDATA SCLKO 100k 100k CONV DRDY SCLK 0.01 100k SDATA
LT1019 -2.5
CS5504
DRDY AIN2+ AIN1+ AIN1AIN2SDATA
DRDY
TP13
0.01
0.01
TP15
0.01 0.01
100k 100k TP14 100k BP/UP SCLK XOUT DGND 32.768
SCLKI
BP/UP 74HC4050 74HC125 CONV BP/UP
CLKIN
Note:
Remove Isolate U3-3 Isolate U3-8 Jumper U1-6 U1-18
AN45REV1
Figure Schematic CDB5504 Modified CAPTURE Interface
Notes

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