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Comparison of MM74HC to 74LS, 74S and 74ALS Logic

Fairchild Semiconductor Application Note 319 June 1983

Comparison of MM74HC to 74LS, 74S and 74ALS Logic
Fairchild Semiconductor Application Note 319 June 1983
AC PERFORMANCE As mentioned previously, the MM54HC / MM74HC logic family has been designed to have speeds equivalent to LS-TTL, and to be 8-10 times faster than CD4000B and MM54C / MM74C logic. Table 1 compares high speed CMOS to the bipolar logic families. HC-CMOS gate delays are typically the same as LS-TTL, and ALS-TTL is two to three times faster. S-TTL is also about twice as fast as HC-CMOS. Flip-flop and counter speeds also follow the same pattern.
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FIGURE 1. HC, LS, ALS, S Comparison of Propagation Delay vs Load for a NAND Gate
TABLE 1. Comparison of Typical AC Performance of LS-TTL, S-TTL, ALS-TTL and HC-CMOS Gates 74XX00 74XX04 74XX139 Propagation Delay Propagation Delay Propagation Delay Select Enable 74XX151 Propagation Delay Address Strobe 74XX240 Clocked MSI 74XX174 74XX374 Propagation Delay Operating Frequency Propagation Delay Enable / Disable Time Operating Frequency 20 40 19 21 50 7 50 7 9 50 18 50 16 17 50 13 100 11 11 100 ns MHz ns ns MHz Propagation Delay Enable / Disable Time 27 26 12 20 8 7 3 7 26 17 10 17 12 12 5 10 ns ns ns ns 25 21 8 8 25 20 8 7 ns ns LS-TTL 8 8 ALS-TTL 5 4 HC-CMOS 8 8 S-TTL 4 3 Units ns ns
Combinational MSI
slopes of these lines indicate the amount of variation in speed with loading, and are dependent on the output impedance of the particular logic gate. The delay variation of LS-TTL and HC-CMOS is similar whereas ALS-TTL and S-TTL have slightly less variation.
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POWER DISSIPATION CD4000B and MM54C / MM74C CMOS devices are well known for extremely low quiescent power dissipation, and high speed CMOS retains this feature. Table 2 compares typical HC static power consumption with LS, ALS and S-TTL. Even CMOS MSI dissipation is well below 1 µW while LS-TTL dissipation is many milliwatts. This makes MM54HC / MM74HC ideal for battery operated or ultra-low power systems where the system may be put to "sleep" by shutting off the system clock. TABLE 2. Comparison of Typical Quiescent Supply Current for Various Logic Families HC-CMOS SSI Flip-Flop MSI 0.0025 µW 0.005 µW 0.25 µW LS-TTL 5.0 mW 20.0 mW 90 mW ALS-TTL 2.0 mW 10 mW 40 mW S-TTL 75 mW 150 mW 470 mW
CMOS dissipation increases proportionately with operating frequency. Doubling the operating frequency doubles the current consumption. This is due to currents generated by charging internal and load capacitances. Figure 3 shows power dissipation versus frequency for a completely unloaded NAND gate, flip-flop and counter implemented in all 4 technologies. The LS, S and ALS curves are essentially flat because the quiescent currents mask out capacitive effects, except at very high frequencies. Capacitive effects are slightly lower for the TTL families, so that, at high frequencies, CMOS dissipation may actually be more than ALS and LS. However, the power crossover frequency is usually well above the maximum operating frequency of MM54HC / MM74HC. The previously mentioned curves plot unloaded circuits. When considering typical system power consumption, capacitive loading should also be considered. Table 3 lists components to implement all the support logic for a small mi-
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FIGURE 2. Power Consumption for Hypothetical Microprocessor System Support Logic
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FIGURE 3. Supply Current Consumption Comparison for (a) 74XX00 (b) 74XX714 (c) 74XX161 Circuits Since, in a typical system, some sections will operate at a high frequency and other parts at lower frequencies, the average system clock frequency is a simplification. For example, a 10 MHz microprocessor will have a bus cycle frequency of 2 to 5 MHz. Most system and memory components will be accessed a small amount of the time, resulting in effective clock frequencies on the order of 100 kHz for these sections. Thus, the average system clock frequency would be around 1 to 2 MHz, and an 8 to 1 power savings would be realized by using CMOS. Another simplification was made to calculate system power. CMOS circuits will dissipate much less power when 3-STATE, which would save much power since, in a given
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bus cycle, only a few buffers will be enabled. LS, ALS and S, however, actually dissipate more power when their outputs are disabled. Several interesting conclusions can be drawn from Figure 2. First, notice that, at higher frequencies, the bipolar logic families start to dissipate more power. This is a result of current consumption due to switching the load. As the operating frequency approaches infinity, this will be the dominant effect. So, for extremely fast low power systems, minimizing load capacitance and overall operating frequency becomes more important. As lower power TTL logic is introduced, system power will be increasingly dependent on capacitive load effects similar to CMOS. Second, TTL logic has a slightly smaller logic voltage swing than CMOS. Thus, for a given load, TTL will actually have a lower average load current. So, similar to the unloaded example, at very high frequencies, CMOS could consume more power than TTL. As Figure 5 indicates, these frequencies are usually far above the 30 MHz limit of HC-CMOS or LS-TTL.
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FIGURE 4. Worst-Case Input and Output Voltages Over Operating Supply Range for HC and LS Logic
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(b) FIGURE 5. Input-Output Transfer Characteristics for 74XX00 NAND Gate Implemented in (a) HC-CMOS (b) LS-TTL (c) ALS-TTL
Another indication of DC noise immunity is the typical transfer characteristics for the logic families. Figure 5 shows the transfer function of the 74XX00 NAND gate for HC-CMOS, LS-TTL and ALS-TTL. High speed CMOS has a very sharp transition typically at 2.25V, and this transition point is very stable over temperature. The bipolar logic transfer functions are not as sharp and vary several hundred millivolts over temperature. This sharp transition is due to the large circuit gains provided by triple buffering the HC-CMOS gate com3
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patible would compromise noise immunity, die size, and significant speed. The designer may improve compatibility by adding a pull-up resistor to the TTL output. He may also utilize a series of TTL-to-CMOS level converters which are being provided to ease design of mixed HC / LS / ALS / S systems. These buffers have 0.8V and 2.0V TTL input voltage specifications, and provide CMOS compatible outputs. When mixing logic, the noise immunity at the TTL to CMOS interface is no better than LS-TTL, but a substantial savings in power will occur when using MM54HC / MM74HC logic. INPUT CURRENT The HC family maintains the ultra-low input currents typical of CMOS circuits. This current is less than 1 µA and is caused by input protection diode leakages. This compares to
the much larger LS-TTL input currents of 0.4 mA for a low input and 40 µA for a high input. ALS-TTL input currents are 0.2 mA and 20 µA and S-TTL input currents are 3.2 mA and 100 µA. Figure 7 tabulates these values. The near zero input current of CMOS eases designing, since a typical input can be viewed as an open circuit. This eliminates the need for fanout restrictions which are necessary in TTL logic designs.
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FIGURE 6. Input-Output Transfer Characteristics for 74XX08 AND Gate Implemented in (a) HC-CMOS (b) ALS-TTL
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FIGURE 7. Comparison of Input Current Specifications for Various Logic Families POWER SUPPLY RANGE Figure 4 also compares the supply range of MM54HC / MM74HC logic and LS-TTL. The high speed CMOS family is specified to operate at voltages from 2V to 6V. 54LS, 54S and 54ALS logic is specified to operate from 4.5V to 5.5V, and 74LS and 74S will operate from 4.75V to 5.25V. 74ALS is specified over a 4.5V to 5.5V supply range. This wider operating range for the HC family eases power supply design by eliminating costly regulators and enhances battery operation capabilities.
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OUTPUT DRIVE Since there was no speed, noise immunity, or power trade-off, standard HC-CMOS was designed to have similar high current output drive that is characteristic of LS-TTL and ALS-TTL. Schottky TTL has about 5 times the output drive of MM54HC / MM74HC. Thus HC-CMOS has an output low current specification of 4 mA at an output voltage of 0.4V. In keeping with CD4000B series and 54C / 74C series logic, the source and sink currents are symmetrical. Thus HC logic can source 4 mA as well. This large increase in output current for high speed CMOS over CD4000B also has the added advantage of reducing signal line crosstalk which can be of greater concern in high speed systems. Figure 8 compares HC, LS, and ALS specified output currents. Since TTL logic families do have significant input currents they have a limited fanout capability. Table 4 illustrates the limitations of these families, based on their input and output currents. High speed CMOS is also included. MM54HC / MM74HC has the same CMOS-to-CMOS fanout characteristics as CD4000B, virtually infinite.
TABLE 4. Fanout of HC-CMOS, LS-TTL, ALS-TTL, S-TTL From, To 74HC 74LS 74ALS 74S 74HC 4000
74LS 10 20 20 50
74ALS 20 40 40 100
As another indication of the similarity of HC-CMOS to LS-TTL, Figure 9 plots typical output currents versus output voltage for LS and HC. The output sink current curves are very similar, but LS source current is somewhat different, due to its emitter-follower output circuitry. MM54HC / MM74HC bus driving circuits, namely the 3-STATE buffers and latches, have half again as much output current drive as standard outputs. These components have a 6 mA output drive. The 6 mA was chosen based on a trade-off of die size and speed-load variations. This current is less than the 12 mA or more specified for LS and ALS bus driver circuits, because the bus fanout limitations of these families do not apply in CMOS systems. S-TTL bus output sink current is 48 mA.
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FIGURE 8. Output Current Specifications for ALS-TTL, S-TTL and HC-CMOS
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FIGURE 9. Comparison of Standard LS-TTL and HC-CMOS Output (a) Source (b) Sink Currents
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FIGURE 10. Propagation Delay Variation Across Temperature for (a) 74LS00 (b) 74ALS00 and (c) 74HC00
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Comparison of MM74HC to 74LS, 74S and 74ALS Logic
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.