Characteristics MM74HC High-Speed CMOS When deciding what circuit

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Characteristics MM74HC High-Speed CMOS When deciding what circuit

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Characteristics MM74HC High-Speed CMOS
Characteristics MM74HC High-Speed CMOS
When deciding what circuits design, speed most often very important criteria. MM74HC intended offer same basic speed performance power Schottky while giving designer power high noise immunity characteristics CMOS. other words, HC-CMOS about times faster than CD4000 MM54C/MM74C metal-gate CMOS logic. Even though HC-CMOS logic does have speeds similar LSTTL, there some differences this family's speeds specified, various parameters affect circuit performance. give designer idea expected performance, this discussion will include characteristics high-speed CMOS specified. This logic family been specified that majority applications, specifications directly applied design. Since impossible specify device under possible situations, performance variations with power supply, loading temperature discussed, several easy methods determining propagation delays nearly situation also described. Finally, useful compare performance HC-CMOS 74LS CD4000. Data Sheet Specifications Even though speeds achieved this high-speed CMOS family similar LSTTL, input, output power supply characteristics very similar metal-gate CMOS. Because this, actual measurements various timing parameters done same TTL. MM74HCT input compatible circuits exception. Standard HC-CMOS specifications measured 2.0V, 4.5V, 6.0V room, military commercial temperature ranges. Also specified with equivalent supply (5.0V) load conditions enable proper comparison power Schottkey TTL. Input signal levels ground with rise fall times (10% 90%). Since standard CMOS logic logic trip point about mid-supply, outputs will transition from ground VCC, timing measurements made from points input output waveforms. This shown Figure Using mid-supply point gives more accurate representation high-speed CMOS will perform CMOS system. This different from 1.3V measurement point ground input waveforms that used measure timing. This output loading used data sheet specifications fall into categories, depending output drive capability specific device. output drive categories standard outputs (IOL driver outputs (IOL mA). Timing measurements standard outputs made using load. driver circuits measured using both load. tests, test load capacitance includes stray test capacitances. 3-STATE measurements where outputs from active output level high impedance state, made using same input waveforms described above, timing measured points output wave-
Fairchild Semiconductor Application Note April 1989
forms. test circuit load composed capacitor resistor. test tPHZ, resistor swiched ground, tPLZ switched VCC. 3-STATE test circuit typical timing waveforms shown Figure Measurements, where output goes from high impedance state active output, same except that measurements made points driver devices both capacitors used.
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1998 Fairchild Semiconductor Corporation
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FIGURE Typical 3-STATE Timing Waveforms Test Circuit 74HC Devices
Note: Some early data sheets used different test circuit. This been changed will changed.
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FIGURE Typical Timing Waveform Propagation Delays, Clocked Delays. Also Test Circuit These Waveforms
/MM74HCT input compatible devices intended operate with devices, makes sense specify them same TTL. Thus, shown Figure typical timing input waveforms 0-3V levels timing measurements made from 1.3V levels these signals. test circuits used same standard input circuits. This shown Figure These measurements compatible with type specified devices. Specifying standard MM74HC speeds using 2.5V input measurement levels does represent specification incompatibility between most RAM/ROM microprocessor speed specifications. should not, however, present
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sign problem. timing difference that results from using different measurement points time takes output make extra excursion from 1.3V 2.5V. Thus, standard high-speed CMOS output, extra transition time should result, worst case, less than increase circuit delay measurement load. Thus speed critical designs adding safely enables proper design into level systems. Power Supply Affect Performance overall power supply range MM74HC logic wide CD4000 series CMOS performance optimization operation; however, this family operate over 2-6V range which does enable some versatility, especially when battery operated. Like metal-gate CMOS, lowering power supply voltage will result increased circuit delays. Some typical delays shown Figure supply voltage decreased from propagation delays increase about three times, when voltage increased delays decrease 10-15%.
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FIGURE Typical Timing Waveforms 74HCT Devices ns)Propagation Delays, Clocked Delays 74HCT
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Speed Variation with Capacitive Loading When high-speed CMOS designed into CMOS system, load given output essentially capacitive, individual input capacitances, 3-STATE output capacitances, parasitic wiring capacitances. load increased, propagation delay increases. rate increase delay particular device increased charge/discharge time output load. rate which delay changes dependent output impedance MM74HC circuit. mentioned, high-speed CMOS, there output structures: driver standard.
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FIGURE Typical Propagation Delay Variations 74HC00, 74HC139, 74HC174 with Power Supply some designs important calculate expected propagation delays specific situation covered data sheet. This easily accomplished using normalized curve Figure which plots propagation delay variation constant, t(V), versus power supply voltage normalized 4.5V operation. This constant, when used with following equation data sheet 5.0V specifications, yields required delay power supply. tPD(V) [t(V)] [tPD(5V)] Where tPD(5V) data sheet delay tPD(V) resultant delay desired supply voltage. This curve also used 4.5V specifications. example, calculate typical delay 74HC00 data sheet typical load) used. From Figure t(V) 0.9, delay would
Figure plots some typical propagation delay variations against load capacitance. calculate under particular load condition what propagation delay circuit need only know what rate change propagation delay with load capacitance this number extrapolate delay from data sheet vaue desired value. Figure plots this constant, t(C), against power supply voltage variation. Thus, expanding equation 1.0, propagation delay load power supply calculated using: tPD(C,V) [t(C) pF)] [tPD(5V) t(V)]
Where t(V) propagation delay variation with power supply constant, tPD(5V) data sheet 4.5V (use (CL- equation) delay, load capacitance tPD(C,V) resultant propagation delay desired load supply. This equation's first term difference propagation delay from desired load data sheet specification load. second term essentially equation 1.0. delay calculated then t(V) t(C) 0.042 ns/pF (standard output), 0.028 ns/pF (bus output). Using previous 74HC00 example, delay load tPD(100 pF,6V) (0.042)(100 15)+(0.9
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FIGURE MM74HC Propagation Delay Variation Power Supply Normalized 4.5V, 5.0V
FIGURE Typical Propagation Delay Variation With Load Capacitance 74HC04, 74HC164, 74HC240, 74HC374
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example from previous section, expected increase propagation delay when operated 85°C [1+(85-25)(0.003)](10 ns)] expected delay some other supply also calculated calculating room temperature delay then calculating delay desired temperature.
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FIGURE Propagation Delay Capacitance Variation Constant Power Supply Speed Variations with Change Temperature Changes temperature will cause some change speed. with CD4000 other metal-gate CMOS logic parts, MM74HC operates slightly slower elevated temperatures, somewhat faster lower temperatures. mechanism which causes this variation same that which causes variations metal-gate CMOS. This factor carrier mobility, which decreases with increase temperature, this causes decrease overall transistor gain which corresponding affect speed.
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FIGURE Typical Propagation Delay Variation With Temperature 54HC02, 54HC390, 54HC139, 54HC151 Output Rise Fall, Setup Hold Times Pulse Width Performance Variations far, previous discussion been restricted propagation delay variations, most instances, this most important parameter know. Output rise fall times also important. Unlike type logic families specifies these data sheet. High-speed CMOS outputs were designed have typically symmetrical rise fall times. Output rise fall time variations track very closely propagation delay variations over temperature supply. Figure plots rise fall time against output load room temperature. Load variation transition time twice delay variation because delays measured halfway points waveform transition. Setup times pulse width performance under different conditions necessary when using clocked logic circuits. These parameters indirect measurements internal propagation delays. Thus they exhibit similar temperature supply dependence propagation delays. They are, however, independent output load conditions.
Figure shows some typical temperature-delay variations some high-speed CMOS circuits. seen, speeds derate fairly linearly from 25°C about -0.3%/C. Thus, 125°C propagation delays will increased about from 25°C.74HC speeds specified room temperature, 85°C (commercial temperature range), 125°C (military range). virtually cases numbers given highest temperature. calculate expected device speeds temperature, specified device data sheet, following equation used: tPD(T) ((T-25)(0.003))][tPD(25)]
Where tPD(T) delay desired temperature, tPD(25) room temperature delay. Using 74HC00
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When comparing CD4000 operating HC-CMOS typically times faster, about three times faster than CD4000 logic operating 15V. This shown Figure
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FIGURE Typical Output Rise Fall Time Load Standard Driver Outputs
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Input Rise Fall Times Another speed consideration, though directly related propagation delays, input rise fall time. with other high-speed logic families also CD4000B CMOS, slow input rise fall times input signals cause logic problems. Typically, small signal gains MM74HC gate greater than 1000 and, input signals spend appreciable time between logic states, noise input power supply will cause output oscillate during this transition. This oscillation could cause logic errors user's circuit well dissipate extra power unnecessarily. this reason MM74HC data sheets recommend that input rise fall times shorter than 4.5V. Flip-flops other clocked circuits also should have their input rise fall times faster than 4.5V. clock input rise fall times become long, system noise generate internal oscillations, causing internal flip-flops toggle wrong external clock edge. Even noise were present, internal clock skew caused slow rise times could cause logic malfunction. long rise fall times unavoidable, Schmitt triggers ('HC14/'HC132) other special devices that employ Schmitt trigger circuits should used speed these input signals. Logic Family Performance Comparison obtain better feeling high-speed CMOS compares bipolar other CMOS logic families, Figure plots MM74HC, 74LS CD4000B logic device speeds versus output loading. HC-CMOS propagation delay delay variation with load nearly same LSTTL about times faster than metal-gate CMOS. Utilizing silicon-gate process enables achievement LSTTL speeds, large output drive this family enables variation with loading nearly same LSTTL well.
FIGURE Comparison LSTTL High-Speed CMOS Delays CD4000 about tenth output drive MM74HC seen Figure capacitive delay variation much larger. shown Figure temperature variation HC-CMOS similar CD4000. This same physical phenomenon both families. 74LS logic family very different temperature variation, which different circuit parameter variations. advantage CMOS that temperature variation predictable, with LSTTL, sometimes speed increases other times speed decreases with temperature. inherent symmetry MM74HC's logic levels rise fall times tends make high high propagation delay very similar, thus making these parts easy use.
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FIGURE Comparison Metal-Gate CMOS High-Speed CMOS Delays
FIGURE Comparison HC-CMOS, Metal-Gate CMOS, LSTTL Propagation Delay Temperature Conclusion High-speed CMOS circuits speed compatible with 74LS circuits, only data sheets, even driving different loads. general, HC-CMOS provides large improvement performance over older metal-gate CMOS. using some equations curves detailed here, along with data sheet specifications, designer very closely estimate performance MM74HC device. Even though above examples illustrate typical performance calculations, more conservative design implemented more conservatively estimating various constants using worst case data sheet limits. also possible estimate fastest propagation delays using speeds about 0.4-0.7 times data sheet typicals aggressively estimating various constants.
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Characteristics MM74HC High-Speed CMOS
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