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ADC INPUT BUFFER AND PROTECTION TECHNIQUES

By Steven Green

Application Note
ADC INPUT BUFFER AND PROTECTION TECHNIQUES
By Steven Green
+15V 78L05 CR5 5.6V 2k Left Analog Input 2k CR1 51 R1 2k Right Analog Input 2k 51 R2 10 nF VA+ 0.1 uF + 1 uF VA5 27 1 CR4 10 nF CR2 51 + 1 uF 0.1 uF 4 VA+ 25 VL+ 0.1 uF
BAT-85 HP5082-2810 2 AINL CS5336 CS5338 CS5339 AINR AGND
CR3 -15V 79L05 CR6 5.6V
INTRODUCTION
The design of input buffer and protection circuits for analog-to-digital-converters (ADC) is critical to an optimized and reliable data acquisition system. The Crystal Semiconductor application note "ADC Input Buffers" covered this area well and the system designer should review this information. Since the publication of "ADC Input Buffers" there have been many requests for additional information and circuits relating to ADC input protection. This application note describes suitable buffer / protection circuits for the CS5336 family of converters. The techniques described are equally applicable to the other families of Crystal analogto-digital converters.
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
SCR LATCH-UP
of the amount of current required to initiate a latch. Problems can arise when input voltages greater than the instantaneous power supply voltages are applied during power-up. A less common but equally damaging SCR condition can occur when power-supply voltages exceed the absolute maximum specified value. There are several protection techniques available to the designer each with their own advantages and disadvantages.
PROTECTION TECHNIQUES
The goal of input protection is to guarantee that the ADC input voltage never exceeds the supply voltages of the converter. This is accomplished with an op-amp buffer between the "outside" world and the ADC input, then limiting the ADC input voltage excursions to the range bounded by the converter power supply voltages.
Method I
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Notes for Method 1
The values of R1 and R2 were selected to optimize the source impedance for the CS5336 and utilize the current limiting characteristics of the op-amp. Clamping circuits with diodes in the feedback loop of the op-amp work well for signal clamping but are not effective for power-on transient or op-amp failure conditions. These circuits are not recommended for protection.
Method II
ADC Power Supply Overvoltage
Standard 3-terminal regulators are designed to either source (78L05) or sink (79L05) current but not both. It is possible to raise the ADC supply voltage above the regulation voltage through the Schottky diodes during error conditions. The 5.6 V zener diodes CR5 and CR6 are included to prevent the supply voltages from exceeding the maximum specified value and damaging the converter.
51 +15V 78L05 + 1 uF 0.1 uF 4 VA+ 25 VL+ 0.1 uF
79L05
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REFERENCES
1) Johnston, Jerome: ADC Input Buffers, Crystal Semiconductor Corp. 2) Fredriksen, Thomas M.: Intuitive IC Op Amps, National Semiconductor Technology Series 1984 3) Pease, Robert: Bounding, clamping techniques improve circuit performance, EDN Nov. 10, 1983 4) Pease, Robert: Active-component problems yield painstaking probing, EDN Aug. 3, 1989 5) Hewlett / Packard Components: Application Bulletin 14, Waveform Clipping With Schottky Diodes. 6) Hewlett / Packard Components: Application Bulletin 15, Waveform Clipping With Schottky Diodes. 7) Hewlett / Packard Components: Application Note 942, Schottky Diodes for High Volume, Low Cost Applications 8) Application Note MSAN-107: Understanding and Eliminating Latch-up in CMOS Applications, MITEL August 1982
CONCLUSION
Two circuits have been described which utilize effective protection techniques. Use of either of these circuits or the techniques described will insure that the performance and reliability of a data acquisition system will not be limited by the input buffer and protection circuits.
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