June 2001, ver. Introduction system speeds have increased, s

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June 2001, ver. Introduction system speeds have increased, s

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Increasing System Bandwidth with
June 2001, ver.
Introduction
system speeds have increased, semiconductor board designers have turned source-synchronous clocking differential signaling improve chip-to-chip data transfer rates. While source-synchronous clocking does meet this need, very flexible. Designers must closely match clock data line lengths, complicating board design. Every chip-to-chip data transfer must have clock well data lines, every connection introduces clock domain. device that receives data from several devices must have dedicated circuitry each connection manage data flow among several clock domains. clocking technique called clock-data synchronization (CDS) combines advantages traditional synchronous clocking sourcesynchronous clocking providing high-speed data transfer without need closely match clock data lines. Unlike clock-data recovery (CDR), there need encode scramble data meet kind run-length requirement. This application note discusses works used variety systems. look-up table (LUT)-based APEXII device family incorporates circuitry differential circuitry. These devices offer four banks high-speed differential pins: output banks input banks. Each bank contains channels clock supports LVDS, LVPECL, PCML, HyperTransport standards gigabit second (Gbps). input banks incorporate CDS, providing advantages described below.
SourceSynchronous Clocking
Source-synchronous clocking become popular technique highspeed designs. With this technique, transmitting device sends clock along with data. advantage this approach that maximum performance longer computed from clock-to-out delay, propagation delay, setup times devices board. Instead, maximum performance related maximum edge rate driver skew between data signals clock signals. Using this technique, data transferred 1-Gbps rate (1-ns period) even though propagation delay from transmitter receiver exceed Figure shows example source-synchronous transfer.
Altera Corporation
A-AN-162-01
162: Increasing System Bandwidth with
Figure Source-Synchronous Transfer
source-synchronous system, trace lengths must matched minimize skew between data traces clock trace.
Transmitter
Receiver
Data1 Data2
Clock
Clock
However, there some drawbacks source-synchronous clocking technique. board design must tightly controlled that there minimal skew between data clock paths. Additionally, each data driven from device must sent with clock signal. Therefore, device receives data from four other devices, that device must also receive four clocks. These clocks complicate design receiver, design manage four clock domains using first-in first-out (FIFO) buffers.
Clock-Data Synchronization
solution this design challenge. With CDS, receiving device synchronize multiple incoming streams data system clock. This technique simplifies board design because skew between data channels clock longer issue. receiver correct amount clock-to-channel channel-to-channel skew. allows designers easily implement various system topologies. Multiple devices feed into receiving device, which processes incoming data clock domain. Figure shows example system using CDS.
Altera Corporation
162: Increasing System Bandwidth with
Figure System Using
APEX Device
APEX Device
APEX Device
APEX Device
Clock Signal
been used address similar skew topology requirements. advantage over because data transmitters operate multiple crystals receiver recovers individual clocks from each incoming data channel. Every channel have phase variation well frequency variation within specified limit. Although provides flexibility, receiver design more complicated because every data channel clock domain. With CDS, data channels vary phase, must precisely same frequency. ensure that channels same frequency, transmitters must clocked from same system clock.
Altera Corporation
162: Increasing System Bandwidth with
Compared CDR, advantage data transmission efficiency. receiver recover clock data, data channel must periodically toggle. This requirement known maximum length. example, common technique 8B/10B encoding, which ensures that more than five ones five zeros never transmitted consecutively. However, this encoding scheme creates inefficiency data channel. 1.25-gigabit data channel only transmit 1-gigabit 8B/10B-encoded data stream. does have length requirement, there need encode data stream. Therefore, entire bandwidth transmission channel used system data; 1.25-gigabit data channel transmit 1.25-gigabits data.
Implementation
APEX receiver works aligning itself known training pattern transmitter sends over data channels. When sending training pattern, transmitter also enables receiving device synchronize data system clock. receiver's circuit captures pattern with multiple phases system clock then selects whichever clock phase correctly captured pattern. After training pattern sent, receiver uses selected clock phase capture actual data. Figure shows circuitry that selects which phase clock captures data.
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162: Increasing System Bandwidth with
Figure Implementation
Input Data
Synchronized Data
Control Logic Selects Register
Output System Clock Output
Note Figure
PLL: phase-locked loop.
When using source-synchronous clocking, data stream automatically byte-aligned. example, data stream eight times fast clock, most significant (MSB) each byte data transmitted during third period after clock. This relationship holds because skew between clock data limited. There limit skew between clock data system. Therefore, designer cannot relationship between clock data byte-align signals. However, system, byte alignment pattern sent receiver after training pattern. receiving device uses this pattern byte-align data.
Altera Corporation
162: Increasing System Bandwidth with
only takes clock cycles transmit process this training byte-alignment sequence, this performed once upon system powerup. multiple transmitting devices same board, they subject same voltage temperature variation, skews between them will vary retraining necessary. transmitting devices send training pattern simultaneously that receiver self-adjust skews simultaneously. However, transmitting devices different boards subsystems, they experience different voltage temperature variation, design need periodically resend training pattern depending variation that system sees. Although additional clock cycles necessary resend training pattern, system still more efficient than systemencoding schemes.
System Applications
improves system efficiency many ways. correct skew that cables connectors introduce data channels. also adds flexibility overall system designs. examples implementing switched backplane breaking large designs into multiple devices. Many systems, including communications storage systems, incorporate backplane transmit data from subsystem another. Historically, these designs have used shared backplane (such PCI). However, need faster data transfer revealed limitations this approach. shared backplane only support transaction time, speed cannot increase fast enough support data requirements. switched backplane approach solution higher data transfer requirements. Rather than sharing common bus, each card communicates point-to-point link master switch. switch transfers data destination point. Differential standards well-suited this architecture, each point-to-point link very high speeds. Furthermore, since shared, multiple transactions executed simultaneously, shown Figure
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162: Increasing System Bandwidth with
Figure Switched Backplane Application
APEX Device
APEX Device
APEX Device
APEX Device
Clock Signal
With source-synchronous clocking, every point-to-point link must have clock. master switch must implement multiple clock domains manage data clock skew across backplane. good solution these concerns because cards system clock. master switch correct skews caused system clock skew, device-to-device variation, data skew. Using this architecture simplifies overall system design keeping entire system synchronized clock. circuitry APEX device family provides flexibility necessary easily implement switched backplane system.
Altera Corporation
162: Increasing System Bandwidth with
Another example application design partitioning. Many complex designs, such packet processing, cannot easily into device partitioned other reasons. example, while software running network processors useful general packet processing, ASICs programmable logic devices (PLDs) often used accelerating specific functions. Network processors PLDs implement different functions within system. example, classification queuing control important assure quality service, encryption important security. These functions implemented higher speed than network processor. size these functions prevent them from being incorporated into PLD. Historically, partitioning these functions into multiple devices resulted very inefficient devices. Each individual device would usually pins before using logic. High-speed differential interconnects conjunction with enable very high bandwidth data transfer from device device required data transfer from chip chip implemented using only pins. Figure shows block diagram OC-192 data path. this design, packet processing divided between network processor multiple PLDs. used implement high-speed data transfer among multiple devices that make packet-processing function.
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162: Increasing System Bandwidth with
Figure OC-192 Design Partitioning
SRAM SDRAM Blocks
Circuitry Device Transceiver Framer Packet Processing Switch Fabric
Packet Processing System
Host Processor
APEX Device
APEX Device
APEX Device
APEX Device
Note Figure
PMD: physical medium dependent.
Because enables easier design partitioning, also useful ASIC prototyping. many cases, designer takes advantage flexibility easy reconfiguration programmable logic prototype design, then moves very large extremely high-volume design ASIC. Since ultimate capacity standard-cell device larger than that programmable logic device, designer will partition this design into multiple PLDs. discussed earlier, this lead inefficient logic within these devices. using CDS, designer implement required data transfer between devices full logic capacity PLDs.
Altera Corporation
162: Increasing System Bandwidth with
Summary
Increasing demand data services driven higher bandwidth requirements system designers. Differential signaling been successfully used address this need. builds success differential signaling, giving designers more flexibility design their boards their overall systems. using APEX devices, designers enhance their systems provide flexibility performance.
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Altera, APEX, APEX specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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June 2001, ver. Introduction system speeds have increased, s

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