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Prepared Senad Lomigora, Paul Shockman Semiconductor Logic Application


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AN1503/D ECLinPS ECLinPS Lite SPICE Modeling
Prepared Senad Lomigora, Paul Shockman Semiconductor Logic Applications Engineering
Objective objective this provide customers with enough circuit schematic SPICE parameter information allow them perform system level interconnect modeling current devices standard ECLinPS ECLinPS Lite logic line, Semiconductor's high performance family. intended provide information necessary perform circuit level modeling ECLinPS devices. With packaged gate delays output edge rates this family defines state-of-the-art logic. ECLinPS line Semiconductor's high performance ECL/PECL family products. Device Input Output Buffers Schematic Information contains representative input output schematics, netlists, waveform used standard ECLinPS ECLinPS Lite devices. This application note will modified devices added. There four terminals transistor models: Emitter, Base, Collector, Substrate (biased VEE). should noted that circuits used single ended replacing with VBB. Table describes nomenclature used schematics netlists.
Table Schematics Netlist Nomenclature
VTT* PECL PECL TERMINATION PLANE* TRUE INPUT INVERTED INPUT TRUE OUTPUT INVERTED OUTPUT
measured pin. package model should placed each device input connecting input model, device output pins connecting output model, VCC, VEE. model used pin: necessary since current constant. Appendix includes explanation package models nodes. package model CDIP-16 only center values provided. Remaining pins ratio values between those given pins.
Table Available Packages
Package Model SO-8 TSSOP-8 SO-20 PLCC-28 PLCC-20 CDIP-16 Page Number
Input Buffer typical input buffer schematic (see Table netlist representing structure currently existing devices this family. schematics require addition models (Figure package models (see Table more accurately model behavior certain device. internal input pulldown resistor, RPD, shown Figure unnecessary include Package model pins models because intended internal node most applications. modeled external node usually bypassed because constant voltage, adding Package parameters provide additional benefit. Output Buffer output buffer schematics (see Table netlists contain temperature compensation structure, only package models need added. input output that driving being driven chip signal should include package models. output buffers show differential inputs outputs. When simulating single ended output, termination load resistor, package model, structure output emitter
Except EL89,
Package case model various package types included improve accuracy system model (see Table package model represents parasitics they
Semiconductor Components Industries, LLC, 2001
September, 2001 Rev.
Publication Order Number: AN1503/D
AN1503/D
follower, unused output, should eliminated simplify system model. SPICE Netlists netlists organized group subcircuits. each subcircuit model netlist, model name followed list node interconnects. Temperature Compensation Network Series output netlists include temperature compensation network circuitry style output buffers. temperature compensation circuitry should placed pictured output buffer schematics with representing left right schematic. circuit components temperature compensation networks shown Figure simulating style outputs these components should either deleted commented subcircuit netlists. SPICE Parameter Information addition schematics netlists listing SPICE parameters transistors referenced schematics netlists. These parameters represent typical device given transistor. Varying typical parameters will affect performance structures; type modeling intended this note, actual delay times necessary modeled, result variation device parameters meaningless. performance levels more easily varied other methods will discussed next section. resistors referenced schematics polysilicon have little parasitic capacitance real circuit none required model. schematics display only devices needed SPICE netlists. Modeling Information bias drivers devices detailed since their circuitry would result substantial increase model complexity simulation time. Instead, these internal reference voltages (VBB, LVCS, Etc.) should driven with ideal constant voltage sources. typical interconnect schematic been modeled provide output waveform ECLinPS Line. typical input buffer driven with output buffer shown Figure schematics SPICE parameters
Line Line
will provide typical output waveshape, which seen Figure Simple adjustments made models allowing output characteristics simulate conditions near corners some data book specifications. Consistent cross-point voltages need maintained.
adjust rise fall times:
Produce desired rise fall times output slew rates adjusting collector load resistors change gates tail current. voltage will affect tail current output differential, which will interact with load resistor collector resistor determine output.
adjust VOH:
Adjust level same amount varying VCC. output levels will follow changes ratio.
adjust only:
Adjust level independently level increasing decreasing collector load resistance. Note that level will also change slightly IBASER drop across collector load resistor. changed varying supply, therefore gate current through current source resistor. Summary information included this provides adequate information SPICE level system interconnect simulation. block diagram Figure illustrates typical situation which modeled using information this kit. Device input output models presented Table Table
Table Buffer Model Figures
Buffer Model OBUF_A OBUF_B OBUF_C OBUF_D OBUF_E INBUFTYPICAL Figure Number Page Number
Line
Typical Input
Typical Output
Typical Input
Typical Input
Figure Typical Application SPICE Modeling
AN1503/D
Table Input/Output Selection
Device E016 E101 E104 E107 E111 E112 E116 E122 E131 E136 E137 E141 E142 E143 E150 E151 E154 E155 E156 E157 E158 E160 E163 E164 E166 E167 E171 E175 E193 E195 E196 E197 E210 E211 E212 E241 E256 E310 E336 E337 E404 E411 Sync. Binary Counter Quad input OR/NOR Gate Quint input AND/NAND Gate Quint input XOR/XNOR Gate Diff. Clock Driver Quad Driver Quint Diff. Line Receiver Buffer Flip-Flop Universal Up/Down Counter Ripple Counter Shift Register Shift Register Hold Register Latch Register Mux-Latch Mux-Latch Mux-Latch Quad Multiplexer Multiplexer Parity Generator/Checker Multiplexer 16:1 Multiplexer Magnitude Comparator Mux-Register Multiplexer Latch with Parity Error Detection/Correction Circuit Programmable Delay Chip Programmable Delay Chip Data Separator Dual 1:4, Diff. Fanout Buffer Diff. Clock Distribution Chip Scannable Registered Address Driver Scannable Register Mux-Latch Voltage Diff. Fanout Buffer Registered Transceiver Scannable Registered Transceiver Quad Diff. AND/NAND Diff. PECL/NECL RAMBus Clock Buffer Function Inputs INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL Output OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_B OBUF_B OBUF_A OBUF_A OBUF_B OBUF_B OBUF_A OBUF_A OBUF_A OBUF_C OBUF_C OBUF_B OBUF_A
AN1503/D
Table Input/Output Selection
E416 E431 E445 E446 E451 E452 E457 E1651 E1652 Quint Diff. Line Receiver Diff. Flip-Flop Serial/Parallel Converter (pins OBUF_B) Parallel/Serial Converter (pins OBUF_B) Register Diff. Data Clock Diff. Register Triple Diff. Multiplexer Dual Output Comparator with Latch Dual Output Comparator with Latch INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL OBUF_D OBUF_A OBUF_A OBUF_A OBUF_A OBUF_A OBUF_B OBUF_A OBUF_A
Table Input/Output Selection
Device EL01 EL04 EL05 EL07 EL11 EL12 EL13 EL14 EL15 EL16 EL17 EL29 EL30 EL31 EL32 EL33 EL34 EL35 EL38 EL39 EL51 EL52 EL56 EL57 EL58 EL59 EL89 EL90 EL91 input OR/NOR input Diff. AND/NAND input AND/NAND input XOR/XNOR Diff. Fanout Buffer Impedance Driver Dual Fanout Buffer Clock Distribution Chip Clock Distribution Chip Diff. Receiver Quad Diff. Receiver Dual Diff. Data Clock Flip-Flop with Set&Reset Flip-Flop with Set&Reset Triple Flip-Flop with Set&Reset Divider Divider Clock Generation Chip Flip-Flop Clock Generation Chip 2/4, Clock Generation Chip Diff. Clock Flip-Flop Diff. Data Clock Flip-Flop Dual Diff. Multiplexer Diff. Multiplexer Multiplexer Triple Multiplexer Coaxial Cable Driver Triple Input PECL Output Translator Triple LVPECL/PECL Input Output Translator Function Inputs INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL INBUFTYPICAL Output OBUF_B OBUF_B OBUF_B OBUF_B OBUF_B OBUF_B OBUF_A OBUF_A OBUF_A OBUF_B OBUF_A OBUF_A OBUF_A OBUF_B OBUF_B OBUF_B OBUF_A OBUF_B OBUF_A OBUF_A OBUF_B OBUF_B OBUF_A OBUF_B OBUF_A OBUF_A OBUF_E OBUF_A OBUF_A
EL89 output swing terminated (see Figure
AN1503/D Netlists Schematics
PROTECTION CIRCUITRY
0.75 RESISTOR 0.405M, 2.2U
PULL DOWN RESISTOR
Figure Typical Input Buffer (INBUFTYPICAL) .SUBCKT INBUFTYPICAL .ENDS INBUFTYPICAL
AN1503/D
TN13P5 -3.7 TERMINATION TN13P5 -0.95 -1.75 0.35n 0.35n 1.5n 3.7n TN13P5 TNECLIPS TNECLIPS
STYLE TEMPERATURE COMPENSATION NETWORK
-1.33
OUTB
Figure Output Buffer (OBUF_A) .SUBCKT OBUF_A Q_Q1 TN13P5 Q_Q2 TN13P5 Q_Q3 TN13P5 Q_Q4 OUTB TNECLIPS Q_Q5 TNECLIPS R_R1 R_R2 R_R3 R_R4 R_R5 OUTB V_IN -1.33Vdc V_INB V_VCC 0Vdc V_VEE -5Vdc V_VTT -2Vdc V_VCS -3.7Vdc +PULSE -0.95 -1.75 0.35n 0.35n 1.5n 3.7n .END OBUF_A
AN1503/D
TN13P5 TN13P5 TN13P5 -0.95 -1.75 0.35n 0.35n 2.5n 5.7n TNECLIPS TNECLIPS OUTB
STYLE TEMPERATURE COMPENSATION NETWORK
-1.33 -3.7 TN13P5
TN13P5
TN13P5
TERMINATION
Figure Output Buffer (OBUF_B) .SUBCKT OBUF_B Q_Q1 TN13P5 Q_Q1a TN13P5 Q_Q2 TN13P5 Q_Q2a TN13P5 Q_Q3 TN13P5 Q_Q3a TN13P5 Q_Q4 TNECLIPS Q_Q5 TNECLIPS R_R1 R_R2 R_R3 R_R4 R_R5 OUTB R_R6 R_R7 OUTB V_IN -1.33Vdc V_INB V_VCC 0Vdc V_VEE -5Vdc V_VCS -3.7Vdc V_VTT -2Vdc +PULSE -0.95 -1.75 0.35n 0.35n 2.5n 5.7n .END OBUF_B
AN1503/D
STYLE TEMPERATURE COMPENSATION NETWORK
TNECLIPS TNECLIPS
-1.33 -3.91
TN13P5
TN13P5
TN13P5 TN13P5
TN13P5 TN13P5 -0.95 -1.75
TN13P5
TN13P5 TN13P5
TERMINATION
Figure Output Buffer (OBUF_C) .SUBCKT OBUF_C Q_Q1 TN13P5 Q_Q1a TN13P5 Q_Q1b TN13P5 Q_Q2 TN13P5 Q_Q2a TN13P5 Q_Q2b TN13P5 Q_Q3 TN13P5 Q_Q3a TN13P5 Q_Q3b TN13P5 Q_Q4 TNECLIPS Q_Q4a TNECLIPS R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 V_IN -1.33Vdc V_INB V_VCC 0Vdc V_VEE -5Vdc V_VCS -3.91Vdc V_VTT -2Vdc +PULSE -0.95 -1.75 .END OBUF_C
AN1503/D
TN13P5 TN13P5 TNECLIPS TNECLIPS OUTB
STYLE TEMPERATURE COMPENSATION NETWORK
-1.33
TN13P5 TN13P5
TN13P5 TN13P5 -0.95 -1.75 0.35n 0.35n 2.5n 5.7n
-3.7
TN13P5
TN13P5 TN13P5
TERMINATION
Figure Output Buffer (OBUF_D) .SUBCKT OBUF_D Q_Q1 TN13P5 Q_Q1a TN13P5 Q_Q1b TN13P5 Q_Q2 TN13P5 Q_Q2a TN13P5 Q_Q2b TN13P5 Q_Q3 N19458 TN13P5 Q_Q3a N19458 TN13P5 Q_Q3b N19458 TN13P5 Q_Q4 TNECLIPS Q_Q5 TNECLIPS R_R1 R_R2 R_R3 R_R4 R_R5 OUTB R_R6 R_R7 OUTB V_INB V_IN -1.33Vdc V_VCC 0Vdc V_VEE -5Vdc V_VCS N19458 -3.7Vdc V_VTT -2Vdc +PULSE -0.95 -1.75 0.35n 0.35n 2.5n 5.7n .END OBUF_D
AN1503/D
TN13P5 -3.67 TN13P5 TN13P5 TN13P5 TN13P5 TN13P5 -0.95 -1.75 0.2n 0.2n 2.2n 4.8n TNECLIPS TNECLIPS
OUTB
-1.33
TERMINATION
Figure Output Buffer (OBUF_E) .SUBCKT OBUF_E Q_Q1 TN13P5 Q_Q1a TN13P5 Q_Q2 TN13P5 Q_Q2a TN13P5 Q_Q3 TN13P5 Q_Q3a TN13P5 Q_Q4 TNECLIPS Q_Q5 OUTB TNECLIPS Q_Q6 Q_Q7 Q_Q8 Q_Q9 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 OUTB V_IN -1.33Vdc V_INB V_VCC 0Vdc V_VEE -5Vdc V_VTT -3Vdc V_VCS -3.67Vdc +PULSE -0.95 -1.75 0.2n 0.2n 2.2n 4.8n .END OBUF_E
AN1503/D
Style
RESISTOR 0.405M, 2.2U
Style
Style Style Figure Temperature Compensation Networks
ECLinPS Lite Circuitry
ECLinPS Circuitry
INPUT
DESD1 CBVCC Input Transistor QESD QESD
INPUT
DESD2 CBSUB RESISTOR 0.405M, 2.2U
Figure Protection Circuitry
AN1503/D
TNECLIPS TNECLIPS
OBUF_A
-1.33 -3.7 TN13P5 TN13P5 TN13P5 OUTB
-0.95 -1.75 0.35n 0.35n 1.5n 3.7n
TERMINATION
INBUFTYPICAL
TYPICAL INPUT BUFFER
Figure Typical Interconnect Schematic
AN1503/D
-0.8 VOUT, OUTPUT VOLTAGE -920 -1.2 -1.6 -1800 -2.0 TIME (ns) CROSS POINT
Figure Typical Output Waveform
AN1503/D
****************** Transistor Diodes Nominal SPICE Models *******************
.MODEL (IS=5.27E-18 BF=120 NF=1 VAF=30 IKF=6.48mA ISE=2.75E-16 BR=10 NE=2 VAR=5 IKR=567uA IRB=8.1uA RB=461.6 RBM=142.5 RE=21.6 RC=83.1 CJE=19.9fF VJE=0.9 MJE=0.4 XTB=0.73 CJC=25.1fF VJC=0.67 MJC=0.32 XCJC=0.3 CJS=49.6fF VJS=0.6 MJS=0.4 FC=0.9 TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=17.0mA ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) .MODEL (IS=8.56E-18 BF=120 NF=1 VAF=30 IKF=10.5mA ISE=4.48E-16 BR=10 NE=2 VAR=5 IKR=922uA IRB=13.2uA RB=291.4 RBM=95.0 RE=13.3 RC=62.7 CJE=29.9fF VJE=0.9 MJE=0.4 XTB=0.73 CJC=31.2fF VJC=0.67 MJC=0.32 XCJC=0.3 CJS=60.9fF VJS=0.6 MJS=0.4 FC=0.9 TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=27.6mA ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) .MODEL TN13P5 (IS=2.09E-17 BF=120 NF=1 VAF=30 IKF=25.7mA ISE=1.09E-15 BR=10 NE=2 VAR=5 IKR=2.25mA IRB=32.2uA RB=122.6 RBM=42.2 RE=5.44 RC=32.8 CJE=67.4fF VJE=0.9 MJE=0.4 XTB=0.73 CJC=53.8fF VJC=0.67 MJC=0.32 XCJC=0.3 CJS=103fF VJS=0.6 MJS=0.4 FC=0.9 TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=67.5mA ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) .MODEL (IS=1.18E-17 BF=120 NF=1 VAF=30 IKF=14.6mA ISE=6.20E-16 BR=10 NE=2 VAR=5 IKR=1.28mA IRB=18.2uA RB=213.1 RBM=71.2 RE=9.60 RC=50.4 CJE=39.9fF VJE=0.9 MJE=0.4 XTB=0.73 CJC=37.2fF VJC=0.67 MJC=0.32 XCJC=0.3 CJS=72.2fF VJS=0.6 MJS=0.4 FC=0.9 TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=38.3mA ISC=0 EG=1.11 XTI=5.2 PTF=0 KF=0 AF=1 NR=1 NC=2) .MODEL TNECLIPS (IS=2.27E-16 BF=120 NF=1 VAF=30 IKF=279mA ISE=1.19E-14 BR=10 NE=2 VAR=5 IKR=24.4mA IRB=349uA RB=15.98 RBM=4.17 RE=0.501 RC=11.1 CJE=611fF VJE=0.9 MJE=0.4 XTB=0.73 CJC=440fF VJC=0.67 MJC=0.32 XCJC=0.3 CJS=668fF VJS=0.6 MJS=0.4 FC=0.9 TF=8pS TR=1nS XTF=10 VTF=1.4V ITF=733mA ISC=0 EG=1.11 XTI=4.0 PTF=0 KF=0 AF=1 NR=1 NC=2) .MODEL CBVCC (IS=1.00E-15 CJO=527fF Vj=0.545 M=0.32 BV=14.5 IBV=0.1E-6 XTI=5 TT=1nS) .MODEL CBSUB (IS=1.00E-15 CJO=453fF TT=1nS)
AN1503/D
Package: SO-8 SPICE subcircuit file coupled transmission lines Transmission line model Conductor number-pin designation cross reference: Conductor number lumps: FASTEST APPLICABLE EDGE RATE: 0.076 COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 Connect chip side N**I board side N**O .SUBCKT LINES N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O L01WB N01I N01M 1.367e-09 N01M N01O 7.794e-10 N01M 2.445e-13 L02WB N02I N02M 1.287e-09 N02M N02O 5.473e-10 N02M 1.888e-13 L03WB N03I N03M 1.287e-09 N03M N03O 5.473e-10 N03M 1.901e-13 L04WB N04I N04M 1.367e-09 N04M N04O 7.723e-10 N04M 2.443e-13 L05WB N05I N05M 1.367e-09 N05M N05O 7.710e-10 N05M 2.478e-13 L06WB N06I N06M 1.287e-09 N06M N06O 5.489e-10 N06M 1.916e-13 L07WB N07I N07M 1.287e-09 N07M N07O 5.495e-10 N07M 1.930e-13 L08WB N08I N08M 1.367e-09 N08M N08O 7.786e-10 N08M 2.451e-13 K0102 0.1687 K0102WB L01WB L02WB 0.3400 C0102 N01O N02O 3.674e-14 K0103 0.0702 K0103WB L01WB L03WB 0.1847 K0203 0.1822 K0203WB L02WB L03WB 0.3505 C0203 N02O N03O 3.521e-14 K0204 0.0682 K0204WB L02WB L04WB 0.1847 K0304 0.1694 K0304WB L03WB L04WB 0.3400
AN1503/D
C0304 N03O N04O 3.675e-14 K0305WB L03WB L05WB 0.1847 K0405WB L04WB L05WB 0.3455 K0406WB L04WB L06WB 0.1847 K0506 0.1697 K0506WB L05WB L06WB 0.3400 C0506 N05O N06O 3.720e-14 K0507 0.0682 K0507WB L05WB L07WB 0.1847 K0607 0.1824 K0607WB L06WB L07WB 0.3505 C0607 N06O N07O 3.570e-14 K0608 0.0702 K0608WB L06WB L08WB 0.1847 K0708 0.1691 K0708WB L07WB L08WB 0.3400 C0708 N07O N08O 3.632e-14 .ENDS LINES
AN1503/D
Package: TSSOP-8 SPICE subcircuit file coupled transmission lines Transmission line model Conductor number-pin designation cross reference: counter-clockwise Conductor number lumps: FASTEST APPLICABLE EDGE RATE: 0.048 COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 R_SHORT 0.0001 X_777 N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O PACKAGE .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O R01WB N01I N01W 4.727e-02 L01WB N01W N01R 1.158e-09 N01R N01C 9.680e-04 N01C 8.978e-14 N01C N01O 7.466e-10 R02WB N02I N02W 3.815e-02 L02WB N02W N02R 9.835e-10 N02R N02C 9.680e-04 N02C 7.711e-14 N02C N02O 7.466e-10 R03WB N03I N03W 3.815e-02 L03WB N03W N03R 9.835e-10 N03R N03C 9.680e-04 N03C 7.704e-14 N03C N03O 7.465e-10 R04WB N04I N04W 4.727e-02 L04WB N04W N04R 1.158e-09 N04R N04C 9.680e-04 N04C 8.983e-14 N04C N04O 7.460e-10 R05WB N05I N05W 4.727e-02 L05WB N05W N05R 1.158e-09 N05R N05C 9.680e-04 N05C 8.983e-14 N05C N05O 7.460e-10 R06WB N06I N06W 3.815e-02 L06WB N06W N06R 9.835e-10 N06R N06C 9.680e-04 N06C 7.704e-14 N06C N06O 7.465e-10 R07WB N07I N07W 3.815e-02
AN1503/D
L07WB N07W N07R 9.835e-10 N07R N07C 9.680e-04 N07C 7.711e-14 N07C N07O 7.466e-10 R08WB N08I N08W 4.727e-02 L08WB N08W N08R 1.158e-09 N08R N08C 9.680e-04 N08C 8.978e-14 N08C N08O 7.466e-10 K0102 0.2481 K0102WB L01WB L02WB 0.1729 C0102 N01C N02C 2.283e-14 K0103 0.1067 K0103WB L01WB L03WB 0.0598 K0104 0.0593 K0203 0.2479 K0203WB L02WB L03WB 0.1463 C0203 N02C N03C 2.136e-14 K0204 0.1068 K0204WB L02WB L04WB 0.0598 K0304 0.2481 K0304WB L03WB L04WB 0.1729 C0304 N03C N04C 2.279e-14 K0506 0.2481 K0506WB L05WB L06WB 0.1513 C0506 N05C N06C 2.279e-14 K0507 0.1068 K0507WB L05WB L07WB 0.0615 K0508 0.0593 K0607 0.2479 K0607WB L06WB L07WB 0.1729 C0607 N06C N07C 2.136e-14 K0608 0.1067 K0608WB L06WB L08WB 0.0615 K0708 0.2481 K0708WB L07WB L08WB 0.1513 C0708 N07C N08C 2.283e-14 .ENDS PACKAGE
AN1503/D
Package: SO-20 SPICE subcircuit file coupled transmission lines Transmission line model Conductor number-pin designation cross reference: Conductor number lumps: FASTEST APPLICABLE EDGE RATE: 0.275 COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O N20I N20O BD_GND R01WB N01I N01W 3.732e-02 L01WB N01W N01R 9.678e-10 N01R N01C 1.700e-02 N01C BD_GND 4.680e-13 N01C N01O 3.814e-09 R02WB N02I N02W 8.086e-02 L02WB N02W N02R 1.822e-09 N02R N02C 1.300e-02 N02C BD_GND 1.924e-13 N02C N02O 2.724e-09 R03WB N03I N03W 9.122e-02 L03WB N03W N03R 2.033e-09 N03R N03C 9.000e-02 N03C BD_GND 1.377e-13 N03C N03O 1.814e-09 R04WB N04I N04W 7.878e-02 L04WB N04W N04R 1.780e-09 N04R N04C 8.000e-02 N04C BD_GND 1.484e-13 N04C N04O 1.551e-09 R05WB N05I N05W 6.634e-02 L05WB N05W N05R 1.531e-09 N05R N05C 7.000e-02
AN1503/D
R06WB L06WB R07WB L07WB R08WB L08WB R09WB L09WB R10WB L10WB R11WB L11WB R12WB L12WB R13WB L13WB R14WB L14WB R15WB L15WB R16WB L16WB R17WB L17WB N05C N05C N06I N06W N06R N06C N06C N07I N07W N07R N07C N07C N08I N08W N08R N08C N08C N09I N09W N09R N09C N09C N10I N10W N10R N10C N10C N11I N11W N11R N11C N11C N12I N12W N12R N12C N12C N13I N13W N13R N13C N13C N14I N14W N14R N14C N14C N15I N15W N15R N15C N15C N16I N16W N16R N16C N16C N17I N17W N17R N17C N17C BD_GND N05O N06W N06R N06C BD_GND N06O N07W N07R N07C BD_GND N07O N08W N08R N08C BD_GND N08O N09W N09R N09C BD_GND N09O N10W N10R N10C BD_GND N10O N11W N11R N11C BD_GND N11O N12W N12R N12C BD_GND N12O N13W N13R N13C BD_GND N13O N14W N14R N14C BD_GND N14O N15W N15R N15C BD_GND N15O N16W N16R N16C BD_GND N16O N17W N17R N17C BD_GND N17O 1.635e-13 1.508e-09 6.634e-02 1.531e-09 7.000e-02 1.584e-13 1.508e-09 7.878e-02 1.780e-09 8.000e-02 1.476e-13 1.553e-09 4.976e-02 1.206e-09 9.000e-02 1.322e-13 1.820e-09 8.086e-02 1.822e-09 1.300e-02 1.864e-13 2.725e-09 7.256e-02 1.655e-09 1.700e-02 4.681e-13 3.814e-09 3.732e-02 9.678e-10 1.700e-02 4.761e-13 3.795e-09 8.086e-02 1.822e-09 1.300e-02 1.888e-13 2.745e-09 9.122e-02 2.033e-09 9.000e-02 1.346e-13 1.879e-09 7.878e-02 1.780e-09 8.000e-02 1.496e-13 1.436e-09 6.634e-02 1.531e-09 7.000e-02 1.550e-13 1.464e-09 6.634e-02 1.531e-09 7.000e-02 1.568e-13 1.465e-09 7.878e-02 1.780e-09 8.000e-02 1.492e-13 1.437e-09
AN1503/D
R18WB L18WB R19WB L19WB R20WB L20WB K0102 K0102WB C0102 K0103 K0104 K0105 K0106 K0107 K0108 K0111 K0112 K0113 K0114 K0115 K0116 K0117 K0118 K0203 K0203WB C0203 K0204 K0205 K0206 K0207 K0208 K0209 K0211 K0212 K0213 K0214 K0215 K0216 K0217 K0218 K0304 K0304WB C0304 K0305 K0306 K0307 K0308 K0309 K0310 K0311 K0312 K0313 K0314 N18I N18W N18R N18C N18C N19I N19W N19R N19C N19C N20I N20W N20R N20C N20C L01WB N01C L02WB N02C L03WB N03C N18W N18R N18C BD_GND N18O N19W N19R N19C BD_GND N19O N20W N20R N20C BD_GND N20O L02WB N02C L03WB N03C L04WB N04C 9.122e-02 2.033e-09 9.000e-02 1.346e-13 1.892e-09 8.086e-02 1.822e-09 1.300e-02 1.880e-13 2.767e-09 7.256e-02 1.655e-09 1.700e-02 4.712e-13 3.825e-09 0.4539 0.1239 2.674e-13 0.2557 0.1742 0.1290 0.1011 0.0834 0.0636 -0.0789 -0.0755 -0.0716 -0.0594 -0.0669 -0.0657 -0.0672 -0.0625 0.3964 0.1239 1.529e-13 0.2341 0.1587 0.1206 0.0974 0.0760 0.0554 -0.0743 -0.0723 -0.0707 -0.0604 -0.0678 -0.0677 -0.0685 -0.0682 0.3767 0.1239 1.006e-13 0.2211 0.1564 0.1219 0.0956 0.0762 0.0639 -0.0654 -0.0662 -0.0688 -0.0614
AN1503/D
K0315 K0316 K0317 K0318 K0319 K0320 K0405 K0405WB C0405 K0406 K0407 K0408 K0409 K0410 K0411 K0412 K0413 K0414 K0415 K0416 K0417 K0418 K0419 K0420 K0506 K0506WB C0506 K0507 K0508 K0509 K0510 K0511 K0512 K0513 K0514 K0515 K0516 K0517 K0518 K0519 K0520 K0607 K0607WB C0607 K0608 K0609 K0610 K0611 K0612 K0613 K0614 K0615 K0616 K0617 K0618 K0619 K0620 K0708 K0708WB C0708 K0709 K0710 L04WB N04C L05WB N05C L06WB N06C L07WB N07C L05WB N05C L06WB N06C L07WB N07C L08WB N08C -0.0683 -0.0692 -0.0684 -0.0730 -0.0609 -0.0501 0.3731 0.1239 8.137e-14 0.2290 0.1637 0.1218 0.0976 0.0836 -0.0645 -0.0673 -0.0722 -0.0658 -0.0724 -0.0733 -0.0708 -0.0763 -0.0673 -0.0597 0.3775 0.1239 8.844e-14 0.2293 0.1565 0.1208 0.1013 -0.0636 -0.0679 -0.0742 -0.0683 -0.0737 -0.0741 -0.0704 -0.0760 -0.0684 -0.0622 0.3743 0.1239 7.898e-14 0.2214 0.1591 0.1293 -0.0607 -0.0668 -0.0752 -0.0700 -0.0741 -0.0742 -0.0690 -0.0754 -0.0697 -0.0652 0.3762 0.1239 1.016e-13 0.2343 0.1746
AN1503/D
K0711 K0712 K0713 K0714 K0715 K0716 K0717 K0718 K0719 K0720 K0809 K0809WB C0809 K0810 K0812 K0813 K0814 K0815 K0816 K0817 K0818 K0819 K0820 K0910 K0910WB C0910 K0913 K0914 K0915 K0916 K0917 K0918 K0919 K0920 K1011WB K1013 K1014 K1015 K1016 K1017 K1018 K1019 K1020 K1112 K1112WB C1112 K1113 K1114 K1115 K1116 K1117 K1118 K1213 K1213WB C1213 K1214 K1215 K1216 K1217 K1218 K1314 K1314WB L08WB N08C L09WB N09C L10WB L11WB N11C L12WB N12C L13WB L09WB N09C L10WB N10C L11WB L12WB N12C L13WB N13C L14WB -0.0581 -0.0657 -0.0756 -0.0707 -0.0736 -0.0730 -0.0667 -0.0735 -0.0692 -0.0661 0.3970 0.1239 1.545e-13 0.2564 -0.0591 -0.0723 -0.0685 -0.0698 -0.0693 -0.0624 -0.0702 -0.0681 -0.0670 0.4542 0.1239 2.677e-13 -0.0675 -0.0688 -0.0687 -0.0693 -0.0618 -0.0723 -0.0742 -0.0759 0.1239 -0.0616 -0.0675 -0.0668 -0.0685 -0.0609 -0.0731 -0.0773 -0.0803 0.4562 0.1239 2.679e-13 0.2725 0.1533 0.1161 0.0901 0.0702 0.0567 0.4103 0.1239 1.538e-13 0.2091 0.1398 0.1055 0.0812 0.0684 0.3577 0.1239
AN1503/D
C1314 N13C N14C 1.026e-13 K1315 0.2088 K1316 0.1474 K1317 0.1074 K1318 0.0930 K1319 0.0693 K1320 0.0578 K1415 0.3383 K1415WB L14WB L15WB 0.1239 C1415 N14C N15C 7.843e-14 K1416 0.1987 K1417 0.1302 K1418 0.1078 K1419 0.0825 K1420 0.0715 K1516 0.3631 K1516WB L15WB L16WB 0.1239 C1516 N15C N16C 9.179e-14 K1517 0.1988 K1518 0.1480 K1519 0.1072 K1520 0.0918 K1617 0.3380 K1617WB L16WB L17WB 0.1239 C1617 N16C N17C 7.810e-14 K1618 0.2096 K1619 0.1419 K1620 0.1183 K1718 0.3595 K1718WB L17WB L18WB 0.1239 C1718 N17C N18C 1.034e-13 K1719 0.2122 K1720 0.1565 K1819 0.4140 K1819WB L18WB L19WB 0.1239 C1819 N18C N19C 1.536e-13 K1820 0.2766 K1920 0.4603 K1920WB L19WB L20WB 0.1239 C1920 N19C N20C 2.679e-13 .ENDS PACKAGE
AN1503/D
Package: PLCC-28 SPICE subcircuit file coupled transmission lines Transmission line model Note: model assume ground plane below package model assume flag floating flag square, starts from left corner lead sequence counter clockwise Conductor number-pin designation cross reference: Conductor number lumps: FASTEST APPLICABLE EDGE RATE: 0.209 COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 ECLinPS usage requires input nodes used subcircuit call statement (X_777) that tied global ports(VCC, VCCO, internal die) have same global names subcircuit call statement(X_777). example, wirebonded certain design, then N20I should relabeled VCC. Again, change needs only incorporated X_777 subcircuit callout statement. Since this requires change netlist below, necessary each design have copy this file with appropriate changes made that required that design. R_SHORT ground 0.0001 X_777 N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O
AN1503/D
N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O N20I N20O N21I N21O N22I N22O N23I N23O N24I N24O N25I N25O N26I N26O N27I N27O N28I N28O ground PACKAGE .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O N15I N15O N16I N16O N17I N17O N18I N18O N19I N19O N20I N20O N21I N21O N22I N22O N23I N23O N24I N24O N25I N25O N26I N26O N27I N27O N28I N28O ground R01WB N01I N01W 1.124e-01 L01WB N01W N01R 2.474e-09 N01R N01C 1.120e-02 N01C ground 3.919e-13 N01C N01O 2.346e-09 R02WB N02I N02W 9.952e-02 L02WB N02W N02R 2.204e-09 N02R N02C 1.120e-02 N02C ground 1.950e-13 N02C N02O 2.180e-09 R03WB N03I N03W 9.164e-02 L03WB N03W N03R 2.042e-09 N03R N03C 1.100e-02 N03C ground 1.789e-13 N03C N03O 2.050e-09 R04WB N04I N04W 9.039e-02 L04WB N04W N04R 2.016e-09 N04R N04C 1.100e-02 N04C ground 1.748e-13 N04C N04O 2.030e-09 R05WB N05I N05W 9.164e-02 L05WB N05W N05R 2.042e-09 N05R N05C 1.100e-02 N05C ground 1.800e-13 N05C N05O 2.049e-09 R06WB N06I N06W 9.952e-02 L06WB N06W N06R 2.204e-09 N06R N06C 1.120e-02 N06C ground 1.936e-13 N06C N06O 2.184e-09 R07WB N07I N07W 1.124e-01 L07WB N07W N07R 2.474e-09 N07R N07C 1.120e-02 N07C ground 3.916e-13 N07C N07O 2.341e-09 R08WB N08I N08W 1.124e-01 L08WB N08W N08R 2.474e-09 N08R N08C 1.120e-02 N08C ground 3.916e-13 N08C N08O 2.341e-09 R09WB N09I N09W 9.952e-02 L09WB N09W N09R 2.204e-09 N09R N09C 1.120e-02 N09C ground 1.936e-13 N09C N09O 2.184e-09 R10WB N10I N10W 9.164e-02 L10WB N10W N10R 2.042e-09 N10R N10C 1.100e-02 N10C ground 1.800e-13 N10C N10O 2.049e-09 R11WB N11I N11W 9.039e-02
AN1503/D
L11WB R12WB L12WB R13WB L13WB R14WB L14WB R15WB L15WB R16WB L16WB R17WB L17WB R18WB L18WB R19WB L19WB R20WB L20WB R21WB L21WB R22WB L22WB R23WB L23WB N11W N11R N11C N11C N12I N12W N12R N12C N12C N13I N13W N13R N13C N13C N14I N14W N14R N14C N14C N15I N15W N15R N15C N15C N16I N16W N16R N16C N16C N17I N17W N17R N17C N17C N18I N18W N18R N18C N18C N19I N19W N19R N19C N19C N20I N20W N20R N20C N20C N21I N21W N21R N21C N21C N22I N22W N22R N22C N22C N23I N23W N23R N11R N11C ground N11O N12W N12R N12C ground N12O N13W N13R N13C ground N13O N14W N14R N14C ground N14O N15W N15R N15C ground N15O N16W N16R N16C ground N16O N17W N17R N17C ground N17O N18W N18R N18C ground N18O N19W N19R N19C ground N19O N20W N20R N20C ground N20O N21W N21R N21C ground N21O N22W N22R N22C ground N22O N23W N23R N23C 2.016e-09 1.100e-02 1.748e-13 2.030e-09 9.164e-02 2.042e-09 1.100e-02 1.789e-13 2.050e-09 9.952e-02 2.204e-09 1.120e-02 1.950e-13 2.180e-09 1.124e-01 2.474e-09 1.120e-02 3.919e-13 2.346e-09 1.124e-01 2.474e-09 1.120e-02 3.919e-13 2.346e-09 9.952e-02 2.204e-09 1.120e-02 1.950e-13 2.180e-09 9.164e-02 2.042e-09 1.100e-02 1.789e-13 2.050e-09 9.039e-02 2.016e-09 1.100e-02 1.748e-13 2.030e-09 9.164e-02 2.042e-09 1.100e-02 1.800e-13 2.049e-09 9.952e-02 2.204e-09 1.120e-02 1.936e-13 2.184e-09 1.124e-01 2.474e-09 1.120e-02 3.916e-13 2.341e-09 1.124e-01 2.474e-09 1.120e-02 3.916e-13 2.341e-09 9.952e-02 2.204e-09 1.120e-02
AN1503/D
R24WB L24WB R25WB L25WB R26WB L26WB R27WB L27WB R28WB L28WB K0102 K0102WB C0102 K0103 K0103WB K0104 K0105 K0106 K0107 K0124 K0125 K0126 K0127 K0128 C0128 K0203 K0203WB C0203 K0204 K0204WB K0205 K0206 K0207 K0225 K0226 K0227 K0228 K0304 K0304WB C0304 K0305 K0305WB K0306 K0307 K0308 N23C N23C N24I N24W N24R N24C N24C N25I N25W N25R N25C N25C N26I N26W N26R N26C N26C N27I N27W N27R N27C N27C N28I N28W N28R N28C N28C L01WB N01C L01WB N01C L02WB N02C L02WB L03WB N03C L03WB ground N23O N24W N24R N24C ground N24O N25W N25R N25C ground N25O N26W N26R N26C ground N26O N27W N27R N27C ground N27O N28W N28R N28C ground N28O L02WB N02C L03WB N28C L03WB N03C L04WB L04WB N04C L05WB 1.936e-13 2.184e-09 9.164e-02 2.042e-09 1.100e-02 1.800e-13 2.049e-09 9.039e-02 2.016e-09 1.100e-02 1.748e-13 2.030e-09 9.164e-02 2.042e-09 1.100e-02 1.789e-13 2.050e-09 9.952e-02 2.204e-09 1.120e-02 1.950e-13 2.180e-09 1.124e-01 2.474e-09 1.120e-02 3.919e-13 2.346e-09 0.4380 0.1463 2.394e-13 0.2472 0.0501 0.1557 0.1083 0.0742 0.0543 0.0506 0.0745 0.1092 0.1565 0.2194 5.401e-14 0.4331 0.1463 2.332e-13 0.2413 0.0708 0.1554 0.1051 0.0741 0.0619 0.0898 0.1237 0.1565 0.4342 0.2238 2.254e-13 0.2434 0.0853 0.1552 0.1083 0.0506
AN1503/D
K0327 K0328 K0405 K0405WB C0405 K0406 K0406WB K0407 K0408 K0409 K0427 K0428 K0506 K0506WB C0506 K0507 K0507WB K0508 K0509 K0528 K0607 K0607WB C0607 K0608 K0609 K0610 K0611 K0708 K0708WB C0708 K0709 K0710 K0711 K0712 K0809 K0809WB C0809 K0810 K0810WB K0811 K0812 K0813 K0814 K0910 K0910WB K0910 K0911 K0911WB K0912 K0913 K0914 K1011 K1011WB C1011 K1012 K1012WB K1013 K1014 K1015 K1112 K1112WB C1112 L04WB N04C L04WB L05WB N05C L05WB L06WB N06C L07WB N07C L08WB N08C L08WB L09WB N09C L09WB L10WB N10C L10WB L11WB N11C L05WB N05C L06WB L06WB N06C L07WB L07WB N07C L08WB N08C L09WB N09C L10WB L10WB N10C L11WB L11WB N11C L12WB L12WB N12C 0.0898 0.1092 0.4355 0.2238 2.282e-13 0.2418 0.0708 0.1558 0.0742 0.0613 0.0619 0.0745 0.4330 0.1463 2.324e-13 0.2474 0.0501 0.1087 0.0889 0.0506 0.4383 0.1463 2.402e-13 0.1558 0.1228 0.0889 0.0613 0.2174 0.0811 5.266e-14 0.1558 0.1087 0.0742 0.0506 0.4383 0.1463 2.402e-13 0.2474 0.0501 0.1558 0.1083 0.0741 0.0543 0.4330 0.1463 2.324e-13 0.2418 0.0708 0.1552 0.1051 0.0742 0.4355 0.2238 2.282e-13 0.2434 0.0853 0.1554 0.1083 0.0506 0.4342 0.2238 2.254e-13
AN1503/D
K1113 K1113WB K1114 K1115 K1116 K1213 K1213WB C1213 K1214 K1214WB K1215 K1216 K1314 K1314WB C1314 K1315 K1316 K1317 K1318 K1415 K1415WB C1415 K1416 K1417 K1418 K1419 K1516 K1516WB C1516 K1517 K1517WB K1518 K1519 K1520 K1521 K1617 K1617WB C1617 K1618 K1618WB K1619 K1620 K1621 K1718 K1718WB C1718 K1719 K1719WB K1720 K1721 K1722 K1819 K1819WB C1819 K1820 K1820WB K1821 K1822 K1823 K1920 K1920WB C1920 L11WB L12WB N12C L12WB L13WB N13C L14WB N14C L15WB N15C L15WB L16WB N16C L16WB L17WB N17C L17WB L18WB N18C L18WB L19WB N19C L13WB L13WB N13C L14WB L14WB N14C L15WB N15C L16WB N16C L17WB L17WB N17C L18WB L18WB N18C L19WB L19WB N19C L20WB L20WB N20C 0.2413 0.0708 0.1557 0.0745 0.0619 0.4331 0.1463 2.332e-13 0.2472 0.0501 0.1092 0.0898 0.4380 0.1463 2.394e-13 0.1565 0.1237 0.0898 0.0619 0.2194 0.0811 5.401e-14 0.1565 0.1092 0.0745 0.0506 0.4380 0.1463 2.394e-13 0.2472 0.0501 0.1557 0.1083 0.0742 0.0543 0.4331 0.1463 2.332e-13 0.2413 0.0708 0.1554 0.1051 0.0741 0.4342 0.2238 2.254e-13 0.2434 0.0853 0.1552 0.1083 0.0506 0.4355 0.2238 2.282e-13 0.2418 0.0708 0.1558 0.0742 0.0613 0.4330 0.1463 2.324e-13
AN1503/D
K1921 0.2474 K1921WB L19WB L21WB 0.0501 K1922 0.1087 K1923 0.0889 K2021 0.4383 K2021WB L20WB L21WB 0.1463 C2021 N20C N21C 2.402e-13 K2022 0.1558 K2023 0.1228 K2024 0.0889 K2025 0.0613 K2122 0.2174 K2122WB L21WB L22WB 0.0811 C2122 N21C N22C 5.266e-14 K2123 0.1558 K2124 0.1087 K2125 0.0742 K2126 0.0506 K2223 0.4383 K2223WB L22WB L23WB 0.1463 C2223 N22C N23C 2.402e-13 K2224 0.2474 K2224WB L22WB L24WB 0.0501 K2225 0.1558 K2226 0.1083 K2227 0.0741 K2228 0.0543 K2324 0.4330 K2324WB L23WB L24WB 0.1463 C2324 N23C N24C 2.324e-13 K2325 0.2418 K2325WB L23WB L25WB 0.0708 K2326 0.1552 K2327 0.1051 K2328 0.0742 K2425 0.4355 K2425WB L24WB L25WB 0.2238 C2425 N24C N25C 2.282e-13 K2426 0.2434 K2426WB L24WB L26WB 0.0853 K2427 0.1554 K2428 0.1083 K2526 0.4342 K2526WB L25WB L26WB 0.2238 C2526 N25C N26C 2.254e-13 K2527 0.2413 K2527WB L25WB L27WB 0.0708 K2528 0.1557 K2627 0.4331 K2627WB L26WB L27WB 0.1463 C2627 N26C N27C 2.332e-13 K2628 0.2472 K2628WB L26WB L28WB 0.0501 K2728 0.4380 K2728WB L27WB L28WB 0.1463 C2728 N27C N28C 2.394e-13 .ENDS PACKAGE
AN1503/D
Package: PLCC-20 ECLinPS Package Model (20-lead PLCC) (External Input Pin) (Internal Output Pin) .SUBCKT PKG20 CPKG 0.65PF RPKG1 RPKG2 RPKG3 LPKG1 0.9NH LPKG2 0.9NH .ENDS PKG20
RPKG1 LPKG1
RPKG2
RPKG3
LPKG2 CPKG 0.65
AN1503/D
Package: CDIP-16 ECLinPS Package Model (16-lead CERDIP PIN) (External Input Pin) (Internal Output Pin) (0V) .SUBCKT PKG16EP CPKG 1.3PF RPKG1 RPKG2 RPKG3 LPKG1 5.5NH LPKG2 5.5NH .ENDS PKG16EP ECLinPS Package Model (16-lead CERDIP CENTER PIN) (External Input Pin) (Internal Output Pin) (0V) .SUBCKT PKG16CP CPKG 0.7PF RPKG1 RPKG2 RPKG3 LPKG1 2.5NH LPKG2 2.5NH .ENDS PKG16CP
AN1503/D
APPENDIX Package Models Help SPICE netlist, X_777 circuit element (black box) with connections subcircuit:
circuit element X_777 connections N01I N01O N021 N02O N03I N03O N04I N04O +N05I N05O N061 N06O N07I N07O N08I N08O subcircuit PACKAGE
defined connection nodes circuit element declared
N01I N01O N021 N02O N03I N03O N04I N04O N05I N05O N061 N06O N07I N07O N08I N08O
subcircuit PACKAGE connected these same nodes:
.SUBCKT PACKAGE N01I N01O N021 N02O N03I N03O N04I N04O +N05I N05O N061 N06O N07I N07O N08I N08O N01I PACKAGE internal node connection chip N01O PACKAGE external node connecting lead
where:
Internal subcircuit PACKAGE several nodes each (See Figure TSSOP, netlist:
R02WB L02WB
N02I R02WB
N02I N02W N02R N02C N02C
N02W N02R N02C N02O
N02W
3.815e-02 9.835e-10 9.680e-04 7.711e-14 7.466e-10
N02R N02O N02C
L02WB
Figure
Parasitic Mutual inductance, capacitance, also represented. Such "K0102", where inductance from Lead (L01) Lead (L02) indicated.
K0102 K0102WB C0102 K0103 K0103WB K0104 K0203 K0203WB C0203 K0204 K0204WB L01WB N01C L01WB L02WB N02C L02WB L02WB N02C L03WB L03WB N03C L04WB 0.2481 0.1729 2.283e-14 0.1067 0.0598 0.0593 0.2479 0.1463 2.136e-14 0.1068 0.0598
AN1503/D
N01I R01WB N01W L01WB K0103WB N01C C0102 K0102WB K0104 N02I R02WB N02W L02WB K0203WB N02C N02R K0102 N02O K0103 K0102 N01R N01O
N03I R03WB
N03W L03WB
N03R N03C
N03O
N04I R04WB
N04W L04WB
N04R N04C
N04O
Figure
AN1503/D
ECLinPS Plus trademark Semiconductor Components Industries, LLC.
Semiconductor trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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AN1503/D

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