Application Note 2001, ver. Introduction Density increa

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LVDS Signaling Using APEX Device Pins
Application Note
2001, ver.
Introduction
Density increases programmable logic devices (PLDs) have users integrate more functions into today's PLDs. This increase functionality allowed PLDs play major role transmitting data between boards nearby systems, making accessibility variety buffers with different capabilities important feature. LVDS data interface standard defined TIA/EIA-644 IEEE Std. 1596.3 specifications. LVDS become popular with system designers throughout industry variety applications. From high-speed backplane applications high-end switch box, LVDS proven technology choice. LVDS differential signaling standard, high noise immunity voltage swing allows data transfers high speeds.
APEX Devices
Altera® APEXdevices offer wide range buffers. Designers various types buffers such LVTTL, LVCMOS, SSTL-2, SSTL-3, CTT, GTL+. However, highest performance standard available APEX 20KE APEX 20KC devices LVDS standard. Altera's APEX 20KE APEX 20KC devices have input output dedicated True-LVDSchannels equipped with embedded serializer/deserializer phase-locked loop (PLL) technology capable transferring data megabits second (Mbps) channel. multiplexing parallel data allows system designers reduce width between points while transmitting data same bandwidth. When application requires more than LVDS channels, APEX 20KE APEX 20KC devices enable their general-purpose pins communicate with other LVDS devices speeds MHz. This technique used APEX 20KE APEX 20KC device package.
Altera Corporation
A-AN-138-01
138: LVDS Signaling Using APEX Pins
This application note describes utilize APEX 20KE APEX 20KC general purpose pins LVDS signaling. This application note covers following topics:
Overview LVDS characteristics Overview APEX standards Board implementation SPICE simulation report QuartusII software implementation
LVDS Characteristics
Figures show typical LVDS application signal levels. Input signals converted LVDS signals transmitter. Typically signals transmitted over pair traces, combination trace, connectors, cables common. media then terminated resistor, because LVDS buffers current, driven combination termination resistor transmitter's current, creates signal swing approximately receiver's inputs. receiver's threshold region ±100 common mode above below 1.2-V offset voltage.
Figure LVDS Application
Driver
Receiver
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure Typical LVDS Signal Levels
+350 +100 Differential Input Signal Differential -100 V1A=VA-VB -350
Table displays LVDS parameters commonly used chip vendors. more information LVDS signaling, International Engineering Consortium site (http://www.iec.org).
Table APEX 20KE APEX 20KC LVDS Levels 3.3-V Specifications Symbol
VCCINT VCCIO
Parameter
Core supply voltage supply voltage Differential output voltage Change between Output offset voltage
Conditions
1.71
Typical
1.89
Units
1.125
1.125
1.375
Change between Differential input threshold Receiver differential input resistor -100
APEX 20KE APEX 20KC Block Standards
Altera's APEX 20KE APEX 20KC devices have eight programmable banks that support many standards. eight banks include True LVDS input output buffers. LVDS buffers strategically placed edge help reduce possible reflection skew. Figure shows APEX 20KE APEX 20KC device banks.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure APEX 20KE APEX 20KC Device Blocks
Bank Bank
Bank
LVDS Transmitter Block Bank
Regular Blocks Support LVTTL LVCMOS PCI-X GTL+ SSTL-2 Class SSTL-3 Class HSTL Class Individual Power
Bank LVDS/LVPECL Input Block
Bank
Bank
Notes:
Bank
first pins that border LVDS blocks only used input maintain acceptable noise
level VCCIO signal.
LVDS input output blocks used LVDS, they support standards used input, output, bidirectional pins with VCCIO
Voltage-Referenced Standards
Many standards externally-supplied reference voltage VREF determine incoming logic level. example, when input level above VREF voltage, logical high, when input level below VREF voltage, logical low. APEX 20KE APEX 20KC devices support VREF bank.
more information voltage-referenced standards, refer Application Note 117: Using Selectable Standards Altera Devices.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Receiving LVDS Signals Using General-Purpose APEX pins
Receiving LVDS signals general-purpose pins accomplished selecting SSTL-2 Class terminating incoming LVDS signals using resistors where their junction connecting VREF bank used. This scheme shown Figure SSTL-2 Class buffers have VREF value similar LVDS common mode voltage; therefore, well suitable receiving LVDS signals.
more information receiving LVDS signals using general-purpose APEX pins, refer Application Note 117: Using Selectable Standards Altera Devices. When more than LVDS channel connected same bank, VREF supplied first channel. other channels terminated utilizing standard resistor.
Figure Receiving LVDS Signals
V(OUTA) Microstrip V(N1A) APEX 20KE Driver Channel VREF V(OUTB) LVDS Driver V(N1B) SSTL-2 Input Buffer Class SSTL-2 Receiver Design V(OUT)
Driver
Channel
SSTL-2 Receiver
Design
Altera Corporation
138: LVDS Signaling Using APEX Pins
LVDS SSTL-2 SPICE Simulation
SPICE simulations utilized validate design technique. simulation using Altera's LVDS SSTL-2 SPICE models. This method simulated using APEX 20KE APEX 20KC device driver receiver SPICE models. Signals were monitored driver output VOUTB, VOUTB, receiver input VN1A, VN1B, receiver's output VOUT.The model media pair -in. differential microstrip traces. Figure schematic representation simulation setup. typical signal applied LVDS driver signals were monitored driver output, receiver input, receiver output. Figure demonstrates result this simulation using nominal models. results across industrial temperature (fast slow models) were similar. simulation shows that scheme would work well point-to-point topology. simulated circuit also validated laboratory environment using test board. Figure LVDS Transmitter SSTL-2 Receiver SPICE Simulation
Altera Corporation
138: LVDS Signaling Using APEX Pins
APEX 2.5-V Buffers LVDS
interface from non-LVDS buffer LVDS receiver buffer implemented using resistor network. resistors attenuate driver outputs levels similar LVDS signaling recognition LVDS receiver. This method also simulated using APEX 2.5-V drivers LVDS receiver SPICE models. Driver inputs (ina inb), resistor network (LVDSa1 LVDSb1), receiver inputs (LVDSa LVDSb) were monitored. Figure shows schematic representation setup.
Figure General Purpose LVDS Receiver
APEX 20KE LVDSa1 Mirco Resistor Network Mirco LVDSb1 LVDSb Receiver LVDSa
2.5-V Transmitter
Internal signal drive with LVDS 2.5-V Transmitter Insert into design
LVDS 2.5-V SPICE Simulation
simulation with models used previous experiment. media also kept constant: pair 6-in. differential microstrip traces. Signals were applied drivers with opposite polarity were monitored various locations circuit. Figure demonstrates result this evaluation room temperature using nominal models. results across industrial temperature (fast slow models) were similar. SPICE simulation shows data correctly transferred destination.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure General Purpose LVDS Receiver SPICE Simulation
Implementing LVDS with Quartus Software
This section describes implement LVDS using general-purpose pins Quartus software. effective transmit receive data source synchronous clocking system. This method utilizes clock transmit capture data. Designers also synchronous clocking method, which does require special design technique.
LVDS Receiver Interface
Implementing LVDS using APEX 20KE APEX 20KC general purpose pins require that differential signal first converted singleended signal. LVDS receiver interface utilizes SSTL-2 Class standard implementation. Because conversion done external device, functional design would entered using single-ended buffers. LVDS signal converted SSTL-2 Class using external resistors board (see Figure
Altera Corporation
138: LVDS Signaling Using APEX Pins
Quartus software reference design capturing serial stream data, both clock data driven into circuit. signal inverted sample LVDS data middle data eye. output register will drive shift register which converts incoming serial data parallel data (four bits time). data then driven LPM_FIFO_DC dual-clock first-in first-out (FIFO) controlled counter. counter enables FIFO read data four bits time while circuit writes into FIFO every clock cycle. standard assignments assigned procedure outlined LVDS Assignment Procedures section.
Figure Receiver Implementation
LMP_SHIFTREG DATA_I CLRN rdreq rdclock shiftin LMP_FIFO_DC data[] wrreq wrclock wrempty rdfull Fifo_Empty outoffifo[3.0] Fifofull
AND2 cout[1] cout[0]
Read_CLK_from_internal_design counter counter clock q[1.0] cout[1.0] Read_REQ_from_internal_design
Figure shows Quartus software reference design capturing data that presented device bus. Both clock data driven into device. data captured FIFO read into design. designer controls data read into design through rdreq internal input pin.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure Alternate Receiver Implementation
SSTL_DATA_IN SSTL_CLK_IN CLRN wrreq rdreq clock full empty Full_Flag Empty_Flag From_Design R1fifo data[0] q[0] dataout_to_Design
words
LVDS Transmitter Design
order transmit data, 2.5-V drivers convert signal-ended signals differential outputs. sample design shown Figure transmitter design uses four PLLs within APEX 20KE APEX 20KC device provide multiples clock input. clocks synchronize outgoing clock data signals. data connected flip flops with connected inverter. LVDS_DATA_p LVDS_DATA_n signals clocked multiple input clock PLL. differential clock created using same technique connected TFF. Place LVDS output pairs that skew between positive negative signals differential pair minimized. necessary, APEX 20KE APEX 20KC device registers select adjacent pins package.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure LVDS Transmitter Design Implementation
CLK_1P_1N altclklock inclock TFFE clock0 clock1 CLRN clock_out_n clock_out_p
CLRN
CLRN
CLRN
LVDS_DATA_p
CLRN
LVDS_DATA_n
CLRN
Some logic array designs 78-MHz clock speed. Therefore, altlock megafunction multiply logic array frequency four, PLL's output transmit data. design shown Figure shows this system implementation Quartus software.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure Transmitter Implementation Quartus Software
counter counter clock q[1.0] out[1.0]
CLK78MHz inclock clock0 out[0] clock1
CLKOutN
CLRN
CLKOutP
CLRN
Data1_155Mbs data1 result data0 Data_155Mbs DFFE CLRN out[1] DataOutP DFFE CLRN DataOutN
CLRN
CLRN
systems where LVDS data rate multiple systems clock, combination counter FIFO cross domain boundaries (see Figure 12).
Altera Corporation
138: LVDS Signaling Using APEX Pins
Figure Transmitter Implementation Quartus Software
CLK155MHz inclock clock0 clock1 CLRN CLKOutN
CLRN CLKOutP
CLRN DFFE DATAOut
CLRN
DFFE shifts2 clock shifts1 q[3.0] DATAOutP
CLRN
LMP_FIFO_DC data[] wrreq wrclock wrempty rdfull CLRN rdreq rdclock FIFO_empty
LMP_SHIFTREG
data FIFOfull
AND2
Systemclk_33_MHz
counter Systemclk_33_MHz clock q[1.0] Read_CLK_by_internal_design Read_Rec_by_internal_design Read Request Read
Altera Corporation
138: LVDS Signaling Using APEX Pins
LVDS Assignment Procedures
APEX 20KE APEX 20KC device pins assigned specific banks. When assign signal select SSTL-2 Class standard, pins within that bank operate Therefore, assign SSTL-2 Class pins same bank avoid consuming pins unnecessarily.
Standard Assignment
following steps assign standards. With project open Quartus development software, choose Compiler Settings (Processing menu). Select Chips Devices Tab. Family: field select APEX 20KE. Target device field, select radio button titled Specific device selected 'Available devices' list. Available devices: field, select appropriate device. Click Assign Pins button Target device field. Assignments window will open. Available Pins Existing Assignments: field select assignment. Type name clock signal data Name: field Assignment category. Standard field, select SSTL-2 from drop-down list available selections.
Click button create standard assignment. Click exit Assignments window. Click Apply button Compiler Settings window changes take effect. Click exit Compiler Settings window.
Altera Corporation
138: LVDS Signaling Using APEX Pins
Assign VREF within same bank SSTL-2 Class pins. previous procedure assign VREF pin. SSTL-2 Class standard must selected VREF pin. enable used VREF pin, check that enables feature Reserve (even does exist design file) select VREF from drop down list associated with reserve field. reference designs discussed this application note available Altera site http://www.altera.com.
Conclusion
Altera's transmitter True-LVDS solution preferred choice today's high-speed, high-performance systems. applications requiring more than LVDS pins where True LVDS pins available, external resistor network used interface LVDS signals APEX 20KE APEX 20KC devices general-purpose pins. more information standards supported APEX 20KE APEX 20KC devices, Application Note 117: Using Selectable Standard Altera Devices.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, APEX 20KE, APEX 20KC, Quartus, Quartus True LVDS trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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