Overview explosive growth Internet boosted demand highspeed data

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SRAM Controller Function
Overview
explosive growth Internet boosted demand highspeed data communication systems that require fast processors highspeed interfaces peripheral components. While processors these systems have improved performance, static memories have kept pace. SRAM architectures evolving support high throughput requirements current systems. such architecture quad data rate (QDR) SRAM, which provide bandwidth improvements more than four times greater than other SRAM architectures. Most existing SRAM solutions were designed have interfaces that transfer data efficiently PC-type single input/output (I/O) applications. contrast, most networking applications require continuous data transfer between SRAM memory controller (e.g., continous transitions between read write cycles through memory). Single devices like standard synchronous pipelined SRAMs perform well these applications. Consortium, comprised Cypress Semiconductor, Integrated Device Technology, Inc., Micron Technology, designed SRAM architecture high-performance networking systems such routers Aswitches. SRAMs designed handle transfer four data words through SRAM single clock cycle. memory provides simultaneous reads writes, well zero latency increased data throughput, guaranteeing simultaneous access same address location. This application note describes implementation SRAM controller Altera® APEX20KE programmable logic device. implementation allows designer interface with Cypress CY7C1302 SRAM device 100-MHz clock speed, giving overall system performance gigabits second (Gbps). Figure compares performance SRAMs versus other SRAM architectures. comparison assumes that interfaces operate MHz. figure shows that SRAM outperforms other types SRAM outperforms other architectures four times networking application.
Altera Corporation
A-AN-133-01
133: SRAM Controller Function
Figure Performance Comparison
Gigabits/second 10.00 Pipe-125 NoBL-125 DDR-125
5.00
0.00 Cache Networking
Source: Consortium
APEX Interface
When using SRAM system, memory controller generates signals needed SRAM serves interface system. Altera APEX 20KE devices-with their speed configurability-are ideal such function. SRAM controller implemented APEX 20KE device provide simplified interface industrystandard SRAM device. Figure provides block diagram system. Figure Block Diagram
APEX 20KE Device WADDR[17.0] RADDR[17.0] WDATA[35.0] RDATA[35.0] CMD[1.0] INCLK PLL_LOCKED K_BAR Memory Controller SRAM Interface Signals A[17.0] DOUT[17.0] DIN[17.0] BWS_BAR[1.0] RPS_BAR WPS_BAR SRAM
Altera Corporation
133: SRAM Controller Function
Table describes function each SRAM-APEX interface. Table SRAM Interface Signals Signal Type
Clock Outputs Clock Input
Signal Name
K_bar
Description
Clock inputs SRAM. transactions initiated synchronously rising edge K_bar. K_bar back C_bar, respectively, SRAM output clocks. controller uses clock feedback input clocking data from SRAM. Active-low read port select signal, sampled rising edge Active-low write port select signal, sampled rising edge
Control Outputs
RPS_bar WPS_bar
BWS_bar[1.0] Active-low byte write select signal, sampled rising edge This signal used individually select which bytes written read. Address Outputs A[17.0] SRAM uses same address signals read write ports. CY7C1302 device, address inputs SRAM sampled rising edge reads rising edge K_bar writes. Read data output from SRAM. words transferred from SRAM during each clock cycle because outputs data rising edges C_bar. Data output SRAM rising edge captured controller subsequent falling edge Data output rising edge C_bar captured subsequent rising edge Write data input SRAM. Data captured rising edges K_bar. Therefore, words transferred SRAM during each clock cycle.
Data Inputs
Dout[17.0]
Data Outputs
Din[17.0]
System-Level Issues
This section describes some issues considered when implementing SRAM controller APEX 20KE device. Because SRAM interface high speed, special care must taken when designing controller interface. Design-specific issues include Expanded HSTL interface, clock generation, delay minimization.
HSTL Pins
HSTL standard required SRAM interface. APEX devices CY7C1302 SRAM devices support Expanded HSTL, which uses 1.8-V supply voltage (VDDQ). Characterization data shown that APEX 20KE devices drive receive Expanded HSTL signals MHz.
Altera Corporation
133: SRAM Controller Function
HSTL voltage-referenced standard, very similar SSTL standard, which supported Quartus software. implement Expanded HSTL interface, perform following procedure. Quartus software, Assignment Organizer make standard assignment SSTL-2 Class APEX pins that interface with SRAM (A[17.0], din[17.0], dout [17.0], rps_bar, wps_bar, bws_bar[1.0], K_bar, implement reference voltage pins required Expanded HSTL standard, Quartus software place VREF assignments banks that hold interface pins. same VREF placement rules apply Expanded HSTL SSTL. Using Standards Quartus Software White Paper further details placing SSTL VREF pins. Quartus software generate SRAM Object File (.sof) APEX device. same generated with SSTL pins used Expanded HSTL pins. board, connect VCCIO each Expanded HSTL bank Connect VREF pins 0.75 terminate Expanded HSTL signals specified SRAM vendor.
Clock Generation
clocking scheme used controller important maintain high frequency operation. This clocking scheme requires PLL, which available on-chip APEX 20KE devices, three global clock resources APEX device. (When ordering devices, sure specify suffix PLL-enabled devices.) following clocks required SRAM controller: Input clock from system controller clocks SRAM clocks K_bar Controller feedback clock
system must supply input clock, nominally MHz. This clock then on-chip PLL, which generates clock clock controller. clock inputs data from system pipes through controller. data address, control lines SRAM clocked double data rate using clock.
Altera Corporation
133: SRAM Controller Function
controller must also generate differential clock signal K_bar) SRAM device. This action performed using clock clock flipflop register true complement output. result clock signal 180-degree-phase-shifted clock signal (K_bar). K_bar output from APEX device sent SRAM along with data, address, control lines. This clocking scheme negates effect signal skew write read request operations, because propagation delays K_bar from APEX device SRAM equal delays data signals. proper operation, board designer should take care equalize trace length (and therefore flight times) data address, control signals with K_bar clocks. When clock reaches SRAM, back controller clock used clock data arriving from SRAM controller. Because SRAM outputs also registered with clock data sent from SRAM arrives controller same time clock, reducing skew read operations. board designer should equalize trace lengths data clock signal. Additionally, Altera recommends that board designer place APEX device adjacent SRAM circuit board. This positioning keeps trace length minimum further minimizes skew caused board delay.
Timing
Because data exchanged between controller SRAM high speeds, special care must taken avoid setup hold violations SRAM APEX device. This section discusses timing issues that arise when designing high-speed interface.
Write Cycle
When designing proper write-cycle timing, meeting setup hold requirements SRAM primary concern. Setup hold specifications CY7C1302 (100-MHz speed grade) each. Both clock data signals driven from controller, clock-to-output delay from APEX device pins same both sets pins. determined characterization, clock-to-output delay from APEX pins when using Expanded HSTL range from (depending temperature) consistent both sets pins. same principle applies board delay, because flight times clock data signals equalized.
Altera Corporation
133: SRAM Controller Function
K_bar outputs clocked from registers, clkout clkout_bar. these registers placed logic element (LE) registers adjacent logic array block (LAB), their clock-to-output time only slightly greater than clock-to-output time data address signals. Because K_bar clocked positive edge clock while data address clocked negative edge, there cushion each timing purposes. following calculations apply controller-to-SRAM data transfers. calculation allows 1.2-ns difference between clock data/address tCO, board skew. [tCO(APEX Clock) tCO(APEX Data Address)] Board Skew (Clock Data) (SRAM) [4.9 [tCO(APEX Data Address) tCO(APEX Clock)] Board Skew (Clock Data) tH(SRAM) [3.4 Figure shows write cycle timing waveform SRAM interface pins MHz. Figure Write Cycle Timing Waveform
(APEX Clock) CLK1X CLK2X K_BAR WPS_BAR BWS_BAR
D(A)
D(A+1)
(APEX Data)
(SRAM)
(SRAM)
Altera Corporation
133: SRAM Controller Function
Read Cycle
When read data sent from SRAM controller, setup times APEX device must met. setup times achieved using programmable delay features available APEX device. Apply following setting Quartus software programmable delay feature, which decreases delay from dout input pins input registers, thereby decreasing setup requirement: With this setting turned setup requirement dout pins APEX 20KE device Hold time requirements remain Arrival time dout signal determined clock-to-output specification SRAM. CY7C1302, maximum value while minimum value (i.e., data output hold time tDOH) Board delay ignored, because flight times signal dout roughly equal. Regardless, timing calculation allows some skew between clock data lines. Data sent SRAM rising edge captured controller falling edge clock speed MHz, there 5-ns window between rising falling edges. Subtracting clockto-output delay leaves setup time APEX pins. This timing meets setup requirement with margin signal skew. following calculations apply data transfer from SRAM controller: (SRAM) Board Skew (Clock Data) (APEX) tDOH (SRAM) Board Skew (Data Clock) (APEX) Figure shows read cycle timing waveform SRAM interface pins MHz.
Altera Corporation
133: SRAM Controller Function
Figure Read Cycle Timing Waveform
(APEX Clock) CLK1X CLK2X K_BAR RPS_BAR DOUT (APEX Address)
Q(A) Q(A+1)
(SRAM) (SRAM)
(SRAM) (APEX)
(APEX)
Conclusion
SRAM architecture designed greatly increase memory bandwidth communications systems. their speed programmability, APEX 20KE devices ideal implementation SRAM controller. more information refer following documents: Cypress CY7C1302V25 SRAM data sheet Altera Using Standards Quartus Software White Paper
References
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, APEX 20KE, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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Altera Corporation

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