with Altera Devices Functions Application Note September 200

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with Altera Devices Functions Application Note September 200

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Implementing W-CDMA System
with Altera Devices Functions
Application Note
September 2000, ver.
Introduction
wireless world, demand advanced information services growing. Voice low-rate data services insufficient world where high-speed Internet access taken granted. trend toward global information networks that offer flexible multimedia information services users demand, anywhere, anytime. need support bandwidth-intensive multimedia services places challenging demands cellular systems networks. International Telecommunications Union (ITU), under initiative named IMT-2000, devised number standards that support these requirements. However, third-generation wireless standards will continue evolve future services technologies identified. Systems that implement these standards must flexible enough accommodate changes easily. Additionally, because demand third-generation products still unknown, diffcult justify high non-recurring engineering (NRE) costs. ASICs-with their associated costs long turnaround times-are expensive respin. example, lower-limit block level turbo specification changed four months after specification initially released. ASIC design implementing turbo function based initial specification would need reworked. advanced capacity enhancement techniques, which contemplated academic circles, require high throughput platform. programmable solution that provides flexibility, zero costs, required throughput right solution third-generation wireless applications. Altera® high-density, high-performance programmable logic devices (PLDs) combined with intellectual property (IP) functions Quartusdevelopment software provide complete solution wireless communications market. example, Altera's high-density APEXdevices implement thousands multiply-accumulators (MACs), making feasible develop very high throughput platform. This application note describes implement wideband code division multiple access (W-CDMA) system that conforms IMT-2000 standard using Altera devices functions. information about Altera devices, functions, software tools refer Altera site http://www.altera.com.
Altera Corporation
A-AN-129-01
129: Implementing W-CDMA System with Altera Devices Functions
W-CDMA Transmitter
This section describes digital architecture downlink transmitter that supports W-CDMA standard. Figure shows block diagram transmitter. Light shaded blocks implemented Altera PLD; dark shaded blocks implemented software embedded processor Excaliburembedded processor PLD.
Figure W-CDMA Transmitter Architecture
Embedded Processor Application Programmable Logic Application OVSF Code Generator Encoder Data Convolutional Encoder
FIlter
Interpolation
Block Interleaver
Baseband Transmit Filter
Turbo Encoder Scrambling Code Cyclic redundancy code Digital analog convertor Numerically controlled oscillator OVSF Orthogonal variable spreading Root raised cosine FIlter Interpolation
conform W-CDMA standard, cyclic redundancy code (CRC) bits added error detection, error correction bits added channel coding. data then spread with user- channel-specific code produce data stream given chip-rate. spread data stream scrambled with Gold code that multipath signals uniquely identified decoded receiver. transmit signal within specified bandwidth, data bits shaped using pulse shaping filter. Next, signal goes through carrier modulation up-conversion radio frequency (RF), then sent antenna transmitted over air. various functions used transmitter described following sections, including: checker Forward error correction (FEC) Block interleaver Orthogonal variable spreading (OVSF) channelization codes Scrambling codes Quadrature phase shift keying (QPSK) modulator
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Checker
standard specifies four different polynomials checking: gCRC24(D) gCRC16(D) gCRC12(D) gCRC8(D)
Altera Corporation
Altera provides MegaCore® function, which implement these polynomials therefore meets third-generation standard requirements. function fully parameterized, including: Variable length generator polynomial Variable data width from width polynomial initial value
Forward Error Correction
standard defines encoding schemes support different quality services. voice MPEG4 applications, standard employs convolutional encoding, which gives error rate (BER) 10-3. data applications, standard uses turbo encoding, which gives 10-6.
Convolutional Encoder
required specification convolutional encoder given below: Basestation: rate Mobile: rate
convolutional encoder uses delay elements XORs. Altera provides building blocks optimized Altera PLDs library parameterized modules (LPM). these functions, example LPM_SHIFTREG LPM_XOR, implement convolutional encoder.
129: Implementing W-CDMA System with Altera Devices Functions
Turbo Encoder
Turbo encoding gives relatively large encoding gain with reasonable computational complexity. This encoding scheme useful data services that permit longer transmission delays. W-CDMA specifications are: Parallel concatenated convolutional code (PCCC) with 8-state constituent encoders interleaver Block size: 5,114 bits Puncturing: rate puncturing); rate (puncturing)
Figure Turbo Encoder Block Diagram
Data
Input
Altera provides turbo encoder MegaCore function, which meets WCDMA standard. Figure block diagram. turbo encoder uses 3,000 logic elements (LEs) embedded system blocks (ESBs) when implemented APEX device.
Encoder
Interleaver
Encoder
Puncture
Parity
Block Interleaver
Systems that transmit digital data require error correction reduce effect spurious burst noise from channel that corrupt data. block interleaving function writes data into rectangular matrix then reorders columns matrix based transmission time interval (TTI) value. APEX device ESBs store matrix elements. permute columns, data read column column right sequence. software routine running embedded processor generate correct read address.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
OVSF Channelization Codes
Transmissions from single source separated channelization codes, i.e., download connections within sector dedicated physical channel uplink. OVSF channelization code preserves orthogonality between different physical channels using tree-structured orthogonal code. tree-structured code generated recursively using following equation:
Because process recursive, implement OVSF code generation software Excalibur embedded processor PLD. device's memory blocks store intermediate results. Other operations within basestation subsystems need refer OVSF code assigned different users. content-addressable memory (CAM) Altera devices store code that quickly accessed when needed. Designing Wireless Basestations with APEX White Paper more information.
Scrambling Codes
Scrambling codes make direct sequence CDMA (DS-CDMA) technique more effective multipath environment. significantly reduces auto-correlation between different time delayed versions spreading code that different paths uniquely decoded receiver. Additionally, scrambling codes separate users basestation sectors from each other allowing them manage their OVSF trees without coordinating amongst themselves. W-CDMA specification scrambling code generator described below. Downlink: 38,400 chips Gold code different scrambling codes Grouped efficient cell search
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Uplink: Long Code: 38,400 chips Gold code Short Code: chips very large Kasami code
Figure Scrambling Code Generator
design scrambling code generator using same functions used convolutional encoder (i.e., LPM_SHIFTREG LPM_XOR). Figure shows scrambling code generator schematic. design highlights ease with which generator designed using functions.
Figure shows downlink scrambling code block diagram.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure Scrambling Code Generator Schematic (Downlink)
This design uses LEs, which resources available EPF20K100E device.
Shift Register load setreg data1[17.0] load sset data[17.0] shiftout q[17.0] q1[17.0] I_out
q1[0] q1[7]
clock enable shiftin
Shift Register load sset data[17.0] shiftout q[17.0] q2[17.0]
data[17.0] q2[0] q2[5] q2[7] q2[10]
clock enable shiftin
q1[4] q1[6] q1[15] q2[5] q2[6] q2[8] q2[9] q2[10] q2[11] q2[12] q2[13] q2[14] q2[15]
Q_out
QPSK Modulator
Figure shows modulator that performs baseband filtering carrier modulation digital domain.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure Digital Modulator
Filter Symbol Mapper Filter Sine Cosine
Filter
Filter
Digital
Using digital modulator instead analog several advantages, including: Channels selected digital domain using numerically controlled oscillator (NCO) digital mixer. direct digital synthesizer gives more precise frequency selection shorter settling time; also provides good amplitude phase balance. digital filter provides extremely linear phase very shape factor.
meet W-CDMA requirements, following elements needed: Nyquist filter Root raised cosine filter: 0.22 Sampling rate: 3.84 Msps 60-MHz bandwidth channel mapping High spurious free dynamic range (SFDR)
Altera provides following functions, which build complete modulator: Compiler create root raised cosine interpolation filter Compiler create LPM_MULT function create digital mixer
Figure shows functional QPSK modulator design. This design fully optimized, however still only uses 2,092 ESBs, which total available EP20K100E total bits.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure QPSK Modulator Schematic (Downlink)
I_in[1.0] clk1_92MHz CLRN Q_in[1.0] clk1_92MHz CLRN I_Q_val yout[18.13] clk15_36MHz clk15_36MHz CLRN CLRN clk100MHz dataa[5.0] result[11.0] datab[5.0] phi_inc_l[23.0] fsin_o[5.0] fcos_o[5.0] reset MULT ADDER dataa[11.0] clk100MHz datab[11.0] MULT result[11.0] result12 x[3.0] clken clk15_36MHz xin[3.0] Filter clken clock Channels yout[18.0] yout[18.0] clk15_36MHz clk1_92MHz result[12.0] MULTIPLEXER data1[1.0] data0[1.0] x[1.0]
x[3.2]
phi_inc_i[23.0] clk100MHz ncoreset
clk100MHz dataa[5.0]
result[11.0] datab[5.0]
novel approach implement multi-carrier modulator based CORDIC algorithm. Figure quad modulator that fulfills spectrum error vector magnitude (EVM) specification W-CDMA been implemented Altera PLDs discussed Multicarrier Modulator, IEEE Transactions Circuits Systems-II: Analog Digital Signal Processing. "References" page Each modulators consist pair root raised cosine filters. These half-band filters connect CORDIC rotator, directly translate baseband signal intermediate frequency (IF). compensate sinx/x roll-off effect digital-to-analog convertors, band-pass filter with inverse sinx/x profile employed.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure CORDIC-Based Modulator
Carrier Frequency Phase Accumulator
Root Raised Cosine Filter 0.22
Halfband Filters
Carrier Frequency Phase Accumulator
Root Raised Cosine Filter 0.22
Halfband Filters
CORDIC Circular Rotator
Root Raised Cosine Filter 0.22
Halfband Filters
CORDIC Circular Rotator
Root Raised Cosine Filter 0.22
Halfband Filters
Carrier Frequency Phase Accumulator
Adder
Inverse Sine Filter
Digital Analog Converter
Root Raised Cosine Filter 0.22
Halfband Filters Carrier Frequency
Phase Accumulator
Root Raised Cosine Filter 0.22
Halfband Filters
CORDIC Circular Rotator
Root Raised Cosine Filter 0.22
Halfband Filters
CORDIC Circular Rotator
Root Raised Cosine Filter 0.22
Halfband Filters
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
W-CDMA Receiver
This section describes digital architecture receiver that supports W-CDMA standard. Figure shows block diagram. Light shaded blocks implemented Altera PLD; dark shaded blocks implemented software embedded processor Excalibur embedded processor PLD.
Figure W-CDMA Receiver Architecture
Embedded Processor Application Multipath Estimator Delay Phases Channel Estimation Symbol Decoding Programmable Logic Application
Decoder Viterbi Decoder Data
Channelizer
Despreading
Multi-User Detector
Multipath Combiner
Deinterleaver
Turbo Decoder
Error Indication
Demodulator
demodulator created using Altera products manner similar QPSK modulator described page
Despreading
radio environment wireless network system multipath environment. effective, system requires despreader that simultaneously despread numerous multipaths both single user well multiple users doing joint detection). RAKE receiver, with multiple fingers despread different multipaths, well suited this function. traditional approach, shown Figure uses coarse delay estimation unit find appropriate values, then triggers delay-locked loops (DLLs) connected finger track multipath. However, this implementation desirable because complex decentralizes process tracking multipaths.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure Traditional DLL-Based Receiver
Coarse Delay Estimator
RAKE Finger with Delays RAKE Finger with Combiner RAKE Finger with RAKE Finger with Combined Narrowband Signal
more desirable implementation full-matched filter that gives value every sample time. full-matched filter eliminates need dedicated DLLs creates centrally controlled RAKE receiver that simpler than distributed with DLLs. High-density Excalibur embedded processor PLDs implement full-matched filter programmable logic, control logic embedded processor.
Channel Estimator Signal Decoder
correct channel distortion, system complex amplitude phase estimation. This action part RAKE receiver, required coherent detection. schemes used estimate complex amplitudes pilot symbol-assisted channel estimation filter, called weighted multi-slot averaging (WMSA) channel estimation filter. this scheme, wideband signal converted narrowband signal using binary correlator. pilot symbols then demultiplexed from data symbols. pilot symbols averaged over multiple slots better average over slot. Figure Excalibur PLDs implement RAKE receiver with correlator portion logic control portion embedded processor.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure Channel Estimator Signal Decoder
Pilot Symbols Wideband Signal Correlator Demultiplexer
Delay Weighted Multi-Slot Averaging
Data Symbols
Narrowband Coherent Signal
effectively implement correlator filter Altera PLD.
Multi-User Detector/Interference Cancellation
capacity DS-CDMA system interference limited. Every user acts interference ever other user. more resistant system interference, more users served. Multi-user detection (MUD) techniques-also called joint detection interference cancellation (IC)- reduce effect multiple access interference increase system capacity. maximum likelihood sequence estimator (MLSE) well-known optimal detection algorithm. However, complex practical DS-CDMA systems. Therefore, most research development efforts focused developing sub-optimal schemes. There classes suboptimal schemes: linear Figure Figure Schemes
Optimal Maximum Likelihood Sequence Estimate Decorrelator, Minimum Mean Square Estimate, Multiple Access Interference Whitening Parallel Interference Cancellation, Successive Interference Cancellation, Decision Feedback
Linear
Multi-User Receivers
Sub-Optimal
Interference Cancellation
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Simulation shown that groupwise successive most promising scheme. this scheme, users grouped according their spreading factor then decorrelator applied within group. Processing starts with lowest group processes towards highest group. illustrate implement PLD, IC-based schemes discussed, wideband narrowband SIC.
Wideband
this scheme, interfering signals cancelled wideband domain. First, RAKE receiver decorrelates number users their multipaths. Next, decorrelated signals grouped based their signal strength spreading factor. appropriate signals regenerated using their corresponding spreading code cancelled from incoming wideband signal. Finally, residual signal from cancellation process added back different signals that tracked before they decorrelated with their respective codes. Figure shows block-level overview. Figure Wideband Block-Level Overview
Sign Select Matrix
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure shows detailed diagram. Figure Wideband Detailed Block Diagram
Detail Representation Residual Signal
1,N-1
Regenator Correlator Code Regenator Correlator Code Regenator Code Correlator Combiner Hard Decision
K,N-1
Regenator Correlator Code Regenator Correlator Code Regenator Correlator Code Combiner Hard Decision
blocks except combiner implemented programmable logic. combiner-with complex algorithm weighted combining low-speed signal processing requirement (3.84 Msps)-can implemented effectively software running Excalibur embedded processor PLDs.
Narrowband
this scheme, interfering signals cancelled narrowband domain. After signals grouped regenerated they would wideband scheme), they decorrelated cross-correlation matrix. cross-correlation matrix contains auto-correlation cross-correlation coefficients between different spreading codes. Cancelling signals removes interference correlation with other spreading codes. Figure
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Figure Narrowband
Sign Calculation Cross Correlator Select Matrix
Evaluating cross-correlation matrix computationally intensive task. matrix must calculated inverted every time user profile changes multipath changes. Therefore, W-CDMA specification uses chips short code (called very long Kasami code). With short spreading code, this implementation more feasible. evaluate cross-correlation matrix, number algorithms that exploit special structure matrix-namely band block Toeplitz structures-can used. approach extend blockToeplitz system matrix into block circulant matrix that inverted with little computational effort using block fast Fourier transform (FFT) function. more information, refer "Efficient Joint Detection Techniques Frequency Domain Third Generation Mobile Radio Systems." "References" page This approach well-suited implementation programmable logic with parallel architecture efficient computation. Additionally, Altera provides processor function, which also suited this application.
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Sequential Correlator
sequential correlator, each incoming sample multiplied sequence that advances chip rate. practical implementation, data values soft symbols where large value indicates more confidence that symbol been received correctly. Results from multiplication stage accumulated over symbol period. period, correlation dumped. Sequential Correlator function from Nova Engineering, Inc., AMPP partner, implement finger RAKE receiver well correlator blocks discussed previously. Figure Sequential Correlator
dump
Sequence Generator
corr_sum[0.m]
clock
Parallel Correlator
parallel correlator, data samples held long shift register, pilot sequence held reference pattern register. Each time sample loaded into data shift register, contents registers multiplied integrated give correlation sum. Figure Parallel Correlator function from Nova Engineering, Inc., AMPP partner, implement multipath delay estimator. Figure Parallel Correlator
clock
Data Shift Register
Reference Pattern Register
dout Correlation Array
corr_sum[0.m]
dref[0.n] ref_en
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Decoders
There types decoders that used receiver. Viterbi decoder used decode signals encoded using convolutional encoders; turbo decoder used with turbo encoder.
Viterbi Decoder
Viterbi algorithm optimal algorithm decode convolutionally encoded data. complexity Viterbi decoding exponential function constraint length. W-CDMA requires decoder with constraint length which poses implementation challenge. Altera provides Viterbi MegaCore function that meets W-CDMA requirements. Figure block diagram. Figure Viterbi Decoder Block Diagram
Add, Compare Select Branch Metrics Computation Traceback Symbol
Path Metric Storage Memory
SysClk RESET
Decoder Control
Valid
There different Viterbi implementations depending throughput requirements. Table Table Viterbi Throughput Implementation
Serial Serial/parallel
1,300 2,600
Speed
Kbps Mbps
Altera Corporation
129: Implementing W-CDMA System with Altera Devices Functions
Turbo Decoder
turbo decoder used decode turbo encoded data. decoder should handle codes different rates block sizes encoded encoder. Altera provides turbo decoder MegaCore function, which following features: Max-logMAP decoder maximum performance Includes UMTS-specific interleaver Fully parameterized tailor decoder system requirements Memory bank swap mechanism increased throughput
Conclusion
Altera Corporation
Figure block diagram. Figure Turbo Decoder Block Diagram
Data Decoder
Output Parity Depuncture Interleaver Deinterleaver
Decoder
Third-generation wireless potential offer exciting services. However, demand unknown related technologies evolving. Also, high throughput platform required support capacity enhancement techniques. These requirements demand flexible solution that also provide necessary performance. Altera portfolio functions, large PLDs with advanced features, Excalibur embedded processor PLDs, offers most complete solution third-generation W-CDMA standard.
129: Implementing W-CDMA System with Altera Functions
References
Andoh, Sawahashi, Adachi. "Channel Estimation Filter Using Time-Multiplexed Pilot Channel Coherent RAKE Combining DS-CDMA Mobile Radio," IEICE Trans. Communications, Vol. E81-B, July 1998. Juntti, "Performance Multi-User Detection Multi-rate CDMA Systems," Wireless Personal Communication, submitted. Marius Vollmew, Jurgen Gotze, Martin Haardt. "Efficient Joint Detection Techniques Frequency Domain Third Generation Mobile Radio Systems," IEEE International Conference Third Generation Wireless Communication, June 2000. Jouko Vankka, Multicarrier Modulator," IEEE Transactions Circuits Systems-II: Analog Digital Signal Processing, Vol. January 2000.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, Excalibur, MegaCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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with Altera Devices Functions Application Note September 200

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