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Implementing a W-CDMA System

with Altera Devices & IP Functions

Implementing a W-CDMA System
with Altera Devices & IP Functions
Application Note 129
September 2000, ver. 1.0
Introduction
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A-AN-129-01
AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
W-CDMA Transmitter
This section describes the digital architecture of a downlink transmitter that supports the W-CDMA standard. Figure 1 shows a block diagram of the transmitter. Light shaded blocks can be implemented in an Altera PLD dark shaded blocks can be implemented in software in the embedded processor of an Excalibur embedded processor PLD.
Figure 1. W-CDMA Transmitter Architecture
Embedded Processor Application Programmable Logic Application OVSF Code Generator FEC Encoder Data CRC Convolutional Encoder
RRC FIlter
Interpolation
Block Interleaver
Baseband Transmit Filter
To conform to the W-CDMA standard, cyclic redundancy code (CRC) bits are added for error detection, and error correction bits are added for channel coding. The data is then spread with a user- or channel-specific code to produce a data stream at a given chip-rate. The spread data stream is scrambled with Gold code so that multipath signals can be uniquely identified and decoded by the receiver. To transmit a signal within the specified bandwidth, the data bits are shaped using a pulse shaping filter. Next, the signal goes through carrier modulation and up-conversion to radio frequency (RF), and is then sent to the antenna to be transmitted over the air. The various functions used in the transmitter are described in the following sections, including: CRC checker Forward error correction (FEC) Block interleaver Orthogonal variable spreading (OVSF) channelization codes Scrambling codes Quadrature phase shift keying (QPSK) modulator
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
CRC Checker
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Altera provides the CRC MegaCore® function, which can implement these polynomials and therefore meets the third-generation standard requirements. The CRC function is fully parameterized, including: Variable length generator polynomial Variable data width from 1 bit to the width of the polynomial Any initial value
Forward Error Correction
The standard defines two encoding schemes to support different quality of services. For voice and MPEG4 applications, the standard employs convolutional encoding, which gives a bit error rate (BER) of up to 10-3. For data applications, the standard uses turbo encoding, which gives a BER of up to 10-6.
Convolutional Encoder
AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Turbo Encoder
Figure 2. Turbo Encoder Block Diagram
Input
Altera provides the turbo encoder MegaCore function, which meets the WCDMA standard. See Figure 2 for a block diagram. The turbo encoder uses 3, 000 logic elements (LEs) and 10 embedded system blocks (ESBs) when implemented in an APEX 20K device.
Encoder 1
Interleaver
Encoder 2
Puncture
Parity
Block Interleaver
Systems that transmit digital data require error correction to reduce the effect of spurious or burst noise from the channel that can corrupt data. A block interleaving function writes data into a rectangular matrix and then reorders the columns of the matrix based on the transmission time interval (TTI) value. APEX device ESBs can store a matrix of elements. To permute the columns, the data is read out column by column in the right sequence. A software routine running in an embedded processor can generate the correct read address.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
OVSF Channelization Codes
2n, 2n
Scrambling Codes
Scrambling codes make the direct sequence CDMA (DS-CDMA) technique more effective in a multipath environment. It significantly reduces the auto-correlation between different time delayed versions of a spreading code so that the different paths can be uniquely decoded by the receiver. Additionally, scrambling codes separate users and basestation sectors from each other by allowing them to manage their own OVSF trees without coordinating amongst themselves. The W-CDMA specification for the scrambling code generator is described below. Downlink: 38, 400 chips of 218 Gold code 512 different scrambling codes Grouped for efficient cell search
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Uplink: Long Code: 38, 400 chips of 225 Gold code Short Code: 256 chips of very large Kasami code
Figure 3. Scrambling Code Generator
Figure 3 shows the downlink scrambling code block diagram.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 4. Scrambling Code Generator Schematic (Downlink)
q10 q17
clk ena
clock enable shiftin
Shift Register load sset data17.0 shiftout q17.0 q217.0
data17.0 q20 q25 q27 q210
clock enable shiftin
q14 q16 q115 q25 q26 q28 q29 q210 q211 q212 q213 q214 q215
QPSK Modulator
Figure 5 shows a modulator that performs baseband filtering and carrier modulation in the digital domain.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 5. Digital I / Q Modulator
BB Filter Symbol Mapper BB Filter Sine Cosine LUT
IF Filter Amp f2 PA
RF Filter
Digital
Using a digital I / Q modulator instead of an analog one has several advantages, including: Channels can be selected in the digital domain using a numerically controlled oscillator (NCO) and a digital mixer. The direct digital synthesizer gives more precise frequency selection and shorter settling time it also provides good amplitude and phase balance. A digital filter provides extremely linear phase and a very low shape factor.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 6. QPSK Modulator Schematic (Downlink)
clk100MHz dataa5.0
result11.0 datab5.0
A novel approach is to implement a multi-carrier QAM modulator based on the CORDIC algorithm. See Figure 7. A quad modulator that fulfills the spectrum and error vector magnitude (EVM) specification of W-CDMA has been implemented in Altera PLDs and is discussed in A Multicarrier QAM Modulator, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing. See "References" on page 20. Each of the modulators consist of a pair of root raised cosine filters. These half-band filters connect to the CORDIC rotator, and directly translate the baseband signal to intermediate frequency (IF). To compensate for the sinx / x roll-off effect of the digital-to-analog convertors, a band-pass filter with inverse sinx / x profile is employed.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 7. CORDIC-Based QAM Modulator
Carrier Frequency 1 Phase Accumulator
3 Halfband Filters
Carrier Frequency 2 Phase Accumulator
3 Halfband Filters
CORDIC Circular Rotator
3 Halfband Filters
CORDIC Circular Rotator
3 Halfband Filters
Carrier Frequency 3 Phase Accumulator
Adder
Inverse Sine Filter
Digital to Analog Converter
3 Halfband Filters Carrier Frequency 4
Phase Accumulator
3 Halfband Filters
CORDIC Circular Rotator
3 Halfband Filters
CORDIC Circular Rotator
3 Halfband Filters
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
W-CDMA Receiver
This section describes the digital architecture of a receiver that supports the W-CDMA standard. Figure 8 shows a block diagram. Light shaded blocks can be implemented in an Altera PLD dark shaded blocks can be implemented in software in the embedded processor of an Excalibur embedded processor PLD.
Figure 8. W-CDMA Receiver Architecture
Embedded Processor Application Multipath Estimator Delay Phases Channel Estimation & Symbol Decoding Programmable Logic Application
FEC Decoder Viterbi Decoder Data
Channelizer
Despreading
Multi-User Detector
Multipath Combiner
Deinterleaver
Turbo Decoder
Error Indication CRC
I / Q Demodulator
The I / Q demodulator can be created using Altera products in a manner similar to the QPSK modulator described on page 7.
Despreading
The radio environment of a wireless network system is a multipath environment. To be effective, the system requires a despreader that can simultaneously despread the numerous multipaths of both a single user as well as multiple users (if doing a joint detection). A RAKE receiver, with its multiple fingers to despread different multipaths, is well suited for this function. A traditional approach, shown in Figure 9, uses a coarse delay estimation unit to find the appropriate tap values, and then triggers delay-locked loops (DLLs) connected to the finger to track the multipath. However, this implementation is not desirable because it is complex and decentralizes the process of tracking the multipaths.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 9. Traditional DLL-Based Receiver
Coarse Delay Estimator
RAKE Finger with DLL Tap Delays RAKE Finger with DLL Combiner RAKE Finger with DLL RAKE Finger with DLL Combined Narrowband Signal
A more desirable implementation is a full-matched filter that gives a new tap value every sample time. A full-matched filter eliminates the need for dedicated DLLs and creates a centrally controlled RAKE receiver that is simpler than a distributed one with DLLs. High-density Excalibur embedded processor PLDs can implement a full-matched filter in programmable logic, and control logic in the embedded processor.
Channel Estimator & Signal Decoder
To correct for channel distortion, the system has complex amplitude and phase estimation. This action is part of the RAKE receiver, and is required for coherent detection. One of the schemes used to estimate complex amplitudes is a pilot symbol-assisted channel estimation filter, called a weighted multi-slot averaging (WMSA) channel estimation filter. In this scheme, the wideband signal is converted to a narrowband signal using a binary correlator. The pilot symbols are then demultiplexed from data symbols. The pilot symbols are averaged over multiple slots to get a better average over the slot. See Figure 10. Excalibur PLDs can implement a RAKE receiver with the correlator portion in logic and the control portion in the embedded processor.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 10. Channel Estimator & Signal Decoder
Pilot Symbols Wideband I / Q Signal Correlator Demultiplexer
Delay Weighted Multi-Slot Averaging
Data Symbols
Narrowband Coherent Signal
You can effectively implement the correlator and filter in an Altera PLD.
Multi-User Detector / Interference Cancellation
The capacity of a DS-CDMA system is interference limited. Every user acts as interference for ever other user. The more resistant the system is to interference, the more users can be served. Multi-user detection (MUD) techniques-also called joint detection and interference cancellation (IC)- reduce the effect of multiple access interference and increase system capacity. The maximum likelihood sequence estimator (MLSE) is a well-known optimal detection algorithm. However, it is too complex for practical DS-CDMA systems. Therefore, most research and development efforts are focused on developing sub-optimal schemes. There are two classes of suboptimal schemes: linear and IC. See Figure 11. Figure 11. MUD Schemes
Optimal Maximum Likelihood Sequence Estimate Decorrelator, Minimum Mean Square Estimate, Multiple Access Interference Whitening Parallel Interference Cancellation, Successive Interference Cancellation, Decision Feedback
Linear
Multi-User Receivers
Sub-Optimal
Interference Cancellation
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Simulation has shown that groupwise successive IC is the most promising scheme. In this scheme, users are grouped according to their spreading factor and then IC or a decorrelator is applied within the group. Processing starts with the lowest SF group and processes towards the highest SF group. To illustrate how to implement MUD in a PLD, two IC-based schemes are discussed, wideband SIC and narrowband SIC.
Wideband SIC
In this scheme, the interfering signals are cancelled in a wideband domain. First, the RAKE receiver decorrelates the number of users and their multipaths. Next, the decorrelated signals are grouped based on their signal strength and spreading factor. The appropriate signals are regenerated using their corresponding spreading code and cancelled from the incoming wideband signal. Finally, the residual signal from the cancellation process is added back to the different signals that are tracked before they are decorrelated with their respective codes. Figure 12 shows a block-level overview. Figure 12. Wideband SIC Block-Level Overview
a1 I&D a2 r a3 Sign I&D a max e j I&D Select Matrix z max
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 13 shows a detailed diagram. Figure 13. Wideband SIC Detailed Block Diagram
Detail Representation Residual Signal
B 1, N-1 (t)
Regenator Correlator Code Regenator Correlator Code Regenator Code Correlator Combiner Hard Decision
B K, N-1 (t)
Regenator Correlator Code Regenator Correlator Code Regenator Correlator Code Combiner Hard Decision B K, N (t)
All of the blocks except the combiner can be implemented in programmable logic. The combiner-with its complex algorithm for weighted combining and low-speed signal processing requirement (3.84 Msps)-can be implemented effectively in software running in an Excalibur embedded processor PLDs.
Narrowband SIC
In this scheme, the interfering signals are cancelled in the narrowband domain. After the signals are grouped and regenerated (as they would be in a wideband SIC scheme), they are decorrelated by a cross-correlation matrix. The cross-correlation matrix contains the auto-correlation and cross-correlation coefficients between the different spreading codes. Cancelling the signals removes the interference due to correlation with other spreading codes. See Figure 14.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Figure 14. Narrowband SIC
a1 I&D a2 r a3 Sign I&D a max e j C 1, N a1 a2 aN Calculation Cross Correlator C 1, 2 I&D Select Matrix z max
Evaluating the cross-correlation matrix is a computationally intensive task. A new matrix must be calculated and inverted every time the user profile changes or multipath tap changes. Therefore, the W-CDMA specification uses a 245 chips short code (called very long Kasami code). With short spreading code, this implementation is more feasible. To evaluate the cross-correlation matrix, a number of algorithms that exploit the special structure of the matrix-namely the band and block Toeplitz structures-can be used. One approach is to extend the blockToeplitz system matrix into a block circulant matrix that can be inverted with little computational effort using a block fast Fourier transform (FFT) function. For more information, refer to "Efficient Joint Detection Techniques in the Frequency Domain for Third Generation Mobile Radio Systems." See "References" on page 20. This approach is well-suited for implementation in programmable logic with a parallel architecture for efficient computation. Additionally, Altera provides the FFT processor function, which is also suited for this application.
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Sequential Correlator
In the sequential correlator, each incoming sample is multiplied by a PN sequence that advances at the chip rate. In a practical implementation, the data values are soft symbols where a large value indicates more confidence that the symbol has been received correctly. Results from multiplication stage are accumulated over the symbol period. At the end of the period, the correlation sum is dumped. You can use the Sequential Correlator function from Nova Engineering, Inc., an AMPP partner, to implement the finger of a RAKE receiver as well as the correlator in MUD blocks discussed previously. Figure 15. Sequential Correlator
dump din
PN Sequence Generator
clock
Parallel Correlator
In the parallel correlator, data samples are held in a long shift register, and the pilot PN sequence is held in a reference pattern register. Each time a new sample is loaded into the data shift register, the contents of the two registers are multiplied and integrated to give a new correlation sum. See Figure 16. You can use the Parallel Correlator function from Nova Engineering, Inc., an AMPP partner, to implement the multipath delay estimator. Figure 16. Parallel Correlator
din clock
Data Shift Register
Reference Pattern Register
dout Correlation Array
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Decoders
There are two types of decoders that can be used in the receiver. The Viterbi decoder is used to decode signals encoded using convolutional encoders the turbo decoder is used with the turbo encoder.
Viterbi Decoder
The Viterbi algorithm is the optimal algorithm to decode convolutionally encoded data. The complexity of Viterbi decoding is an exponential function of the constraint length. W-CDMA requires a decoder with a constraint length of 9, which poses an implementation challenge. Altera provides the Viterbi MegaCore function that meets W-CDMA requirements. See Figure 17 for a block diagram. Figure 17. Viterbi Decoder Block Diagram
Add, Compare Select RR Branch Metrics Computation Traceback Symbol
Path Metric Storage Memory
SysClk RESET
Decoder Control
Valid
There are two different Viterbi implementations depending on the throughput requirements. See Table 1. Table 1. Viterbi Throughput Implementation
Serial Serial / parallel
Speed
500 Kbps 2 Mbps
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AN 129: Implementing a W-CDMA System with Altera Devices & IP Functions
Turbo Decoder
The turbo decoder is used to decode turbo encoded data. The decoder should handle codes of different rates and block sizes encoded by the encoder. Altera provides the turbo decoder MegaCore function, which has the following features: Max-logMAP decoder for maximum performance Includes UMTS-specific interleaver Fully parameterized to tailor decoder to system requirements Memory bank swap mechanism for increased throughput
Conclusion
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See Figure 18 for a block diagram. Figure 18. Turbo Decoder Block Diagram
Data Decoder 1
Output Parity Depuncture Interleaver Deinterleaver
Decoder 2
Third-generation wireless has the potential to offer exciting new services. However, the demand is unknown and related technologies are evolving. Also, a high throughput platform is required to support capacity enhancement techniques. These requirements demand a flexible solution that can also provide necessary performance. The Altera portfolio of IP functions, large PLDs with advanced features, and Excalibur embedded processor PLDs, offers the most complete solution for the third-generation W-CDMA standard.
AN 129: Implementing a W-CDMA System with Altera IP Functions
References
H. Andoh, M. Sawahashi, and F. Adachi. "Channel Estimation Filter Using Time-Multiplexed Pilot Channel for Coherent RAKE Combining in DS-CDMA Mobile Radio, " IEICE Trans. Communications, Vol. E81-B, No. 7, July 1998. Juntti, M., "Performance of Multi-User Detection in Multi-rate CDMA Systems, " Wireless Personal Communication, submitted. Marius Vollmew, Jurgen Gotze, and Martin Haardt. "Efficient Joint Detection Techniques in the Frequency Domain for Third Generation Mobile Radio Systems, " IEEE International Conference in Third Generation Wireless Communication, June 2000. Jouko Vankka, et al. "A Multicarrier QAM Modulator, " IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 1, January 2000.
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