March 2000, ver. Introduction Advances programmable logic de

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Using STAPL Embedded Processor
March 2000, ver.
Introduction
Advances programmable logic devices (PLDs) have enabled innovative in-system programmability (ISP) in-circuit reconfigurability (ICR) features. JamStandard Test Programming Language (STAPL), JEDEC standard JESD-71, compatible with current PLDs that offer Joint Test Action Group (JTAG), providing softwarelevel, vendor-independent standard in-system programming configuration. Designers STAPL implement enhance quality, flexibility, life-cycle their products. Regardless number PLDs that must programmed configured, STAPL simplifies in-field upgrades revolutionizes programming configuration PLDs. This application note describes Altera's programming configuration support using STAPL embedded systems.
Embedded Systems
embedded systems made both hardware software components. When designing embedded system, first step layout printed circuit board (PCB). second step develop firmware that manages board's functionality.
Connecting JTAG Chain Embedded Processor
There ways connect JTAG chain embedded processor. most straightforward method connect embedded processor directly JTAG chain. this method, four processor pins dedicated JTAG interface, thereby saving board space reducing number available embedded processor pins. Figure illustrates second method, which connect JTAG chain existing interface PLD. this method, JTAG chain becomes address existing bus. processor then reads from writes address representing JTAG chain.
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A-AN-122-01
122: Using STAPL Embedded Processor
Figure Embedded System Block Diagram
Embedded System
to/from ByteBlasterMV
Interface Logic (Optional)
Control adr[19.0] Control d[3.0]
d[7.0]
JTAG Device 9000, 9000A, 7000S, 7000A, 7000AE, 3000 Device
TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
Embedded Processor
Control
d[7.0] adr[19.0]
EPROM System Memory
adr[19.0]
FLEX 10K, FLEX 10KA, FLEX10KE, APEX 20K, APEX 20KE Device
JTAG Device
Both JTAG connection methods should include space MasterBlasteror ByteBlasterMVheader connection. header useful during prototyping because allows designers quickly verify modify PLD's contents. During production, header removed save cost.
Example Interface Design
Figure shows example design schematic interface PLD. different design implemented; however, important points exemplified this design are:
TMS, TCK, should synchronous outputs Multiplexer logic should included allow board access MasterBlaster ByteBlasterMV download cable
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122: Using STAPL Embedded Processor
This design example reference only. inputs except data[3.0] optional included only show interface address embedded data bus.
Figure Interface Logic Design Example
data[1.0][2.0] result[2.0]
Byteblaster_nProcessor_Select TDI_Reg
LPM_MUX
ByteBlaster_nProcessor_Select ByteBlaster_TDI DATA3 ByteBlaster_TMS ByteBlaster_TCK ByteBlaster_TDO
ByteBlaster_TDI TDI_Reg ByteBlaster_TMS TMS_Reg TMS_Reg ByteBlaster_TCK TCK_Reg DATA2 data[1][1] data[0][2] data[1][2] data[0][0] data[1][0] data[0][1]
address_decode adr[19.0] adr[19.0] AD_VALID DATA1
TCK_Reg
result0 result1
result2
d[3.0] R_nW R_AS nRESET
DATA0
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122: Using STAPL Embedded Processor
Figure embedded processor asserts JTAG chain's address, R_nW R_AS signals tell interface when processor wants access chain. write involves connecting data path data[3.0] JTAG outputs three registers that clocked system clock (CLK). This clock same clock that processor uses. Likewise, read involves enabling tri-state buffers letting signal flow back processor. design also provides hardware connection read back values TDI, TMS, registers. This optional feature useful during development phase, allowing software check valid states registers interface PLD. addition, multiplexer logic included permit MasterBlaster ByteBlasterMV download cable program device chain. This capability useful during prototype phase development, when programming configuration must verified.
This interface design available MAX+PLUS® Graphic Design File (.gdf) Altera site
Board Layout
following elements important when laying board that programs configures IEEE Std. 1149.1 JTAG chain:
Treat signal trace clock tree pull-down resistor Make JTAG signal traces short possible external resistors pull outputs defined logic level
Signal Trace Protection Integrity
clock entire JTAG chain devices. These devices edge-triggered signal, imperative that protected from high-frequency noise good signal integrity. Ensure that signal meets rise time (tR) fall time (tF) parameters appropriate device family data sheet. signal also need termination prevent overshoot, undershoot, ringing. This step often overlooked since this signal software-generated originates processor general-purpose pin.
Pull-Down Resistors
should held pull-down resistor keep JTAG Test Access Port (TAP) known state power-up. missing pull-down resistor cause device power-up JTAG state, which cause conflicts board. typical resistor value
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122: Using STAPL Embedded Processor
JTAG Signal Traces
Short JTAG signal traces help eliminate noise drive-strength issues. Special attention should paid pins. Because connected every device JTAG chain, these traces will higher loading than TDO. Depending length loading JTAG chain, some additional buffering required ensure that signals propagate from processor with integrity.
External Resistors
should external resistors output pins pull outputs defined logic level during programming configuration. Output pins will tri-state during programming configuration. Also, 7000, FLEX 10K, APEX 20K, configuration devices pins will pulled weak internal resistor (e.g., However, Altera devices have weak pull-up resistors during in-system programming in-circuit reconfiguration. Refer appropriate device family data sheet learn which devices have weak pull-up resistors. Altera recommends that outputs driving sensitive input pins tied appropriate level external resistor, order Each preceding board layout element require further analysis, especially signal integrity. some cases, need analyze loading layout JTAG chain determine whether discrete buffers termination technique.
Software Development
more information, Application Note (In-System Programmability Guidelines). Altera's embedded programming configuration file output from MAX+PLUS software tool standardized Player software. Designing these tools requires minimal developer intervention because files contain data programming configuring Altera devices. bulk development time spent porting Player host embedded processor. more information porting Byte-Code Player, "Porting STAPL Byte-Code Player" page
Files (.jam .jbc)
Altera supports following types files:
ASCII text files (.jam) Byte-Code files (.jbc)
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122: Using STAPL Embedded Processor
ASCII Text Files (.jam)
Altera supports types files:
JEDEC STAPL format version (pre-JEDEC format)
JEDEC STAPL format uses syntax specified JEDEC Standard JESD-71A specification. Altera recommends using JEDEC STAPL files projects. most cases, files used tester environments.
Byte-Code Files (.jbc)
files binary files that compiled versions files. files compiled virtual processor architecture, where ASCII commands mapped byte-code instructions compatible with virtual processor. There types files:
STAPL Byte-Code (compiled version JEDEC STAPL file) Byte-Code (compiled version version file)
Altera recommends using STAPL Byte-Code files embedded applications because they minimal memory.
Generating Files
MAX+PLUS software generate both file types. addition, files compiled into files stand-alone Byte-Code compiler. compiler produces functionally equivalent file.
Byte-Code compiler downloaded from site http://www.jamisp.com. Generating files directly from MAX+PLUS software simple. software tool supports programming configuration multiple devices from single multiple files. Figure shows dialog that specifies which files generated MAX+PLUS software.
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122: Using STAPL Embedded Processor
Figure Generating File Multi-Device JTAG Chain
following steps explain generate files using MAX+PLUS software. generate files APEXdevices, follow same procedure using SRAM Object Files (.sof) generated Quartussoftware. MAX+PLUS Programmer, choose Create File (File menu). Create File dialog box, specify name sequence devices JTAG chain well programming file associated with each device.
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122: Using STAPL Embedded Processor
Specify STAPL Byte-Code File File Format drop-down list box. Click
include both Altera non-Altera JTAG-compliant devices JTAG chain. specify programming file Programming File Names field, devices JTAG chain will bypassed.
Players
Players read descriptive information files translate them into data that programs configures target PLDs. Players program configure particular device architecture vendor; they only read understand syntax defined file specification. In-field changes confined file, Player. result, need modify Player source code each in-field upgrade. There types Players accommodate types files: ASCII STAPL Player STAPL Byte-Code Player. general concepts within this application note apply both player types; however, following information focuses STAPL Byte-Code Player.
Player Compatibility
embedded Player able read files that conform standard JEDEC file format. embedded Player compatible with legacy files that version syntax. Both Players backwardcompatible; they play version files STAPL files.
more information Altera's support version syntax, Application Note (Using Language Embedded Processor).
STAPL Byte-Code Player
STAPL Byte-Code Player coded programming language 16-bit 32-bit processors. Some 8-bit processors also supported specific subset source code available site http://www.jamisp.com.
more information about Altera's support 8-bit processors, Application Note (Embedded Programming Using 8051 ByteCode).
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122: Using STAPL Embedded Processor
16-bit 32-bit source code divided into categories:
Platform-specific code that handles functions applies specific hardware (jbistub.c) Generic code that performs Player's internal functions (all other files)
Figure illustrates organization source code files function. Keeping platform-specific code inside jbistub.c file simplifies process porting STAPL Byte-Code Player particular processor.
Figure STAPL Byte-Code Player Source Code Structure
STAPL Player Functions (jbistub.c file)
Error Message
.jbc Main Program
Parse
Interpret
Compare Export
Porting STAPL Byte-Code Player
default configuration jbistub.c file includes code DOS, 32-bit Windows, UNIX that source code easily compiled evaluated correct functionality debugging these predefined operating systems. embedded environment, this code easily removed using single preprocessor #define statement. addition, porting code involves making minor changes specific parts code jbistub.c file.
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122: Using STAPL Embedded Processor
port Player, need customize several functions jbistub.c file, which shown Table
Table Functions Requiring Customization
Function
jbi_jtag_io() jbi_export() jbi_delay() jbi_vector_map() jbi_vector_io()
Description
Interface four IEEE 1149.1 JTAG signals, TDI, TMS, TCK, Passes information such User Electronic Signature (UES) back calling program Implements programming pulses delays needed during execution Processes signal-to-pin non-IEEE 1149.1 JTAG signals Asserts non-IEEE 1149.1 JTAG signals defined VECTOR
ensure that have customized necessary code, follow these four steps: preprocessor statements exclude extraneous code JTAG signals hardware pins Handle text messages from jbi_export() Customize delay calibration
Step Preprocessor Statements Exclude Extraneous Code jbistub.c, change default PORT parameter EMBEDDED eliminate DOS, Windows, UNIX source code included libraries. #define PORT EMBEDDED Step JTAG signals hardware pins jbi_jtag_io() function contains code that sends receives binary programming data. Each four JTAG signals should re-mapped embedded processor's pins. default, source code writes PC's parallel port. jbi_jtag_io() signal maps JTAG pins parallel port registers shown Figure
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122: Using STAPL Embedded Processor
Figure Default Parallel Port Signal Mapping
Note
Port
OUTPUT DATA Base Address INPUT DATA Base Address
Note:
parallel port hardware inverts most significant bit, TDO.
mapping highlighted following jbi_jtag_io() source code: jbi_jtag_io(int tms, tdi, read_tdo) data=0; tdo=0; (!jtag_hardware_initialized) initialize_jtag_hardware(); jtag_hardware_initialized=TRUE; data ((tdi?0x40:0)|(tms?0x2:0)); /*TDI,TMS*/ write_byteblaster(0,data); (read_tdo) /*TDO*/ write_blaster(0,data|0x01); /*TCK*/ write_blaster(0,data); return (tdo); previous code, parallel port inverts actual value TDO. jbi_jtag_io() source code inverts again retrieve original data. line which inverts value follows:
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122: Using STAPL Embedded Processor
target processor does invert TDO, code should look like: signals correct addresses, left shift (<<) right shift (>>) operators. example, ports respectively, code would follows: Apply same process TDO. read_byteblaster write_byteblaster signals inp() outp() functions from conio.h library, respectively, read write port. these functions available, equivalent functions should substituted. Step Handle Text Messages from jbi_export() jbi_export() function sends text messages stdio, using printf() function. STAPL Byte-Code Player uses jbi_export() signal pass information (e.g., device USERCODE) operating system software that calls Player. function passes text form string) numbers form decimal integer).
definitions these terms, Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices). there device available stdout, information redirected file storage device, passed variable back program that calls Player. Step Customize Delay Calibration calibrate_delay() function determines many loops host processor runs millisecond. This calibration important because accurate delays used programming configuration. default, this number hard-coded 1,000 loops millisecond represented following assignment: one_ms_delay 1000
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122: Using STAPL Embedded Processor
this parameter known, should adjusted accordingly. known, code similar that Windows platforms. Code included these platforms that count number clock cycles that time takes execute single while loop. This code sampled over multiple tests averaged produce accurate result upon which delay based. advantage this approach that calibration vary based speed host processor. Once STAPL Byte-Code Player ported working, verify timing speed JTAG port target device. Timing parameters MAX®, FLEX®, APEX devices should comply with values given Tables
Table IEEE Std. 1149.1 Timing Parameters
Symbol Parameter 9000
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port highimpedance valid output JTAG port valid output high-impedance Capture register setup time Capture register hold time Update register clock output Update register high-impedance valid output Update register valid output high-impedance
7000A
7000AE
7000S
Unit
tJSXZ
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122: Using STAPL Embedded Processor
Table IEEE Std. 1149.1 Timing Parameters
Symbol Parameter 3000A 7000B
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port highimpedance valid output JTAG port valid output high-impedance Capture register setup time Capture register hold time Update register clock output Update register high-impedance valid output Update register valid output high-impedance
APEX
FLEX
EPC2
Unit
tJSXZ
STAPL Byte-Code Player does operate within timing specifications, code should optimized with appropriate delays. Timing violations occur only processor very powerful generate rate faster than MHz. Other than jbistub.c file, Altera strongly recommends keeping source code other files unchanged from their default state. Altering source code these files will result unpredictable Player operation.
STAPL Byte-Code Player Memory Usage
STAPL Byte-Code Player uses memory predictable manner. This section documents estimate both memory usage.
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122: Using STAPL Embedded Processor
Estimating Usage following equation estimate maximum amount required store Player file: Size File Size Player Size file size separated into categories: amount memory required store programming data, space required programming algorithm. following equation estimate file size:
File Size
Data
where: Data Space used algorithm Space used compressed programming data Index representing device being targeted Number target devices chain
This equation provides file size estimate that vary ±10%, depending device utilization. When device utilization low, file sizes tend smaller because compression algorithm used minimize file size more likely find repetitive data. equation also indicates that algorithm size stays constant device family, programming data size grows slightly more devices targeted. given device family, increase file size (due data component) linear.
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122: Using STAPL Embedded Processor
Table shows algorithm file size constants when targeting single device family, Table shows algorithm file size constants possible combinations Altera device families that support language.
Table Algorithm File Size Constants Targeting Single Altera Device Family
Device
APEX APEX 20KE FLEX FLEX 10KE FLEX 10KA FLEX 10KB EPC2 7000AE 7000 3000A 9000 7000S 7000A 7000B
Typical File Algorithm Size (Kbytes)
Table Algorithm File Size Constants Targeting Multiple Altera Device Families
Devices Typical File Algorithm Size (Kbytes)
FLEX 10K, 7000A, 7000S, 7000AE FLEX 10K, 9000, 7000A, 7000S, 7000AE 7000S, 7000A, 7000AE 9000, 7000A, 7000S, 7000AE Note:
When configuring FLEX APEX devices programming devices, FLEX APEX algorithm adds negligible memory.
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122: Using STAPL Embedded Processor
Table shows data size constants Altera devices that support language ISP.
Table Data Constants (Part
Device Typical STAPL Byte-Code Data Size (Kbytes) Compressed
EPM7032S EPM7032AE EPM7064S EPM7064AE EPM7128S, EPM7128A EPM7128AE EPM7128B EPM7160S EPM7192S EPM7256S, EPM7256A EPM7256AE EPM7512AE EPM9320, EPM9320A EPM9400 EPM9480 EPM9560, EPM9560A EPF10K10, EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50, EPF10K50V EPF10K50E EPF10K70 EPF10K100, EPF10K100A, EPF10K100B EPF10K100E EPF10K130E EPF10K130V EPF10K200E EPF10K250A
Uncompressed
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122: Using STAPL Embedded Processor
Table Data Constants (Part
Device Typical STAPL Byte-Code Data Size (Kbytes) Compressed
EP20K100 EP20K200 EP20K400 EPC2 Note:
more information generate files with uncompressed programming data, contact Altera Applications (800) 800-EPLD.
Uncompressed
1,180
After estimating file size, estimate Player size using information Table
Table STAPL Byte-Code Player Binary Sizes
Build
16-bit 32-bit
Description
Pentium/486 using MasterBlaster ByteBlasterMV download cables Pentium/486 using MasterBlaster ByteBlasterMV download cables
Size (Kbytes)
Estimating Dynamic Memory Usage following equation estimate maximum amount DRAM required Player: Size File Size
Data
(Uncompressed Data Size)k
file size determined single- multi-device equation (see "Estimating Usage" page 15). amount used Player will size file plus data required each device that targeted. file generated using compressed data, then some will used Player uncompress data temporarily store uncompressed data sizes provided Tables uncompressed file used, following equation: Size File Size
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memory requirements stack heap negligible, with respect total amount memory used STAPL Byte-Code Player. maximum depth stack JBI_STACK_SIZE parameter jbimain.c file.
Estimating Memory Example following example uses 16-bit Motorola 68000 processor program EPM7128AE EPM7064AE device IEEE Std. 1149.1 JTAG chain file that uses compressed data. determine memory usage, first determine amount required then estimate usage. following steps calculate amount DRAM required Byte-Code Player: Determine file size. following multi-device equation estimate file size. Because files compressed data, compressed data file size information, listed Tables determine Data size. File Size where: Kbytes Data EPM7064AE Data EPM7128AE Data Kbytes Thus, file size equals Kbytes. Estimate Player size. This example uses Player size Kbytes because this 68000 16-bit processor. following equation determine amount needed: Size File Size Player Size Size Kbytes. Estimate usage with following equation: Size Kbytes
Data
Data
(Uncompressed Data Size)k
Because file uses compressed data, uncompressed data size each device must summed find total amount used. Uncompressed Data Size constants follows: EPM7064AE Kbytes EPM7128AE Kbytes
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122: Using STAPL Embedded Processor
Calculate total DRAM usage follows: Size Kbytes Kbytes Kbytes) Kbytes general, Files more than ROM, which desirable because cheaper overhead associated with easy upgrades becomes less factor larger number devices programmed. most applications, easy upgrades outweigh memory costs.
Updating Devices Using
Updating device field means downloading file running STAPL Byte-Code Player with what most cases "program" action. main entry point execution Player jbi_execute(). This routine passes specific information Player. When Player finishes, returns exit code detailed error information runtime errors. interface defined routine's prototype definition. JBI_RETURN_TYPE jbi_execute PROGRAM_PTR program long program_size, char *workspace, long workspace_size, *action, char **init_list, long *error_line, init *exit_code code within main(), jbistub.c, determines variables that will passed jbi_execute(). most cases, this code will applicable embedded environment; therefore, this code removed jbi_execute() routine embedded environment. Table describes each parameter, Table describes each action name.
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122: Using STAPL Embedded Processor
Table Parameters
Parameter
program
Note
Status Description
Mandatory pointer file. most embedded systems, setting this parameter easy assigning address pointer before calling jbi_execute(). Mandatory Amount memory bytes) that file occupies. Optional pointer dynamic memory that used Player perform necessary functions. purpose this parameter restrict Player memory usage pre-defined memory space. This memory should allocated before calling jbi_execute(). maximum dynamic memory usage concern, this parameter null, which allows Player dynamically allocate necessary memory perform specified action. scalar representing amount memory bytes) which workspace points.
program_size workspace
workspace_size Optional action
Mandatory pointer string (text that directs Player). Example actions PROGRAM VERIFY. most cases, this parameter will string PROGRAM. Player case-sensitive, text either upper lower case. Player supports actions defined Standard Test Programming Language Specification. Table Note that string must null terminated. Optional array pointers strings. This parameter used when applying version files. pointer long integer. error encountered during execution, Player will record line file where error occurred. pointer long integer. Returns code there error that applies syntax structure file. this kind error encountered, supporting vendor should contacted with detailed description circumstances which exit code encountered.
init_list error_line exit_code
Notes:
Mandatory parameters must passed Player run. more information, refer Application Note (Using Language Embedded Processor).
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122: Using STAPL Embedded Processor
Table Supported Actions
Action Name
CHECKCHAIN READ_IDCODE READ_USERCODE READ_UES ERASE BLANK_CHECK PROGRAM VERIFY READ CHECKSUM SECURE QUERY_SECURITY TEST
Note
Description
Verify continuity IEEE Std. 1149.1 scan chain Read IEEE 1149.1 IDCODE EXPORT Read IEEE 1149.1 USERCODE EXPORT Read UESCODE EXPORT Perform bulk erase device(s) Check erased state device(s) Program device Verify programming data device(s) Read programming data device(s) Calculate fuse checksum programming data device(s) security device(s) Check whether security Perform test. This test include tests such boundary scan, internal, vector, built-in self tests.
Note:
actions applicable every Altera device. appropriate device family data sheet learn which functions apply.
Player returns status code type JBI_RETURN_TYPE integer. This value indicates whether action successful (returns "0"). jbi_execute() return following exit codes Table defined Standard Test Programming Language Specification.
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122: Using STAPL Embedded Processor
Table Exit Codes
Exit Code
Success Checking chain failure Reading IDCODE failure Reading USERCODE failure Reading UESCODE failure Entering failure Unrecognized device Device version supported Erase failure Blank check failure Programming failure Verify failure Read failure Calculating checksum failure Setting security failure Querying security failure Exiting failure Performing system test failure
Description
Running STAPL Byte-Code Player
Calling STAPL Byte-Code Player like calling other subroutine. this case, sub-routine given actions file name, then performs function. some cases, in-field upgrades performed depending whether current device design up-to-date. JTAG USERCODE often used electronic "stamp" that indicates design revision. USERCODE older value, embedded firmware updates device. following pseudocode illustrates Byte-Code Player could called multiple times update target PLD: result jbi_execute(jbc_file_pointer, jbc_file_size, "READ_USERCODE", error_line, exit_code); STAPL Byte-Code Player will read JTAG USERCODE export using jbi_export() routine. code then branch based upon result. Figure shows example code using Player.
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122: Using STAPL Embedded Processor
Figure Player Code Example
switch (USERCODE) case "0001": /*Rev update Rev*/ result jbi_execute (rev3_file, file_size_3, "PROGRAM", error_line, exit_code); case "0002": /*Rev update Rev*/ result jbi_excecute(rev3_file, file_size_3, "PROGRAM", error_line, exit_code); case "0003": /*Do nothing this current Rev*/ default: /*Issue warning update current Rev*/ Warning unexpected design revision; /*Program device with newest anyway*/ result jbi_execute(rev3_file, file_size_3, "PROGRAM", error_line, exit_code);
switch statement used determine which device needs updated which design revision should used. With STAPL Byte-Code software support, updates become easy adding lines code.
Conclusion
Using STAPL provides simple benefit from ICR. meets necessary embedded system requirements such small file sizes, ease use, platform independence. In-field upgrades simplified confining updates STAPL Byte-Code file. Executing Player straightforward, calculation resources that will used. most recent updates information, visit site http://www.jamisp.com.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, APEX, ByteBlaster, ByteBlasterMV, EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K30E, EPF10K40, EPF10K50, EPF1050E, EPF10K50V, EPF10K70, EPF10K100, EPF10K100A, EPF10K100B, EPF10K100E, EPF10K130E, EPF10K130V, EPF10K200E, EPF10K250A, EPF10K250E, EPM7032S, EPM7064AE, EPM7064S, EPM7128A, EPM7128AE, EPM7128S, EPM7160S, EPM7192S, EPM7256A, EPM7256S, EPM9400, EPM9480, EPM9560, EPM9560A, FLEX 10K, FLEX 10KA, Jam, MasterBlaster, MAX, MAX+PLUS, Quartus, 7000A, 7000AE, 7000S, 9000, 9000A trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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March 2000, ver. Introduction Advances programmable logic de

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