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Using LVDS

in APEX 20KE Devices

Using LVDS
in APEX 20KE Devices
Application Note 120
July 2001, ver. 1.1
Introduction
LVDS Standards
Two key industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS and ANSI / TIA / EIA-644. Although both standards have similar features, the IEEE Std. 1596.3 SCI-LVDS standard supports a maximum data transfer rate of only 250 Mbps. APEX 20KE devices are designed to meet the ANSI / TIA / EIA-644 standard while supporting a maximum data transfer rate of 840 Mbps. The ANSI / TIA / EIA-644 standard defines driver output and receiver input characteristics. Figure 1 shows how the current-mode LVDS driver works.
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Figure 1. LVDS Current-Mode Driver
Current Source (~3.5 mA)
Driver
Receiver
~350 mV 100
LVDS Differential Transmission
The LVDS I / O standard utilizes a low-voltage differential data transmission scheme without requiring an input reference voltage. Differential transmission means that every LVDS signal uses two lines. The voltage difference between the two lines defines the logic state of the LVDS signal. For each signal pair, there is a true signal and a complementary signal. The differential signal is the difference between the true signal and the complementary signal (i.e., LVDSRX01p minus LVDSRX01n). The differential transmission scheme has several key advantages over single-ended schemes:
Increased performance Reduced power consumption Minimized electromagnetic interference (EMI) generation
Increased Performance
Low-voltage swing is important for high performance the smaller the voltage swing, the faster a signal can change logic levels. The faster the transition time (i.e., edge rate), the higher the potential data rate. To provide switching speeds in the hundreds-of-Mbps range, the LVDS standard defines a typical low-voltage signal swing of 350 mV. The two signals are referenced to each other, not to GND or another static signal level. Therefore, a differential standard has a much smaller switching region. For example, the same bandwidth for a low-voltage CMOS (LVCMOS) data bus can be achieved with LVDS using one-fourth as many pins by operating the LVDS signals at eight times the data rate. Figure 2 shows a 128-bit LVCMOS data bus that can be implemented with 16 LVDS channels (32 pins).
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Figure 2. LVCMOS & LVDS Performance
With LVCMOS (256 I / O Pins)
Microprocessor
128-Bit Bus at 105 MHz
APEX 20KE Device
128-Bit Bus at 105 MHz
13-Gbps Switch
Memory
With LVDS (64 I / O Pins, 32 Channels)
Microprocessor
16 LVDS Channels at 840 Mbps
APEX 20KE Device
16 LVDS Channels at 840 Mbps
13-Gbps Switch
Memory
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Power Efficiency
LVDS is a power-efficient standard. Because LVDS has a low switching voltage (typically 350 mV), the AC power dissipation per signal is small. Furthermore, the DC current is typically 3.5 mA per channel. Table 1 shows the equations that calculate the load power dissipation. Table 1. Calculating LVDS Power Dissipation Calculation
DC power per channel (PDC) AC power per channel (PAC) Total power Note:
(1) The voltage level is 3.3 V because the VCCIO of the APEX LVDS driver is driven by a 3.3-V supply.
Equation
Example
To understand how LVDS power consumption compares to LVTTL, consider the following example in which both LVDS and LVCMOS are operating at a 622.08-Mbps bandwidth. The comparison is shown in Table 2. Table 2. LVDS Power Consumption Compared to LVCMOS Power Consumption Parameter
Number of pins / channels Frequency Total bandwidth Data voltage swing Power per pin Total power Note:
1 channel (1) 622.08 622.08 0.35 - 12.77
LVCMOS
8 pins (1) 77.76 622.08 3.3 3.39 27.090
- MHz Mbps V mW mW
Reduced Electromagnetic Interference (EMI)
Using the LVDS standard also provides the important advantage of reduced electromagnetic interference (EMI). EMI is radiated noise created from the acceleration of electric charge within a device and across the transmission medium between devices. Device-generated EMI is dependent on frequency, output voltage swing, and slew rate. Due to the low-voltage swing of the LVDS standard, the EMI effects are much smaller than in CMOS, TTL, or other I / O standards.
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Furthermore, LVDS is less susceptible to common-mode noise because LVDS is a differential standard. Figure 3 shows that system and power supply noise is equally coupled to both LVDS signals, and thus does not affect signal quality. Figure 3. System-Level Noise Rejection
Common-mode noise from power supply & EMI is rejected.
Common-Mode Noise Range
2.4 V +1 V 1.4 V 1.0 V 0.4 V Driver Output -1 V 0.0 V Receiver Input 2.0 V
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Deskew Circuitry
APEX 20KE devices incorporate an optional deskew circuitry, which can be used to ensure successful data capture at high data rates. The deskew circuitry can be used to achieve high performance even with substantial board skew. The deskew circuitry can be used to increase the RSKM parameter as seen in the section "LVDS Timing" on page 9. The deskew circuitry is implemented inside the APEX 20KE device to compensate for board skew on the data channels, as shown in Figure 5. Figure 5. Channel-to-Channel & Clock-to-Channel Skew
Data Stream Skewed from Others Receiver Cannot Capture Data
Channel 1
1 1 0 1 0 0 Clock 8x Channel 3
Channel Skew
To LEs
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Table 3. Calibration Data Pattern for Deskew Circuitry LVDS Operating Mode
Calibration Pattern
At least 3 cycles
DESKEW Input Clock
Input Calibration Data
Byte Boundaries
First bit of valid data (MSB) during user mode
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Changes in temperature and voltage can affect the receiver input skew margin (RSKM). RSKM is the tolerance of the difference between the input clock and the input data. The deskew circuitry needs to be re-calibrated often enough to ensure the skew in the system never exceeds RSKM. An analysis of the circuit must be performed to determine if the RSKM specification is violated.
Data Orientation
Receiver External Input Clock (LVDSRXINCLK) LVDS Data Byte
MSB LSB
Receiver Input Data
Internal Multiplied Clock
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LVDS Timing
Timing Budget
The internally generated PLL clock is positioned to meet the requirements of the timing budget. Figure 8 shows a timing diagram that includes the relationships between the LVDS timing parameters and the bit positions. Figure 8 also shows the waveforms defining the timing specifications for high-speed LVDS operation.
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Figure 8. LVDS Timing Diagram & Timing Budget
Timing Diagram
External Input Clock
Time Unit Interval (TUI)
Internal Clock TCCS RSKM Sampling Window (SW) RSKM TCCS
Receiver Input Data
TPPos (min) tsw (min) Bit n Bit n TPPos (max) Bit n
Internal Clock Falling Edge
tsw (max) Bit n
TPPos (min) Bit n+1
TPPos (max) Bit n+1
Timing Budget
TUI External Clock
Clock Placement Internal Clock Synchronization
Transmitter Output Data
TCCS RSKM
Receiver Input Data
t SW(min)
t SW(max)
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Sampling Window
The sampling window (SW) is the period of time that the input data must be stable to ensure that it can be successfully sampled by the LVDS receiver (Rx). The receiver requires the data to be stable for a period of time before it may be sampled (setup time) and it must be held for a period of time after sampling (hold time). The SW is also defined by the worst-case setup and hold times that take into account the worst-case variation in clock strobe placement.
Channel-to-Channel Skew
The channel-to-channel skew (TCCS) is the difference between the fastest and slowest data output transitions, which includes the clock-to-output (tCO) variation and the clock skew of the transmitter. Skew is the variation in arrival time of two signals that are specified to arrive at the same time. Figure 9 shows a diagram of TCCS. Figure 9. Channel-to-Channel Skew (TCCS)
LVDS Transmitter Interface + -
LVDSTX01p n-1 n n+1
Data127.0
Built in I / O Parallel-to-Serial Converters + LVDSTX16p n-1 n
(8x) PLL 4 (1x) + LVDSTXOUTCLK1
Receiver Input Skew Margin
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LVDS Interconnect
System skew is made up of cable skew, connector skew, and PCB trace skew. A wide variety of cables and connectors for LVDS interconnect are available. Cable skew is determined by cable type, cable length, and cable quality and is normally specified in picoseconds per unit length. The longer the cable the greater the skew. Connector skew is normally much less than cable skew. "Zero skew" connectors consist of a single row of pins that minimize the skew. The PCB traces should be routed with equal length to minimize the skew. For more information on routing LVDS traces, see the Board Design Guidelines for LVDS Systems White Paper. As much as possible, designers should maintain equal distance between traces in an LVDS pair. Routing the pair of traces close together will maximize the common-mode rejection ratio (CMRR).
Design Example
This section describes an LVDS design example using an APEX 20KE-to-APEX 20KE connection and a data transfer rate of 624 Mbps over a 5-m cable. This design uses a 3M Corporation cable (14526-EZ5B) and connector (10226-1A10VE). Figure 10 shows a design example of an APEX 20KE-to-APEX 20KE (specifically for EP20K400E-1X and EP20K600E-1X devices) connection with 3M cable assembly. The timing parameters used in this example are described in Table 6.
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Figure 10. LVDS Design Example
APEX 20KE Device
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Table 4 shows the LVDS timing specifications and terminology. Table 4. LVDS Timing Specifications & Terminology LVDS Timing Specification
tC fLVDSCLK tLHT tHLT TUI
Terminology
fLVDSDR Channel-to-channel skew (TCCS)
Receiver input skew margin (RSKM)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (RMS) tDUTY tLOCK
LVDS Timing Specifications
Tables 5 and 6 show the LVDS timing specifications as described in Figure 8 and Table 4. Table 5. LVDS Multiplication Rate Symbol
w (LVDS mode)
Description
Width of parallel data and PLL multiplication factor
Value
Integer Integer Integer
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Table 6. EP20K400E & EP20K600E LVDS Timing Requirement (Part 1 of 2) Symbol Conditions Commercial -1 Speed Grade Min
Commercial -2 Speed Grade Min
Industrial -2 Speed Grade Min
33 33 20 78.125 87.5 145.25 ns ns ns MHz MHz MHz ps ps ns ns ns Mbps Mbps Mbps ps ps ps ps ps ps ps
4.167 1.429 tC / w 4.762 1.633 tC / w 5 840 735 700 400 400 400 175 190 224 473 1.721 tC / w 240 210 200 w / tC w / tC w / tC
4.167 1.600 tC / w 4.762 1.633 tC / w 5 700 612.5 581 450 450 450 199 301 346 556 1.721 tC / w 240 210 200 w / tC w / tC w / tC
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Table 6. EP20K400E & EP20K600E LVDS Timing Requirement (Part 2 of 2) Symbol Conditions Commercial -1 Speed Grade Min
Commercial -2 Speed Grade Min Typ Max
Industrial -2 Speed Grade Min Typ Max
All All
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Table 7. EP20K1000E & EP20K1500E LVDS Timing Requirement (Part 1 of 2) Symbol Conditions Commercial -1 Speed Grade Min
Commercial -2 Speed Grade Min
Industrial -2 Speed Grade Min
33 33 20 78.125 87.5 145.25 ns ns ns MHz MHz MHz ps ps ns ns ns Mbps Mbps Mbps ps ps ps ps ps ps ps
4.167 1.600 tC / w 4.762 1.633 tC / w 5 750 735 700 400 400 400 177 190 224 510 1.721 tC / w 240 210 200 w / tC w / tC w / tC
4.167 1.600 tC / w 4.762 1.633 tC / w 5 625 612.5 581 450 450 450 285 301 346 685 1.721 tC / w 240 210 200 w / tC w / tC w / tC
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Table 7. EP20K1000E & EP20K1500E LVDS Timing Requirement (Part 2 of 2) Symbol Conditions Commercial -1 Speed Grade Min
Commercial -2 Speed Grade Min
Industrial -2 Speed Grade Min
All All
Receiver & Transmitter Data Valid Windows
For internally generated LVDS PLLs to be properly phase-aligned at the serial-to-parallel converter for data capture, the data sampling window must be properly positioned with respect to the clock. The location of the sampling window and data transmit windows are defined in this section. They are compatible with source-synchronous LVDS buffers offered by National Semiconductor and Texas Instruments. The input timing waveform is shown in Figure 11. To be compatible with National Semiconductor Corporation (NSC) and Texas Instruments, Inc. (TI) source synchronous LVDS devices, there is a 2-bit cycle phase delay from the input clock to the input data.
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Figure 11. Input Timing Waveform
Input Clock (Differential Signal) Previous Cycle Input Data (Single-ended Signal) bit 0 bit 1
Note (1)
Current Cycle bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
Next Cycle
tsw0 (min) MSB tsw0 (max) tsw1 (min) tsw1 (max) tsw2 (min) tsw2 (max) tsw3 (min) tsw3 (max) tsw4 (min) tsw4 (max) tsw5 (min) tsw5 (max) tsw6 (min) tsw6 (max) tsw7 (min) tsw7 (max)
Note:
(1) The timing specifications are referenced at a 100 mV differential voltage.
The output timing waveform in Figure 12 shows the relationship between the output LVDS clock and the serial output data stream.
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Figure 12. Output Timing Waveform
Output Clock (Differential Signal) Previous Cycle Output Data (Single-ended Signal) TPPos0 (min) TPPos0 (max) TPPos1 (min) TPPos1 (max) TPPos2 (min) TPPos2 (max) TPPos3 (min) TPPos3 (max) TPPos4 (min) TPPos4 (max) TPPos5 (min) TPPos5 (max) TPPos6 (min) TPPos6 (max) TPPos7 (min) TPPos7 (max) bit 0 bit 1 bit 2 bit 3 bit 4 Current Cycle bit 5 bit 6 bit 7
Next Cycle
Note:
(1) The timing specifications are referenced at a 250 mV differential voltage.
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There is an Automated LVDS Bit Positions Calculator on the Altera web site (http://www.altera.com), which will calculate the bit positions based on your specific design settings.
tSW0 tSW1 tSW2 tSW3 tSW4 tSW5 tSW6 tSW7
Parameter
Sampling window position for bit 0 Sampling window position for bit 1 Sampling window position for bit 2 Sampling window position for bit 3 Sampling window position for bit 4 Sampling window position for bit 5 Sampling window position for bit 6 Sampling window position for bit 7
Minimum
Typical
Maximum
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7
Parameter
Transmitter output pulse position for bit 0 Transmitter output pulse position for bit 1 Transmitter output pulse position for bit 2 Transmitter output pulse position for bit 3 Transmitter output pulse position for bit 4 Transmitter output pulse position for bit 5 Transmitter output pulse position for bit 6 Transmitter output pulse position for bit 7
Minimum
Typical
Maximum
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tSW0 tSW1 tSW2 tSW3 tSW4 tSW5 tSW6
Parameter
Sampling window position for bit 0 Sampling window position for bit 1 Sampling window position for bit 2 Sampling window position for bit 3 Sampling window position for bit 4 Sampling window position for bit 5 Sampling window position for bit 6
Minimum
Typical
Maximum
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6
Parameter
Transmitter output pulse position for bit 0 Transmitter output pulse position for bit 1 Transmitter output pulse position for bit 2 Transmitter output pulse position for bit 3 Transmitter output pulse position for bit 4 Transmitter output pulse position for bit 5 Transmitter output pulse position for bit 6
Minimum
Typical
Maximum
tSW0 tSW1 tSW2 tSW3
Parameter
Sampling window position for bit 0 Sampling window position for bit 1 Sampling window position for bit 2 Sampling window position for bit 3
Minimum
Typical
Maximum
TPPos0 TPPos1 TPPos2 TPPos3
Parameter
Transmitter output pulse position for bit 0 Transmitter output pulse position for bit 1 Transmitter output pulse position for bit 2 Transmitter output pulse position for bit 3
Minimum
Typical
Maximum
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LVDS Electrical Specifications
Table 14 shows the recommended operating conditions for the LVDS I / O block.
Table 14. 3.3-V LVDS I / O Specifications Symbol
VCCINT VCCIO VOD VOD VOS VOS VTH RL Note:
(1) Devices that do not have the "X" suffix in their ordering codes have a maximum VOD of 550 mV.
Parameter
Supply voltage for internal logic and input buffers Supply voltage Differential output voltage Change in VOD between H and L Output offset voltage Change in VOS between H and L Differential input threshold Receiver differential input resistor
Conditions
Units
Data Conversion Modes
The PLL is the key to successful transmission of the high data rates supported by LVDS. The PLL minimizes skew and phase-aligns the clock at the parallel-to-serial and serial-to-parallel data converters. In EP20K400E and larger devices, two of the ClockLock PLLs can be configured for use in the LVDS I / O interfaces. One LVDS PLL is used for the input block, and another is used for the output block. Figure 13 shows a block diagram of the APEX 20KE LVDS PLLs, including LVDS-specific pin names.
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Figure 13. LVDS PLL Block Diagram
4 Dedicated Clocks G4 G1 LVDSTXOUTCLK1p
LVDSTXINCLK1p G1 G2 G3 CLK4p
clock1 clock0
clock1 clock0 PLL3 inclock
LVDSRXINCLK1p CLK3p
Notes:
(1) (2) These PLL I / O ports are only used in LVDS mode. PLL3 and PLL4 can be used for either LVDS or as a general-purpose PLL.
When using LVDS, the clocks can be multiplied to support high-speed data transfer rates and convert between LVDS and CMOS data. You can multiply the input clock by 4, 7, or 8 for use in the dedicated data conversion circuitry. A general-purpose PLL is recommended for LVDS in bypass mode. Figure 14 shows the connections to the LVDS PLL on the receiver side. Figure 14. LVDS PLL Block Diagram
Allows conversion to 4-, 7-, or 8-bit parallel CMOS Data
LVDS Clock
Dedicated Silicon Serial-to-Parallel Converter
Dedicated Clock
An LVDS PLL is used to boost the LVDS input clock for internally clocking the LVDS data. The PLL also phase-aligns the clock with the incoming data.
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APEX 20KE LVDS Interface
Serial Data 840 Mbps
data7.0 105 Mbps Built-In I / O Serial-to-Parallel Converter
LVDSRXINCLK 105 MHz Clock
Dedicated Clock
Figure 16 shows a block diagram of the LVDS transmitter circuitry. The transmitter PLL (PLL4) can be driven externally or by the output of the receiver PLL (PLL3) via an internal global line, G3, or by dedicated clock pins via G1, G2, or G3. However, the output of the general-purpose PLLs cannot drive the transmitter PLL (PLL4). The output of the transmitter PLL can be driven off-chip to clock other LVDS devices in the system.
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Figure 16. Dedicated LVDS Transmitter Circuitry Block Diagram
APEX 20K LVDS Interface data7.0 105 Mbps Built-In I / O Parallel-to-Serial Converter
Serial Data 840 Mbps
LVDSTXOUTCLK
Internal Global Clocks (G1, G2, G3)
For more information on the ClockLock and ClockBoost circuitry, refer to Application Note 115 (Using the ClockLock & ClockBoost PLL Features in APEX Devices). Figure 17 shows how the LVDS receiver and transmitter internally interface with the logic and the other devices in the system. There are 16 input LVDS channels in the input block, with an LVDS PLL used to clock the serial-to-parallel converter in the receiver. Two PLLs (PLL3 for the receiver and PLL4 for the transmitter) generate phase-locked clock signals for the serial-to-parallel and parallel-to-serial data converters. The receiver has 16 input channels, and the transmitter has 16 output LVDS channels. The LVDS receiver converts a maximum of 16 LVDS signals into 128 parallel data bits, which feeds internal LEs within the device. Similarly, the LVDS transmitter converts a maximum of 128 on-chip data bits into 16 LVDS data streams, using an 8-to-1 parallel-to-serial converter.
LVDS Interface
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Figure 17. LVDS Receiver & Transmitter Interface
Loadable Shift Register Synchronization Registers Loadable Shift Register
LVDSTX01p LVDSTX01n
LVDSRX01p LVDSRX01n
User Logic
LVDSTXOUTCLK1p LVDSRXINCLK1p LVDSRSINCLK1n
LVDSTXINCLK1p LVDSTXINCLK1n
APEX 20KE I / O Structure
APEX 20KE devices have eight programmable I / O banks and two dedicated LVDS I / O blocks. Figure 18 shows a representation of the APEX 20KE I / O banks and LVDS blocks. The LVDS receiver block is located on the right, and the transmitter block is located on the left.
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Figure 18. APEX 20KE I / O Banks
LVDS Transmitter Block (1) I / O Bank 7
Regular I / O Blocks Support I LVTTL I LVCMOS I 2.5-V I 1.8-V I 3.3-V PCI I PCI-X I GTL+ I SSTL-3 Class I and II I SSTL-2 Class I and II I HSTL Class I I CTT I AGP Individual Power Bus
I / O Bank 3 (1) LVDS Receiver Block
Note:
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EP20K200E and smaller devices support using LVDS on dedicated clock signals. For the EP20K300E and smaller devices, the "X" suffix indicates that the device includes PLLs. All APEX 20KE devices, including devices without an "X" suffix in their ordering codes, support LVDS on dedicated clocks. LVDS support is summarized in Table 15. Table 15. LVDS Support in APEX 20KE Devices Device Density
EP20K200E and smaller EP20K300E EP20K400E and larger
Feature
LVDS Clock LVDS I / O pins LVDS Clock LVDS I / O pins LVDS Clock LVDS I / O pins
Devices with PLLs
Devices without PLLs
The LVDS transmitter and receiver blocks support all of the I / O standards and can be used as input, output, or bi-directional pins at 3.3 V, 2.5 V, and 1.8 V. The first two I / O pins that border the LVDS blocks are input only to maintain an acceptable noise level on the internal VCCIO supply. The programmable I / O element (IOE) blocks have individual power planes with separate VCCIO pins for each I / O bank. The VCCIO planes support 3.3-V, 2.5-V, and 1.8-V levels. If the I / O pins are used for LVDS I / O standards, always connect the LVDS power bus-associated VCCIO pins to 3.3 V. When not used for LVDS, the two LVDS I / O blocks support all of the standards supported by APEX 20KE devices.
Board Termination
The LVDS I / O standard requires a termination resistor between the signals at the receiver side. This termination resistor generates the differential output voltage (VOD) at the receiver input. The termination resistor should match the differential load impedance of the bus (typically 100 , but the values may range between 90 and 110 ). Figure 19 shows LVDS board termination at the receiver.
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Figure 19. LVDS Board Termination at the Receiver
Transmitting Device Receiving Device
For multi-drop configurations where one transmitter drives multiple receivers, only one termination resistor is used, and it should be placed at the furthest receiver from the transmitter device, as shown in Figure 20. Figure 20. Multi-Drop Configuration Termination
LVDS Design Guidelines
Because of the high data transmission rates used with LVDS, skew can be a problem. To prevent skew and maintain signal integrity, follow the recommendations below:
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Software
This section provides information on implementing the LVDS I / O standard in the Quartus II software. LVDS can be easily implemented in APEX devices using the Quartus II software and the altlvds megafunction, saving design time and reducing board space.
LVDS Paired Pin Labeling
Function
Receiver positive data pin Receiver negative data pin Transmitter positive data pin Transmitter negative data pin Receiver input clock positive pin Receiver input clock negative pin Transmitter input clock positive pin Transmitter input clock negative pin Transmitter output clock positive pin Transmitter output clock negative pin Dedicated clock 1 positive pin (PLL 1) Dedicated clock 1 negative pin (PLL 1) Dedicated clock 2 positive pin (PLL 2) Dedicated clock 2 negative pin (PLL 2) Dedicated clock 3 positive pin (PLL 3) Dedicated clock 3 negative pin (PLL 3) Dedicated clock 4 positive pin (PLL 4)
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Table 16. LVDS Pin Naming Convention (Part 2 of 2) Pin Names
Function
Dedicated clock 4 negative pin (PLL 4) Dual-purpose ClockLock feedback positive pin (PLL 1) Dual-purpose ClockLock feedback negative pin (PLL 1) Dual-purpose ClockLock feedback positive pin (PLL 2) Dual-purpose ClockLock feedback negative pin (PLL 2) Dual-purpose ClockLock output positive pin (PLL 1) Dual-purpose ClockLock output negative pin (PLL 1) Dual-purpose ClockLock output positive pin (PLL 2) Dual-purpose ClockLock output negative pin (PLL 2)
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Figure 21. LVDS Receiver in the Floorplan Editor
LVDS Bit Positions
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Figure 22. Bit Order for One Channel of LVDS Data
Table 17 shows the conventions for LVDS bit naming. Table 17. LVDS Bit Naming Receiver Data Channel Number
Internal CMOS 8-bit Parallel Data MSB Position
LSB Position
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The altlvds Megafunction
Figures 23 and 24 show the symbols for the altlvds megafunction transmitter and receiver, respectively. Each module represents the dedicated LVDS silicon present in APEX 20KE devices as well as the dedicated LVDS PLLs that are present for clock generation. A single module represents either one or multiple LVDS channels. Figure 23. The altlvds Megafunction Transmitter Module Symbol
Figure 24. The altlvds Megafunction Receiver Module Symbol
Figures 25 through 28 show the AHDL Function Prototype (port name and order also apply to Verilog HDL) and VHDL Component Declaration sample scripts for both the LVDS transmitter and receiver.
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Notes
LVDS reference input clock
No No Yes Yes No No
Optional clock for the input registers Enable control for the LVDS PLL LVDS input data channel LVDS reference input clock Specifies whether to activate calibration mode Enable control for the LVDS PLL
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Table 19. Output Ports of the altlvds Megafunction Port Name Required Description LVDS Transmitter Output Ports
Notes
LVDS Receiver Output Ports
Internal reference clock Gives the status of the LVDS PLL
Table 20. The altlvds Megafunction Parameters (Part 1 of 2) Parameter Type Required Description
LVDS Transmitter Parameters
String
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Table 20. The altlvds Megafunction Parameters (Part 2 of 2) Parameter Type Required Description
LVDS Transmitter Parameters
String
LVDS Receiver Parameters
String
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The MegaWizard Interface
The MegaWizard® interface allows users to customize the LVDS megafunction. The MegaWizard Plug-In Manager automatically generates the following files:
Component Declaration File (.cmp) that can be used in VHDL Design Files (.vhd) Include File (.inc) that can be used in Text Design Files (.tdf) and Verilog HDL Design Files (.v) Quartus II Block Symbol File (.bsf) that can be used in Quartus II Block Design Files (.bdf) Custom Megafunction variation file (TDF, VHD, or V file)
The MegaWizard Plug-In Manager can be invoked in two ways:
Choosing the MegaWizard Plug-In Manager command from the Tools menu, as seen in Figure 29. Selecting MegaWizard Plug-In Manager from the Symbol dialog box in the Block Editor, as seen in Figure 30.
Figure 29. Invoking the MegaWizard Plug-In Manager from the Tools Menu
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Figure 30. Invoking the MegaWizard Plug-In Manager from the Block Editor
The MegaWizard Plug-In Manager takes a step-by-step approach to generating customized LVDS transmitter and receiver modules. Each page of the MegaWizard Plug-In Manager allows the user to select from a set of customizable features that tailors the modules to the needs of the design. Figure 31 displays the third page of the altlvds megafunction in the MegaWizard Plug-In Manager when instantiating an LVDS transmitter. Figure 32 shows the third page for a receiver instantiation. These pages allow the user to customize the LVDS transmitter and receiver modules.
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Figure 31. Page 3 of the altlvds Transmitter MegaWizard Plug-In Manager
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Figure 32. Page 3 of the altlvds Receiver MegaWizard Plug-In Manager
Described below are the various customizable features that are available in the MegaWizard interface:
Number of channels - this option allows the user to select the number of LVDS channels to be used in the design. The desired value can be either typed or selected from the pop-up menu, up to a maximum of 16 channels. This simplifies the complexity of the design in that only one transmitter or receiver module needs to be instantiated to represent multiple LVDS channels. Deserialization factor - this option specifies the number of bits per channel. The user can either type or select 4, 7, or 8 from the pop-up menu. Clock frequency / period - this option specifies the clock frequency or period of the LVDS input clock. LVDS transmitter / receiver - this option specifies the function of the LVDS module. Register inputs / outputs - specifies whether or not to register the inputs for the transmitter and outputs for the receiver. If the signals are not registered in the adjacent MegaLAB structure, then the registered inputs / outputs option must be turned on.
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MegaWizard Examples
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HDL Examples
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Synthesis with Third-Party Tools
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Testbenches
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PORT MAP (
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Quartus II LVDS Reporting
The Quartus II software reports LVDS usage in the compilation report file. The report file documents all information pertaining to LVDS resource usage and placement in the APEX device under the following categories:
All Package Pins Control Signals Global and Other Fast Signals LVDS ClockLock
This section briefly describes each category.
All Package Pins
This category of the report file indicates the function and location of all package pins. LVDS pins are displayed with their names and pin numbers, as seen in the Figure 46 example. Figure 46. All Package Pins Category of the Report File
The Quartus II software adheres to the previously discussed banking rules and will not place non-LVDS outputs in LVDS-enabled banks. In such configurations, the design yields a no-fit, indicating that these nonLVDS outputs are illegally placed. For more information on using I / O standards in the Quartus II software, refer to Application Note 117 (Using I / O Standards in the Quartus Software).
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AN 120: Using LVDS in APEX 20KE Devices
Control Signals
Global and Other Fast Signals
The Global and Other Fast Signals category displays the globally routed signals in the design. When LVDS is used, only the PLL-generated clocks and the synchronization clocks are routed globally as seen in Figure 48. The number of fan-out nodes for the global signal is also displayed. Figure 48. Global and Other Fast Signals Category of the Report File
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AN 120: Using LVDS in APEX 20KE Devices
This category reports LVDS usage in the design, as seen in Figure 49. The instance name is displayed along with its function and deserialization factor. Both PLL output clocks for the LVDS modules are also shown. The LVDS category is omitted when LVDS is not used in the APEX device. Figure 49. LVDS Section of the Report File
ClockLock
The ClockLock category of the report file, as seen in Figure 50, gives the specifications of each PLL that was used. The input frequency is indicated as well as the various resulting clock frequencies after multiplication by the deserialization factor. Figure 50. ClockLock Section of the Report File
Floorplanner
The Floorplanner gives a visual representation of the internal routing and placement of logic within the device. Figure 51 shows the Floorplan view for an LVDS transmitter. The transmitter is divided between two or more colored blocks: the LVDS PLL is located adjacent to the transmitter output clock pins (LVDSTXOUTCLK1p and LVDSTXOUTCLK1n), and the individual parallel-to-serial converters are located adjacent to each pair of LVDS data-out pins (e.g., LVDSTX01p and LVDSTX01n).
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AN 120: Using LVDS in APEX 20KE Devices
Figure 51. Floorplan View of LVDS Transmitter
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Simulation in Quartus II
The Quartus II development tool provides users with the capability to conveniently and efficiently simulate the LVDS design. Vector waveform files (.vwf), which are used as inputs to the native simulation tool, can be created within the Quartus II software. The simulation model for the LVDS receiver is essentially a serialization shift-register that is driven by an LVDS data channel and clocked by an LVDS PLL multiplied by the serialization value. The shift-register drives a bank of data registers clocked by the original clock. The LVDS transmitter module is the inverse of the receiver. A data register is driven by internal parallel data signals and clocked by the original LVDS clock. It then loads a shift-register that drives the LVDS output pin and is clocked by the multiplied output of the LVDS PLL. For more information on simulation in the Quartus II software, see Quartus II Help. Figure 53 shows the results of an example functional simulation of an LVDS transmitter. The 16-channel transmitter is operating at 60 MHz with the synchronization clock activated and a deserialization factor of 8. Figure 53. Example Functional Simulation Waveform of LVDS Transmitter
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Figure 56. Bit Mapping Sample Waveform
Guidelines for Using LVDS Blocks
When an LVDS pin is used as LVDS, non-LVDS output pins cannot be placed in or within two I / O pads of the LVDS receiver and transmitter blocks in the same I / O bank. This only applies for the neighboring I / O bank that shares the same VCCIO bus. Switching outputs on these pins could affect the LVDS pins and degrade performance. The only exception is the PLL LOCK pin, because it rarely changes. As shown in Figure 57, output pins must be at least two pads away from the LVDS receiver and transmitter blocks, unless separated by a power or ground pin. Some LVDS pins may be used as non-LVDS input pins while portion of the block is using LVDS. The Show Pads view in the Floorplan Editor can be used to see the pad order.
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AN 120: Using LVDS in APEX 20KE Devices
Figure 57. I / O Pin Placement in the I / O Bank Adjacent to the LVDS Blocks
Other pads may be inputs or outputs Regular I / O banks
Two pads next to LVDS may be inputs Shared VCCIO bus Pads in LVDS may be non-LVDS inputs
LVDS receiver or transmitter block
LVDS pads
Required Guidelines for LVDS in APEX 20KE Devices
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AN 120: Using LVDS in APEX 20KE Devices
The easiest way to implement dual frequency applications is to use the LVDSRXINCLK to feed the receiver PLL and a dedicated clock pin to feed the transmitter PLL. When designing with LVDS in the transmitter or receiver blocks, the two pads around any LVDS signal cannot be used as an output pin. The Quartus II software will report an error message for violating the two-pad rule next to LVDS pins. These two I / O pads are input only because the LVDS blocks share the same VCCIO supply with the I / O bank that it is located in. Noise from the switching of the non-LVDS output pins would degrade the LVDS performance in the LVDS block.
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AN 120: Using LVDS in APEX 20KE Devices
Packaging
The low inductance and capacitance of 1.27-mm BGA and 1.0-mm FineLine BGA packages makes them ideal for the LVDS feature. The balls used for LVDS signals are located on the outer two rows of balls on the FineLine BGA package. Figure 58 shows the LVDS ball placement on a 672-pin FineLine BGA package for EP20K400E, EP20K600E, and EP20K1000E devices. The marked pins include the 16 LVDS input signals and LVDS clock input on the left side of the package (bottom view). The 16 LVDS output signals, clock signal, and clock output signal are shown on the right side of the package.
Figure 58. Location of LVDS I / O Balls on a 672-Pin FineLine BGA Package
LVDSTXINCLK LVDSTXOUTCLK
LVDS I / O input pairs are placed on the outer two rows of balls to minimize skew.
LVDS Transmitter Data Channels
LVDSRXINCLK
Applications
APEX devices offer different LVDS modes with multiple ways to connect the receiver and transmitter LVDS PLLs. You can interface multiple LVDS devices by using a method that accommodates your design needs. The following LVDS applications are supported with APEX 20KE devices:
Point-to-point configurations Multi-drop LVDS Bypassing the dedicated LVDS converter circuitry
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Point-to-Point Configurations
Point-to-point LVDS applications involve two devices communicating data via LVDS. For point-to-point communication, the receiver PLL can be clocked from either of two sources: the same source as the transmitting devices or the PLL output clock generated by the transmitting devices. Figures 59 and 60 show both cases. For high performance, use the source synchronous clocking scheme shown in Figure 59. Standard I / O timing parameters (setup time and clock-to-output) must be taken into consideration for the application shown in Figure 60. For the source synchronous application, designers should follow the LVDS timing budget defined in "Data Orientation" on page 8. Figure 59. Transmitter PLL Clocks Receiver PLL
Device 1 PLL
External Clock
Device 2 PLL PLL
1 to 16 Channels Internal Logic
Bridges Clock Domain
FIFO Internal Logic
Optionally Clocked at Different Frequency
Clock
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AN 120: Using LVDS in APEX 20KE Devices
Figure 60. Receiver PLLs Clocked by Board Clock
Device 1 PLL PLL Device 2 PLL
1 to 16 Channels Internal Logic
Bridges Clock Domain
FIFO Internal Logic
Optionally Clocked at Different Frequency
Clock
Multi-Drop Configurations
Multi-drop configurations have one transmitter and multiple receivers. The transmitter clock from the source device clocks the LVDS PLLs in the receiving devices. Performance is affected by the number of loads that the transmitter is required to drive. Preliminary information shows that an APEX 20KE device can support up to 16 loads at 400 MHz. Contact Altera Applications for up-to-date information on multi-drop configurations. Figure 61 shows a multi-drop configuration with four loads.
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AN 120: Using LVDS in APEX 20KE Devices
Figure 61. Multi-Drop Configuration
Receivers Transmitter
Clock Data
1 to 16 Channels
Bypassing the Dedicated LVDS Converter Circuitry
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AN 120: Using LVDS in APEX 20KE Devices
Figure 62. Data Feeds LEs Directly
LE, IOE, ESB Registers
General Purpose PLL
Summary
References
Revision History
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