June 2001, ver. Introduction APEXII, APEX 20K, MercuryTM, AC
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Configuring SRAM-Based Devices
June 2001, ver.
Introduction
APEXII, APEX 20K, MercuryTM, ACEX1K, FLEX® 10K, FLEX 6000 devices configured using configuration schemes. configuration schemes either microprocessor configuration device. Table
Table Configuration Schemes Configuration Scheme
Configuration Device
Device Family
APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 APEX APEX 20K, Mercury, ACEX FLEX APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 APEX APEX 20K, Mercury, ACEX FLEX
Typical
Configuration with EPC16, EPC8, EPC2, EPC1, EPC1441 configuration devices.
Passive Serial (PS)
Configuration with serial synchronous microprocessor interface MasterBlastercommunications cable ByteBlasterMVparallel port download cable. (1), Configuration with parallel synchronous microprocessor interface. Configuration with parallel asynchronous microprocessor interface. this scheme, microprocessor treats target device memory. Configuration with serial asynchronous microprocessor interface. Configuration through IEEE Std. 1149.1 (JTAG) pins.
Passive Parallel Synchronous (PPS) Passive Parallel Asynchronous (PPA) Passive Serial Asynchronous (PSA) Joint Test Action Group (JTAG) Notes Table
MasterBlaster communications cable uses standard serial universal serial (USB) hardware interface download configuration data APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices. supports operation with supported QuartusII software MAX+PLUS® software versions higher. more information MasterBlaster cable, MasterBlaster Serial/USB Communications Cable Data Sheet. ByteBlasterdownload cable replaced ByteBlasterMV parallel port download cable. Although cannot configure FLEX 6000 devices through JTAG pins, perform JTAG boundary-scan testing.
Altera Corporation
A-AN-116-2.0
116: Configuring SRAM-Based Devices
This application note discusses configure more APEX APEX (including APEX 20KE APEX 20KC), Mercury, FLEX (including FLEX 10KE FLEX 10KA), FLEX 6000 device. This application note should used conjunction with following documents:
APEX Programmable Logic Device Family Data Sheet APEX Programmable Logic Device Family Data Sheet APEX 20KC Programmable Logic Device Data Sheet Mercury Programmable Logic Device Family Data Sheet ACEX Programmable Logic Device Family Data Sheet FLEX Embedded Programmable Logic Family Data Sheet FLEX 10KE Embedded Programmable Logic Family Data Sheet FLEX 6000 Programmable Logic Device Family Data Sheet Configuration Devices APEX FLEX Devices Data Sheet EPC16 Configuration Device Data Sheet appropriate, illustrations this application note show devices with generic "APEX 20K", "FLEX 10K", "FLEX 6000" labels indicate they valid APEX 20K, FLEX 10K, FLEX 6000 devices.
Contents
This application note provides information following topics: Device Configuration Overview. Configuration Schemes Configuration Device Configuration with Download Cable Configuration with Microprocessor Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) Parallel Configuration with APEX Devices. Configuration (FLEX 6000 Devices Only). Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) JTAG Programming Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) JTAG Programming Configuration Multiple Devices (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) STAPL Programming Test Language Combining Different Configuration Schemes Device Options Device Configuration Pins. Device Configuration Files Programming Configuration Devices APEX 20KE Power Sequencing. Configuration Reliability Board Layout Tips.
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116: Configuring SRAM-Based Devices
Device Configuration Overview
During device operation, APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices store configuration data SRAM cells. Because SRAM memory volatile, SRAM cells must loaded with configuration data each time device powers After APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device configured, registers pins must initialized. After initialization, device enters user mode in-system operation. Figure shows state device during configuration, initialization, user_mode.
Figure APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration Cycle
D(N-1)
nCONFIG nSTATUS CONF_DONE DCLK DATA High-Z User I/Os INIT_DONE MODE Configuration Configuration Initialization User High-Z High-Z
User
Notes Figure
During initial power-up configuration, CONF_DONE low. After configuration, CONF_DONE goes high. device reconfigured, CONF_DONE goes after nCONFIG driven low. User pins tri-stated during configuration. APEX APEX 20K, Mercury, ACEX FLEX 10KE devices have weak pull-up resistor pins during configuration. After initialization, user pins perform function assigned user's design. optional INIT_DONE signal high when nCONFIG before configuration during approximately first clock cycles configuration APEX APEX devices, first cycles Mercury devices, first cycles ACEX FLEX 10K, FLEX 6000 devices. DCLK should left floating after configuration. should driven high low, whichever more convenient. DATA (FLEX 6000 devices) DATA0 (APEX APEX 20K, Mercury, ACEX FLEX 10KE devices) should left floating. They should driven high low, whichever more convenient.
configuration data APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices loaded using active passive configuration scheme. When using active configuration scheme with configuration device, both target device configuration device generate control synchronization signals. When both devices ready begin configuration, configuration device sends data APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device.
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116: Configuring SRAM-Based Devices
When using passive configuration scheme, APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device incorporated into system with intelligent host, such microprocessor, that controls configuration process. host supplies configuration data from storage device (e.g., hard disk, RAM, other system memory). When using passive configuration, change target device's functionality while system operation reconfiguring also perform in-field upgrades distributing programming file system users. Select APEX APEX 20K, Mercury, ACEX FLEX device's configuration scheme driving MSEL0 MSEL1 pins either high shown Table Table APEX APEX 20K, Mercury, ACEX FLEX Configuration Schemes Note MSEL1
Note Table
MSEL1 MSEL0 pins used change configuration modes between configurations. However, they generally connected ground.
MSEL0
Configuration Scheme
Configuration device passive serial. Passive parallel synchronous. Passive parallel asynchronous.
FLEX 6000 devices, MSEL controls configuration, shown Table Table FLEX 6000 Configuration Schemes MSEL
Note Table
MSEL change configuration modes between configurations. However, generally connected ground.
Note
Configuration Scheme
Configuration device passive serial scheme, using MasterBlaster ByteBlasterMV cables. Passive serial asynchronous.
Device option bits device configuration pins discussed further "Device Options" page "Device Configuration Pins" page respectively.
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116: Configuring SRAM-Based Devices
Table summarizes approximate configuration file size required each APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device. calculate amount storage space required multi-device configurations, simply together file size each device. Table APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration File Sizes (Part Note Device
EP2A90 EP2A70 EP2A40 EP2A25 EP2A15 EP20K1500E, EP20K1500C EP20K1000E, EP20K1000C EP20K600E, EP20K600C EP20K400 EP20K400E, EP20K400C EP20K300E EP20K200 EP20K200E, EP20K200C EP20K160E EP20K100 EP20K100E, EP20K100C EP20K60E EP20K30E EP1M350 EP1M120 EP1K100 EP1K50 EP1K30 EP1K10 EPF10K250A EPF10K200E EPF10K130E EPF10K130V EPF10K100E EPF10K100, EPF10K100A, EPF10K100B EPF10K70
Data Size (Bits)
17,389,000 9,612,000 6,275,200 4,714,000 12,011,000 8,938,000 5,654,000 3,878,000 3,901,000 2,733,000 1,950,000 1,964,000 1,523,000 985,000 1,009,000 641,000 347,000 4,383,000 1,297,000 1,337,000 785,000 470,000 178,000 3,292,000 2,740,000 1,840,000 1,582,000 1,336,000 1,200,000 893,000
Data Size (Kbytes)
2,123 1,174 1,467 1,092
Altera Corporation
116: Configuring SRAM-Based Devices
Table APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration File Sizes (Part Note Device
EPF10K50E EPF10K50, EPF10K50V EPF10K40 EPF10K30E EPF10K30A EPF10K30 EPF10K20 EPF10K10A EPF10K10 EPF6024A EPF6016, EPF6016A EPF6010A Notes Table
Binary Files (.rbf) were used determine these file sizes. Contact Altera Applications this information.
Data Size (Bits)
785,000 621,000 498,000 470,000 402,000 376,000 231,000 120,000 118,000 398,000 260,000 260,000
Data Size (Kbytes)
numbers Table should only used estimate file size before design compilation. exact file size vary because different Quartus MAX+PLUS software versions slightly different number padding bits during programming. However, specific version Quartus MAX+PLUS software, design targeted same device same configuration file size. Table lists Altera configuration devices that used configure APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices. Table Configuration Devices Device
EPC16 EPC8 EPC2 EPC1 EPC1441
Description
16,000,000 1-bit device with 3.3-V operation 8,000,000 1-bit device with 3.3-V operation 1,695,680 1-bit device with 5.0-V 3.3-V operation 1,046,496 1-bit device with 5.0-V 3.3-V operation 440,800 1-bit device with 5.0-V 3.3-V operation
Altera Corporation
116: Configuring SRAM-Based Devices
data from Tables determine number configuration devices required configure your device. example, configure EPF10K100 device, need EPC1 devices, only EPC2 device. Similarly, EP20K400 device requires three EPC2 devices, only EPC8 device.
Configuration Schemes
This section describes configure APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices with following configuration schemes:
Configuration Device Configuration with Download Cable Configuration with Microprocessor Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) Configuration (FLEX 6000 Devices Only) Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) JTAG Programming Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only) JTAG Programming Configuration Multiple Devices (APEX APEX 20K, Mercury, ACEX FLEX Devices Only)
Configuration Device
configuration device scheme uses Altera-supplied serial configuration device supply data APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device serial bitstream. Figure
Altera Corporation
116: Configuring SRAM-Based Devices
Figure Configuration Device Scheme Circuit
APEX ACEX Mercury, APEX 20KC, APEX FLEX Devices
APEX ACEX Mercury, APEX 20KC, APEX FLEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO N.C.
Configuration Device
DCLK DATA nINIT_CONF (3),
APEX 20KE Devices
VCCINT(6)
APEX 20KE Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO N.C.
Configuration Device
DCLK DATA nINIT_CONF (3),
FLEX 6000 Devices
FLEX 6000 Device
DCLK DATA nSTATUS CONF_DONE nCONFIG nCEO
Configuration Device
DCLK DATA
N.C.
MSEL
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116: Configuring SRAM-Based Devices Notes Figure
pull-up resistor should connected same supply voltage configuration device. pull-up resistors APEX 20KE APEX 20KC devices). EPC16, EPC8, EPC2 devices' pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. nINIT_CONF available EPC2, EPC8, EPC16 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC2 devices. external pull-up resistor required nINIT_CONF pin. nCEO left unconnected. ensure successful configuration between APEX 20KE configuration devices possible power-up sequences, pull nCONFIG VCCINT. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC2 devices. nCONFIG must connected VCCINT through 10-k resistor. isolate 1.8-V 3.3-V power supplies when configuring APEX 20KE devices, diode between APEX 20KE device's nCONFIG configuration device's nINIT_CONF pin. Select diode with threshold voltage (VT) less than equal diode will make nINIT_CONF opendrain pin; will only able drive tri-state. EPC16, EPC8, EPC2 devices should used configure FLEX 6000 devices.
configuration device scheme, nCONFIG usually tied (when using EPC16, EPC8, EPC2 devices, nCONFIG connected nINIT_CONF). Upon device power-up, target APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device senses low-tohigh transition nCONFIG initiates configuration. target device then drives open-drain CONF_DONE low, which in-turn drives configuration device's low. When exiting POR, both target configuration device release open-drain nSTATUS pin. Before configuration begins, configuration device goes through delay (maximum) allow power supply stabilize; during this time, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When both devices complete POR, they release nSTATUS, which then pulled high pull-up resistor. When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. When devices ready, configuration device clocks data serially target devices using internal oscillator.
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116: Configuring SRAM-Based Devices
After successful configuration, configuration device starts clocking target device initialization. CONF_DONE released target device then pulled high pull-up resistor. When initialization complete, configuration device enters user mode. error occurs during configuration, target device drives nSTATUS low, resetting itself internally resetting configuration device. Auto-Restart Configuration Frame Error option-available MAX+PLUS Global Project Device Options dialog (Assign menu)-is turned device reconfigures automatically error occurs. Quartus software provides similar option using Device Option dialog box. choose this option, select Compiler Settings (Processing menu), then click Chips Devices tab. this option turned off, external system must monitor nSTATUS errors then pulse nCONFIG restart configuration. external system pulse nCONFIG nCONFIG under system control rather than tied VCC. When configuration complete, target device releases CONF_DONE, which disables configuration device driving high. configuration device drives DCLK before after configuration. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that target device configured successfully. this case, configuration device pulses microseconds, driving target device's nSTATUS low. Auto-Restart Configuration Frame Error option software, target device resets then pulses nSTATUS low. When nSTATUS returns high, configuration device reconfigures target device. When configuration complete, configuration device drives DCLK low. When CONF_DONE driven after device configuration, configuration device recognizes that target device configured successfully; therefore, your system should pull CONF_DONE delay initialization. Instead, should Quartus MAX+PLUS software's User-Supplied Start-Up Clock option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain will initialize together. more information this option, "Device Options" page Figure shows configure multiple devices with configuration device. This circuit similar configuration device circuit single programmable logic device (PLD), except APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices cascaded multi-device configuration.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration Circuit
APEX ACEX Mercury, APEX 20KC, APEX FLEX Devices
Note
APEX ACEX Mercury, APEX 20KC,APEX FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO
APEX FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF (6),
Configuration Device
DCLK DATA nINIT_CONF (6),
N.C.
nCEO
VCCINT
APEX 20KE Devices
APEX 20KE Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO
APEX 20KE Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF (6),
Configuration Device
DCLK DATA nINIT_CONF (6),
N.C.
nCEO
FLEX 6000 Devices
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG
Configuration Device (10)
DCLK DATA
Configuration Device (10)
DCLK DATA
nCASC
N.C.
nCEO
nCEO
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116: Configuring SRAM-Based Devices Notes Figure
When performing multi-device active serial configuration, must generate configuration device's Programmer Object File (.pof) from each project's SRAM Object File (.sof). combine multiple SOFs using MAX+PLUS software's Combine Programming Files dialog (File menu). APEX devices, Quartus software provides similar option Device Option dialog box. choose this option, select Compiler Settings (Processing menu), then click Chips Devices tab. more information create configuration programming files, "Device Configuration Files" page pull-up resistor should connected same supply voltage configuration device. pull-up resistors APEX 20KE APEX 20KC devices). EPC16, EPC8, EPC2 devices' pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. EPC16 EPC8 configuration devices cannot cascaded. nCEO left unconnected last device chain. nINIT_CONF available EPC16, EPC8, EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled through resistor. EPC16, EPC8, EPC2 devices should used configure FLEX 6000 devices. ensure successful configuration between APEX 20KE configuration devices possible power-up sequences, pull nCONFIG VCCINT through 10-k resistor. isolate 1.8-V 3.3-V power supplies when configuring APEX 20KE devices, diode between APEX 20KE device's nCONFIG configuration device's nINIT_CONF pin. Select diode with threshold voltage (VT) less than equal diode will make nINIT_CONF open-drain pin; will only able drive tri-state. (10) nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin.
After first device completes configuration during multi-device configuration, nCEO activates second device's pin, prompting second device begin configuration. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. addition, nSTATUS pins tied together; thus, device (including configuration devices) detects error, configuration stops entire chain. Also, first configuration device does detect CONF_DONE going high configuration, resets chain pulsing microseconds. This pulse drives second configuration device drives nSTATUS APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices, causing them enter error state. This state similar APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device detecting error. Auto-Restart Configuration Frame Error option software, APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices release their nSTATUS pins after reset time-out period. When nSTATUS pins released pulled high, configuration devices reconfigure chain. Auto-Restart Configuration Frame Error option set, APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices drive nSTATUS until they reset with pulse nCONFIG.
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116: Configuring SRAM-Based Devices
also cascade several configuration devices configure multiple APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices. When data from first configuration device sent, drives nCASC low, which turn drives subsequent configuration device. Because configuration device requires less than clock cycle activate subsequent configuration device, data stream uninterrupted. EPC16 EPC8 configuration devices cannot cascaded. Figure shows timing waveform configuration device scheme. Figure Configuration Device Scheme Timing Waveform
nINIT_CONF VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE
Note
tPOR
tDSU
DCLK DATA User INIT_DONE
tOEZX
User Mode
Tri-State
Tri-State
Notes Figure
timing information, refer Configuration Devices APEX FLEX Devices Data Sheet EPC16 Configuration Device Data Sheet. configuration device will drive DATA after configuration. APEX APEX devices enter user mode clock cycles after CONF_DONE goes high. Mercury devices enter user mode clock cycles after CONF_DONE goes high. ACEX FLEX 10K, FLEX 6000 devices enter user mode clock cycles after CONF_DONE goes high.
single configuration chain configure multiple APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices. this scheme, nCEO first device connected second device chain. configure properly, device CONF_DONE nSTATUS pins must tied together. Figure shows examples configuring multiple APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices using configuration device.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration with APEX 20K, FLEX FLEX 6000 Devices
Note
Configuring APEX FLEX 6000 Devices
FLEX Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG N.C. nCEO
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF (5),
Configuration Device
DCLK DATA nINIT_CONF (5),
nCEO
Configuring FLEX FLEX 6000 Devices
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG N.C. nCEO
FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA
Configuration Device
DCLK DATA
nCASC
nCEO
Notes Figure
timing information, refer Configuration Devices APEX FLEX Devices Data Sheet EPC16 Configuration Device Data Sheet. should connected same supply voltage configuration device, except APEX 20KE APEX 20KC devices. APEX 20KE APEX 20KC devices, 10-k resistor pull nCONFIG VCCINT. pull-up resistors APEX 20KE APEX 20KC devices). EPC2 device's pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. nCEO left unconnected last device chain. nINIT_CONF available EPC16, EPC8, EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor. nINIT_CONF internal pull-up resistor which always active EPC16, EPC8, EPC2 devices. EPC16, EPC8, EPC2 devices configure FLEX 6000 devices. EPC16 EPC8 configuration devices cannot cascaded.
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116: Configuring SRAM-Based Devices
timing information, refer Configuration Devices APEX FLEX Devices Data Sheet EPC16 Configuration Device Data Sheet. Table shows status device DATA pins during after configuration. APEX APEX 20K, Mercury, ACEX FLEX devices have DATA[7.0] bus, while FLEX 6000 devices have DATA only. Table DATA Status During After Configuration Pins APEX APEX 20K, Mercury, ACEX FLEX Device During
DATA DATA0 Used configuration
FLEX 6000 Device During
Used configuration
After
Tri-state User defined
After
Tri-state
DATA[7.1] Used some configuration modes pins Notes Table
Tri-state
User defined
Tri-state
User defined
status shown configuration with configuration device. function these pins depends upon settings specified MAX+PLUS software's Global Project Device Options dialog box. APEX devices, Quartus software provides similar option using Device Option dialog box. choose this option, select Compiler Settings (Processing Menu), then click Chips Devices tab. more information, refer MAX+PLUS Quartus Help.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration with Download Cable
configuration with download cable, intelligent host transfers data from storage device APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device MasterBlaster ByteBlasterMV cable. initiate configuration this scheme, download cable generates low-to-high transition nCONFIG pin. programming hardware then places configuration data time device's DATA (the DATA0 APEX APEX 20K, Mercury, ACEX FLEX devices, DATA FLEX 6000 devices). data clocked into target device until CONF_DONE goes high.
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116: Configuring SRAM-Based Devices
When using programming hardware APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000, setting Auto-Restart Configuration Frame Error option does affect configuration cycle because Quartus MAX+PLUS software must restart configuration when error occurs. Figure shows configuration APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices using MasterBlaster ByteBlasterMV cable.
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116: Configuring SRAM-Based Devices
Figure Configuration Circuit with MasterBlaster ByteBlasterMV Cable
APEX APEX 20K, Mercury Device
MSEL0 MSEL1 CONF_DONE nSTATUS
MasterBlaster ByteBlasterMV 10-Pin Male Header
DCLK DATA0 nCONFIG
ACEX FLEX Device
MSEL0 MSEL1 CONF_DONE nSTATUS
Shield
MasterBlaster ByteBlasterMV 10-Pin Male Header
DCLK DATA0 nCONFIG
Shield
FLEX 6000 Device
MSEL CONF_DONE nSTATUS
DCLK DATA nCONFIG
MasterBlaster ByteBlasterMV 10-Pin Male Header
Shield
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116: Configuring SRAM-Based Devices Notes Figure
pull-up resistor should connected same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable, except APEX 20KE APEX 20KC devices. APEX 20KE APEX 20KC devices, 10-k resistor pull nCONFIG VCCINT. pull-up resistor should APEX 20KE APEX 20KC devices. nCEO left unconnected last device chain. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. header reference voltage MasterBlaster output driver. should match device's VCCIO. This connect ByteBlasterMV header.
programming hardware configure multiple APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices connecting each device's nCEO subsequent device's pin. other configuration pins connected each device chain. Because CONF_DONE pins tied together, devices chain initialize enter user mode same time. addition, because nSTATUS pins tied together, entire chain halts configuration device detects error. this situation, Quartus MAX+PLUS software must restart configuration; AutoRestart Configuration Frame Error option does affect configuration cycle. Figure shows configure multiple ACEX FLEX 10K, FLEX 6000 devices with MasterBlaster ByteBlasterMV download cable.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration ACEX FLEX FLEX 6000 Devices with Cable
ACEX FLEX Device
MasterBlaster ByteBlasterMV 10-Pin Male Header (Passive Serial Mode)
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
DATA0 nCONFIG
FLEX 6000 Device
MSEL
CONF_DONE nSTATUS DCLK nCEO N.C.(4)
DATA nCONFIG
Notes Figure
pull-up resistor should connected same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain.
Figure shows configure multiple ACEX FLEX devices with MasterBlaster ByteBlasterMV download cable.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration Multiple ACEX FLEX Devices with Cable
ACEX FLEX Device
MSEL0
MasterBlaster ByteBlasterMV 10-Pin Male Header (Passive Serial Mode)
MSEL1
CONF_DONE nSTATUS DCLK
DATA0 nCONFIG
nCEO
ACEX FLEX Device
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
N.C.
DATA0 nCONFIG
Notes Figure
pull-up resistor should connected same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain.
Figure shows configure multiple APEX APEX 20K, Mercury, ACEX FLEX devices with MasterBlaster ByteBlasterMV cable.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration APEX APEX 20K, Mercury, ACEX FLEX Devices with Cable
APEX APEX 20K, ACEX Mercury Device
MSEL0
MasterBlaster ByteBlasterMV 10-Pin Male Header (Passive Serial Mode)
MSEL1
CONF_DONE nSTATUS DCLK
nCEO
DATA0 nCONFIG
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
N.C.
DATA0 nCONFIG
APEX APEX 20K, ACEX Mercury, FLEX Device
Notes Figure
pull-up resistor should connected same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable, except APEX 20KE APEX 20KC devices. APEX 20KE APEX 20KC devices, 10-k resistor pull nCONFIG VCCINT. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain. resistor value should APEX 20KE APEX 20KC devices. there combination APEX 20KE APEX 20KC devices with other devices, 10-k pull-up resistors nSTATUS CONF_DONE pins.
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116: Configuring SRAM-Based Devices
using MasterBlaster ByteBlasterMV cable configure device(s) board that also configuration devices, should electrically isolate configuration device from target device(s) cable. isolate configuration device logic, such multiplexer, that select between configuration device cable. multiplexer chip should allow bidirectional transfers nSTATUS CONF_DONE signals. Another option switches five common signals (i.e., CONF_DONE, nSTATUS, DCLK, nCONFIG, DATA0) between cable configuration device. last option remove configuration device from board when configuring with cable. Figure shows combination configuration device MasterBlaster ByteBlasterMV cable configure PLD. Figure Configuring with Combined Configuration Device Scheme
DATA0 nCONFIG nCEO N.C.
APEX APEX 20K, ACEX Mercury, FLEX Device
MSEL0 MSEL1 CONF_DONE nSTATUS DCLK
MasterBlaster ByteBlasterMV 10-Pin Male Header (Passive Serial Mode)
Configuration Device
DCLK DATA nINIT_CONF
Notes Figure
pull-up resistor should connected same supply voltage configuration device except APEX 20KE APEX 20KC devices where nCONFIG should pulled VCCINT 10-k pull-up resistor. resistor value should APEX 20KE APEX 20KC devices. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. header reference voltage MasterBlaster output driver. should match target device's VCCIO. This connect ByteBlasterMV header. nCEO left unconnected. should attempt configuration with MasterBlaster ByteBlasterMV cable while configuration device connected APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device. Instead, should either remove configuration device from socket when using download cable place switch five common signals between download cable configuration device. nINIT_CONF available EPC16, EPC8, EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor. diode between APEX 20KE device's nCONFIG configuration device's nINIT_CONF isolate 1.8-V 3.3-V power supplies. Select diode with threshold voltage (VT) less than equal diode will make nINIT_CONF open-drain pin. These pins will only break drive tri-state.
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116: Configuring SRAM-Based Devices
more information MasterBlaster ByteBlasterMV cables, following documents:
MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration with Microprocessor
configuration with microprocessor, microprocessor transfers data from storage device target APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device. initiate configuration this scheme, microprocessor must generate low-to-high transition nCONFIG target device must release nSTATUS. microprocessor programming hardware then places configuration data time DATA target device (the DATA0 APEX APEX 20K, Mercury, ACEX FLEX devices, DATA FLEX 6000 devices). least significant (LSB) each data byte must presented first. Data clocked continuously into target device until CONF_DONE goes high. After data transferred, DCLK must clocked additional times ACEX FLEX 10K, FLEX 6000 devices, additional times APEX APEX devices, additional times Mercury devices initialize device. device's CONF_DONE goes high show successful configuration start initialization. configuration files created Quartus MAX+PLUS software incorporate extra bits initialization. Driving DCLK device after configuration does affect device operation. Therefore, sending entire configuration file device sufficient configure initialize Handshaking signals used configuration modes. Therefore, configuration clock speed must below specified frequency ensure correct configuration. maximum DCLK period exists. pause configuration halting DCLK indefinite amount time. target device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option Quartus MAX+PLUS software, target device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target device without needing pulse nCONFIG low.
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116: Configuring SRAM-Based Devices
microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sends data initialization clock starts CONF_DONE INIT_DONE have gone high, must reconfigure target device. Figure shows circuit configuration with microprocessor.
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116: Configuring SRAM-Based Devices
Figure Configuration Circuit with Microprocessor
APEX APEX 20K, ACEX Mercury, FLEX Devices
Memory
ADDR DATA0
APEX APEX ACEX Mercury, FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0 N.C.
Microprocessor
DATA0 nCONFIG DCLK
FLEX 6000 Devices
Memory
ADDR DATA
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DATA nCONFIG DCLK
Notes Figure
pull-up resistor should APEX 20KE APEX 20KC devices. nCEO left unconnected single device configuration.
multi-device configuration with microprocessor, first device's nCEO cascaded second device's pin. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. Because device CONF_DONE pins tied together, devices initialize enter user mode same time.
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116: Configuring SRAM-Based Devices
addition, nSTATUS pins tied together. Thus, device detects error, entire chain halts configuration drives nSTATUS low. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option Quartus MAX+PLUS software, target devices release nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target devices. Figure shows multi-device configuration with microprocessor.
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration with Microprocessor
APEX APEX 20K, ACEX Mercury, FLEX Devices
Memory
ADDR DATA0
APEX APEX 20K, ACEX Mercury, FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX APEX 20K, ACEX Mercury, FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO N.C. MSEL0
Microprocessor
DATA0 nCONFIG DCLK DATA0 nCONFIG DCLK
FLEX 6000 Devices
Memory
ADDR DATA
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DATA nCONFIG DCLK DATA nCONFIG DCLK
Notes Figure
pull-up resistor should connected supply that provides acceptable input signal devices chain. example, when device chain contains mixture 5.0-V FLEX devices 2.5-V FLEX 10KE devices, pull-up resistor should connected should this scenario because FLEX 10KE pins 5.0-V tolerant. nCEO left unconnected last device chain. pull resistor should APEX 20KE APEX 20KC devices. there combination APEX 20KE APEX 20KC devices along with other devices, 10-k pull-up resistor nSTATUS CONF_DONE pins.
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116: Configuring SRAM-Based Devices
Figure shows configuration timing waveform APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices. Figure Timing Waveform APEX 20K, FLEX FLEX 6000 Devices
tCF2ST1 tCFG
nCONFIG
tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD ST2CK
CONF_DONE
DCLK
DATA
tDSU
User INIT_DONE High-Z User Mode
tCD2UM
Notes Figure
Upon power-up, APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device holds nSTATUS more than after reaches minimum requirement. Upon power-up before configuration, CONF_DONE low. DATA should left floating after configuration. should driven high low, whichever more convenient.
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116: Configuring SRAM-Based Devices
Tables contain timing information APEX APEX devices. Table Timing Parameters APEX Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
33.3
Table Timing Parameters APEX APEX 20KE APEX 20KC Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Note
8.75 8.75 17.5
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
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116: Configuring SRAM-Based Devices
Tables contain timing information Mercury ACEX devices. Table Timing Parameters Mercury Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Note
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
Table Timing Parameters ACEX Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
33.3
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116: Configuring SRAM-Based Devices
Tables contain timing information FLEX 10KE, FLEX 10K, FLEX 6000 devices. Table Timing Parameters FLEX 10KE Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
33.3
Table Timing Parameters FLEX FLEX 6000 Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
16.7
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116: Configuring SRAM-Based Devices Notes Tables
configuration stopped reinitiated before CONF_DONE goes high, this value applies when internal oscillator selected clock source. configuration stopped reinitiated before CONF_DONE goes high clock source CLKUSR DCLK, multiply clock period APEX APEX devices, Mercury devices, FLEX FLEX 6000 devices determine this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period APEX APEX devices, Mercury devices, ACEX FLEX 10K, FLEX 6000 devices obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width. APEX APEX 20KC, Mercury device timing parameters preliminary.
Figure shows example multi-device configuration circuit with APEX APEX 20K, ACEX Mercury, FLEX 10K, FLEX 6000 devices using microprocessor. Figure Multi-Device Configuration APEX APEX 20K, ACEX Mercury, FLEX FLEX 6000 Devices with Microprocessor
Memory
ADDR DATA0
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO
APEX APEX ACEX Mercury, FLEX Device
MSEL1 MSEL0 CONF_DONE nSTATUS DATA0 nCEO N.C.
Microprocessor
DATA nCONFIG DCLK
nCONFIG DCLK
Notes Figure
pull-up resistor should connected supply that provides acceptable input signal devices chain. example, when device chain contains mixture 5.0-V FLEX devices 2.5-V FLEX 10KE devices, pull-up resistor should connected should this scenario because FLEX 10KE pins 5.0-V tolerant. pull-up resistor should APEX 20KE APEX 20KC devices. there combination APEX 20KE APEX 20KC devices with other devices, 10-k pull-up resistor nSTATUS CONF_DONE pins. nCEO left unconnected last device chain.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
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116: Configuring SRAM-Based Devices
Configuration (APEX 20K, Mercury, ACEX FLEX Devices Only)
passive parallel synchronous (PPS) configuration scheme, intelligent host drives target APEX 20K, Mercury, ACEX FLEX device. host system outputs parallel data serializing clock device. target device latches byte-wide data DATA[7.0] pins, serializes internally. DCLK, CONF_DONE, nCONFIG, nSTATUS, DATA[7.0] pins connected port intelligent host, such microprocessor. begin configuration, nCONFIG given low-to-high transition host places 8-bit configuration word target device's data inputs. host clocks target device; data should presented host latched target device every eight clock cycles. first rising clock edge, byte configuration data latched into target device; subsequent eight falling clock edges serialize data device. ninth rising clock edge, next byte configuration data latched serialized into target device. pause configuration halting DCLK. DCLK halted indefinite amount time. status (RDYnBSY) target device indicates when serializing data when ready accept next data byte. error occurs during configuration, nSTATUS drives low. host senses this signal begins reconfiguration issues error. Once target device configures successfully, releases CONF_DONE pin. When CONF_DONE goes high, indicates that configuration complete. After last data byte, DCLK must clocked times APEX devices, times Mercury devices, times FLEX devices release CONF_DONE initialize device. Figure
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116: Configuring SRAM-Based Devices
Figure Configuration Circuit
Note
APEX 20K, ACEX Mercury, FLEX Device
MSEL0
Memory
ADDR DATA[7.0]
MSEL1 CONF_DONE nSTATUS
Microprocessor
DATA[7.0] DCLK nCONFIG
Notes Figure
APEX 20K, Mercury, ACEX FLEX devices, configuration word Tabular Text File (.ttf), Binary File (.rbf), Hexadecimal (.hex) format. information create configuration programming files, "Device Configuration Files" page pull-up resistor should APEX 20KE APEX 20KC devices.
configure multiple APEX 20K, Mercury, ACEX FLEX devices mode cascading devices. Once first device configured, drives nCEO low, driving second device's low. second device begins configuration within clock cycle. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. addition, nSTATUS pins tied together; thus, device detects error, entire chain reset automatic reconfiguration. Figure
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration Circuit
APEX 20K, ACEX Mercury, FLEX Device Memory ADDR DATA[7.0] MSEL CONF_DONE nSTATUS Microprocessor nCEO MSELO
APEX 20K, ACEX Mercury, FLEX Device MSELO MSEL CONF_DONE nSTATUS DATA[7.0] DCLK nCONFIG
DATA[7.0] DCLK nCONFIG
Note Figure
pull-up resistor should APEX 20KE APEX 20KC devices. APEX 20KE APEX 20KC devices combined with other devices, 10-k pull-up resistor nSTATUS CONF_DONE pins.
Figure shows timing waveforms configuration APEX 20K, Mercury, ACEX FLEX devices. Figure Timing Waveform APEX 20K, Mercury, ACEX FLEX Devices
tCFG
nCONFIG nSTATUS DCLK DATA[7.0] RDYnBSY CONF_DONE INIT_DONE User
High High User Mode
tCF2CK
Cycles
tCLK
tDSU
Byte
tCH2B
Byte
Byte
User Mode User Mode
tCD2UM
Tables define timing parameters configuration APEX 20K, Mercury, ACEX FLEX devices.
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116: Configuring SRAM-Based Devices
Table Timing Parameters APEX Devices Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tStatus tST2CK
Note Units
16.7
Parameter
nCONFIG first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high first rising edge DCLK
0.75
Notes Table
This information preliminary. This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width.
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116: Configuring SRAM-Based Devices
Table Timing Parameters Mercury Devices Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tStatus tST2CK
Note
0.75 16.7
Parameter
nCONFIG first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high first rising edge DCLK
Units
Notes Table
This information preliminary. This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width.
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116: Configuring SRAM-Based Devices
Table Timing Parameters ACEX Devices Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tStatus tST2CK
Parameter
nCONFIG first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high first rising edge DCLK
0.75
Units
16.7
Notes Table
This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value.
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116: Configuring SRAM-Based Devices
Table Timing Parameters FLEX Devices Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tStatus tST2CK
Parameter
nCONFIG first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high first rising edge DCLK
0.75
Units
16.7
Notes Table
This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this number.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Parallel Configuration with APEX Devices
Parallel configuration APEX devices designed meet continuously increasing demand faster configuration times. APEX devices designed with capability receiving byte-wide configuration data clock cycle, guarantee configuration time less than with 66-MHz configuration clock. Designers take advantage parallel configuration feature using microprocessor, EPC8, EPC16 device.
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116: Configuring SRAM-Based Devices
This section discusses following schemes parallel configuration APEX devices:
Parallel configuration using configuration device Parallel configuration using microprocessor
Parallel Configuration Using Configuration Device
configuration device scheme parallel configuration uses either EPC8 EPC16 device supply data byte-wide fashion APEX device. Figure Figure APEX Parallel Configuration Using Configuration Device
APEX Device
DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO N.C.
EPC8 EPC16 Configuration Device
DCLK DATA[7.0] nINIT_CONF
Notes Figure
pull-up resistors should connected same supply voltage EPC16 EPC8 device. pull-up resistors nCS, nINIT_CONF pins EPC16 EPC8 devices have user-configurable internal pull-up resistors. internal pullup resistor nINIT_CONF always active. nINIT_CONF used, nCONFIG must pulled either directly through resistor. nCEO left unconnected last device chain.
configuration device scheme, nCONFIG tied nINIT_CONF. power target APEX device senses low-to-high transition nCONFIG initiates configuration. target APEX device then drives open-drain CONF_DONE low, which in-turn drives EPC8 EPC16 device's low.
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116: Configuring SRAM-Based Devices
Before configuration starts, there delay PORSEL connected EPC16 EPC8 device. PORSEL connected GND, delay When each device determines that power stable, will release nSTATUS pin. Since EPC16 EPC8 device's connected target APEX device's nSTATUS pin, configuration delayed until both nSTATUS pins released each device, when each devices signal will pulled resistor. When configuring multiple devices, connect nSTATUS pins together ensure configuration only happens when devices release their nSTATUS pins. EPC16 EPC8 device then clocks data parallel APEX device using 66-MHz internal oscillator. there error during configuration, APEX device drives nSTATUS low, resetting itself internally resetting configuration device. Quartus software provides Auto-restart configuration after error option that automatically initiates reconfiguration whenever error occurs. following instructions turn this option off: Compiler Settings (Processing menu) Choose Chips Devices Click Device Options General tab, check uncheck Auto-restart configuration after error option Click twice this option turned off, nSTATUS must monitored check errors. initiate reconfiguration, pulse nCONFIG low. external system pulse nCONFIG under system control rather than tied VCC. Therefore, nCONFIG must connected nINIT_CONF need reprogram APEX device fly. When configuration complete, APEX device releases CONF_DONE pin, which then pulled resistor. This disables EPC16 EPC8 device driven high. When initialization complete, APEX device enters user mode. EPC16 EPC8 device drives DCLK before after configuration.
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116: Configuring SRAM-Based Devices
after sending data, EPC8 EPC16 device does detect CONF_DONE going high, recognizes that APEX device configured successfully. EPC8 EPC16 device pulses microseconds, driving nSTATUS APEX device low. Auto-restart configuration after error option APEX device resets then pulses nSTATUS low. When nSTATUS returns high, reconfiguration restarted (see Figure page 45). drive CONF_DONE after device configuration delay initialization. Instead, Enable user-supplied start-up clock option same Quartus dialog Auto-restart configuration after error option. Figure shows dialog enable disable this option. This option used synchronize initialization multiple devices that same configuration chain. Devices same configuration chain will initialize together.
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116: Configuring SRAM-Based Devices
Figure Configuration Options Dialog
Figure shows configuration multiple APEX devices with EPC16 EPC8 device. This circuit similar Figure (configuring single APEX device with EPC16 EPC8 configuration device), except that APEX devices cascaded multi-device configuration. EPC16 EPC8 device itself cannot cascaded.
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116: Configuring SRAM-Based Devices
Figure Parallel Configuration with Multiple APEX Devices EPC8 EPC16 Configuration Device
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
APEX Device MSEL1 MSEL0 DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG
EPC8 EPC16 Configuration Device DCLK DATA[7.0] nINIT_CONF
N.C.
nCEO
nCEO
Notes Figure
pull-up resistors should connected same supply voltage EPC16 EPC8 device. pull-up resistors nCS, nINIT_CONF pins EPC16 EPC8 devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. nINIT_CONF used, nCONFIG must pulled either directly through resistor. nCEO left unconnected last device chain.
After first APEX device completes configuration during multidevice configuration, nCEO activates second APEX device's pin, prompting second device begin configuration. devices initialize enter user mode same time since CONF_DONE pins tied together. Since nSTATUS tied together, configuration stops whole chain device (including EPC16 EPC8) detects error. Also, EPC16 EPC8 device does detect high CONF_DONE configuration, will pulse microseconds reset chain. pulse will drive nSTATUS APEX devices, causing them enter error state. This state similar APEX device detecting error. Auto-restart configuration after error option APEX devices release their nSTATUS pins after reset time-out period. When nSTATUS pins released pulled high, configuration devices reconfigure chain. Auto-restart configuration after error option nSTATUS will stay until APEX devices reset with pulse nCONFIG. Figure shows configuration device timing waveform APEX devices.
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116: Configuring SRAM-Based Devices
Figure Configuration Device Timing Waveform APEX Devices
nINIT_CONF VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE
Note
tPOR
tDSU
DCLK DATA User INIT_DONE
tOEZX
User Mode
Tri-State
Tri-State
Notes Figure
timing information, refer Configuration Devices APEX FLEX Devices Data Sheet EPC16 Configuration Device Data Sheet. configuration device will drive DATA after configuration. APEX devices enter user mode clock cycles after CONF_DONE goes high.
Parallel Configuration with Microprocessor
When using microprocessor parallel configuration, microprocessor transfers data from storage device APEX device configuration hardware. initiate configuration, microprocessor needs generate low-to-high transition nCONFIG APEX device must release nSTATUS. microprocessor then places configuration data DATA[7:0] pins APEX device bits time. Data clocked continuously into APEX device until CONF_DONE goes high. After data transferred, DCLK must clocked additional times APEX device initialize. APEX device's CONF_DONE goes high show successful configuration start initialization. configuration files created Quartus software incorporate extra bits initialization driving DCLK device after configuration. These extra bits affect device operation. Therefore, sending entire configuration file device sufficient configure initialize Configuration paused halting DCLK. Although there maximum DCLK period, configuration clock speed should below ensure correct configuration.
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116: Configuring SRAM-Based Devices
APEX device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration error. With Auto-restart configuration after error option APEX device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure APEX device without pulsing nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sends data initialization clock starts, CONF_DONE INIT_DONE have gone high, must reconfigure APEX device. Figure shows circuit parallel configuration APEX device using microprocessor. Figure APEX Parallel Configuration Using Microprocessor
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK
Notes Figure
pull-up resistors should connected that meets APEX highlevel input voltage (VIH) specification. pull-up resistors nCEO left unconnected.
multi-device parallel configuration with microprocessor, nCEO first APEX device cascaded second device's pin. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. Because CONF_DONE pins devices connected together, devices initialize enter user mode same time.
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116: Configuring SRAM-Based Devices
Since nSTATUS pins also tied together, devices detects error, entire chain halts configuration drives nSTATUS low. microprocessor then pulse nCONFIG restart configuration. Auto-restart configuration after error option Quartus software, APEX devices release nSTATUS after reset time-out period. microprocessor then reconfigure devices once nSTATUS released. Figure shows multi-device configuration using microprocessor. Figure shows multi-device configuration when both APEX devices getting same data. Figure Multiple APEX Device Parallel Data Transfer Serial Configuration with Microprocessor
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX Device
MSEL1 CONF_DONE MSEL0
nSTATUS nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK DATA[7.0] nCONFIG DCLK
Notes Figure
pull-up resistors should connected that meets APEX high-level input voltage (VIH) specification. pull resistors nCEO last device left unconnected.
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116: Configuring SRAM-Based Devices
Figure Multiple APEX Device Parallel Configuration with Same Data Using Microprocessor
Memory
ADDR DATA[7.0]
APEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX Device
MSEL1 CONF_DONE MSEL0
N.C.
nSTATUS nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG DCLK
DATA[7.0] nCONFIG DCLK
Notes Figure
pull-up resistors should connected that meets APEX high-level input voltage (VIH) specification. pull resistors nCEO pins left unconnected when configuring same data into multiple APEX devices.
Figure shows timing waveform APEX devices. Table shows timing parameters APEX devices. Figure Timing Waveform APEX Devices
tCF2ST1 tCFG
nCONFIG
tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD ST2CK
CONF_DONE
DCLK
DATA
Byte Byte Byte Byte Byte
User Mode
tDSU
User INIT_DONE High-Z User Mode
tCD2UM
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116: Configuring SRAM-Based Devices
Table Timing Parameters APEX Devices Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tStatus tST2CK
Note
0.75 16.7
Parameter
nCONFIG first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high first rising edge DCLK
Units
Notes Table
This information preliminary. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width.
Configuration (FLEX 6000 Devices Only)
passive serial asynchronous (PSA) configuration, microprocessor drives data FLEX 6000 device. When mode, should pull DCLK high using pull-up resistor prevent unused configuration pins from floating. begin configuration, microprocessor drives nCONFIG high then pulls FLEX 6000 device's high. microprocessor places configuration FLEX 6000 device's DATA input pulses write data FLEX 6000 device. next rising edge nWS, FLEX 6000 device latches configuration data. Next, FLEX 6000 device drives RDYnBSY signal low, indicating that processing configuration data. microprocessor then perform other system functions while FLEX 6000 device processing data bit.
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116: Configuring SRAM-Based Devices
Afterward, microprocessor checks nSTATUS CONF_DONE. device asserts nSTATUS low, encountered error microprocessor should restart configuration. nSTATUS configuration data been received, FLEX 6000 device ready initialization. beginning initialization, CONF_DONE goes high indicate that configuration complete. both nSTATUS CONF_DONE low, microprocessor sends next data bit. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sent configuration data started initialization CONF_DONE high, microprocessor must reconfigure FLEX 6000 device. MAX+PLUS Quartus II-generated programming files include extra bits required initialize device configuration. However, configuration, FLEX 6000 device initialize itself. Therefore, FLEX 6000 device asserts CONF_DONE high initializes itself before data sent. microprocessor stop sending configuration data when CONF_DONE asserted high. FLEX 6000 device's pins toggled during configuration design meets specifications tCSSU, tWSP, tCSH Table page Figure shows configuration FLEX 6000 devices.
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116: Configuring SRAM-Based Devices
Figure Configuration Circuit FLEX 6000 Devices
FLEX 6000 Device
CONF_DONE nSTATUS nCEO DATA nCONFIG RDYnBSY DCLK MSEL
N.C.
Microprocessor
Notes Figure
pull-up resistor should connected same supply voltage FLEX 6000 device. nCEO left unconnected.
optional address decoder control device's pins. This decoder allows microprocessor select FLEX 6000 device accessing particular address, simplifying configuration process. microprocessor also control signals directly. signals active state (i.e., tied low) other signal toggled control configuration. FLEX 6000 device process data internally without microprocessor. When device ready next configuration data, pulls RDYnBSY high, causing microprocessor strobe next configuration data into FLEX 6000 device. Alternatively, signal strobed low, causing RDYnBSY signal appear DATA. simplify configuration, microprocessor wait total time tBUSY(Max) tRDY2WS+tW2SB before sending next data bit. Because RDYnBSY does need monitored, strobing read state configuration data saves system port. should drive data onto DATA while because causes contention. used monitor configuration, should tied high.
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116: Configuring SRAM-Based Devices
After configuration, nCS, nRS, nWS, RDYnBSY pins user pins. However, when using scheme, default these pins tri-stated user mode should driven microprocessor. scheme default changed MAX+PLUS software under "Global Project Device Option". FLEX 6000 device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option Quartus MAX+PLUS software, FLEX 6000 device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure FLEX 6000 device. this point, microprocessor does need pulse nCONFIG low. mode also used configure multiple FLEX 6000 devices. Multi-device configuration similar single-device configuration, except that FLEX 6000 devices cascaded. After first FLEX 6000 device configured, nCEO asserted low, which asserts second device's low, causing begin configuration. second FLEX 6000 device begins configuration within write cycle first device; therefore, transfer data destinations transparent microprocessor. FLEX 6000 device CONF_DONE pins tied together, FLEX 6000 devices initialize enter user mode same time. more than five FLEX 6000 devices used, buffer split fan-out signal. Figure
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116: Configuring SRAM-Based Devices
Figure Multi-Device Configuration Circuit FLEX 6000 Devices
FLEX 6000 Device
MSEL CONF_DONE nSTATUS DATA nCONFIG RDYnBSY nCEO
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DCLK
DATA nCONFIG RDYnBSY
DCLK
Notes Figure
pull-up resistor should connected same supply voltage FLEX 6000 device. nCEO left unconnected last device chain.
Figure shows FLEX 6000 timing waveforms configuration.
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116: Configuring SRAM-Based Devices
Figure Timing Waveforms FLEX 6000 Devices
tCFG
nCONFIG
tST2WS
nSTATUS
tSTATUS
CONF_DONE DATA
tCSH
tDSU
tCSSU
tWSP tCSSU
tRDY2WS
tWS2B tBUSY
RDYnBSY User INIT_DONE
Notes Figure
Upon power-up, nSTATUS held more than when reaches minimum requirement. DATA should left floating. should driven high low, whichever more convenient. After configuration, state nCS, nWS, RDYnBSY depends design programming FLEX 6000 device. Device pins user mode.
Figure shows FLEX 6000 timing waveforms when using strobed signal.
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116: Configuring SRAM-Based Devices
Figure Timing Waveforms Using FLEX 6000 Devices
tCFG tCF2WS
nCONFIG nSTATUS CONF_DONE DATA (Microprocessor)
tWS2RS tRSD7 tRS2WS tCSH tWSP tCSSU tSTATUS tCF2ST1 tST2WS tDSU
DATA (FLEX 6000)
tRDY2WS tCF2ST0 tCF2CD
Notes Figure
Upon power-up, nSTATUS held more than when reaches minimum requirement. DATA should left floating. should driven high low, whichever more convenient. After configuration, state nCS, nWS, nRS, RDYnBSY depends design programming FLEX 6000 device. Device pins user mode.
Table summarizes timing parameters configuration.
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116: Configuring SRAM-Based Devices
Table Timing Parameters FLEX 6000 Devices Symbol
tCFG tSTATUS tCF2ST1 tST2WS tCF2WS tDSU tCSSU tCSH tWSP tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCF2CD tCF2ST0
Parameter
nCONFIG pulse width nSTATUS pulse width nCONFIG high nSTATUS high nSTATUS high first rising edge nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge falling edge rising edge falling edge rising edge falling edge falling edge DATA7 valid with RDYnBSY signal nCONFIG CONF_DONE nCONFIG nSTATUS
Units
Note Table
This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices Only)
passive parallel asynchronous (PPA) schemes, microprocessor drives data APEX APEX 20K, Mercury, ACEX FLEX device download cable. When using scheme, should pull DCLK high through pull-up resistor prevent unused configuration pins from floating.
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116: Configuring SRAM-Based Devices
begin configuration, microprocessor drives nCONFIG high then asserts target device's high. Next, microprocessor places 8-bit configuration word target device's data inputs pulses low. rising edge nWS, target device latches byte configuration data then drives RDYnBSY signal low, indicating that processing byte configuration data. microprocessor then perform other system functions while APEX APEX 20K, Mercury, ACEX FLEX device processing byte configuration data. Next, microprocessor checks nSTATUS CONF_DONE. nSTATUS CONF_DONE released pulled high, microprocessor sends next data byte. nSTATUS low, device signaling error microprocessor should restart configuration. However, nSTATUS configuration data been received, device ready initialization. beginning initialization, CONF_DONE goes high indicate that configuration complete. Figure shows configuration circuit. optional address decoder controls device pins. This decoder allows microprocessor select APEX APEX 20K, Mercury, ACEX FLEX device accessing particular address, simplifying configuration process.
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116: Configuring SRAM-Based Devices
Figure Configuration Circuit APEX APEX 20K, Mercury, ACEX FLEX Devices
Address Decoder ADDR
Memory
ADDR DATA[7.0]
APEX APEX 20K, ACEX Mercury, FLEX Device CONF_DONE nSTATUS MSEL1 MSEL0
nCEO
N.C.
Microprocessor
DATA[7.0] nCONFIG RDYnBSY
DCLK
Notes Figure
nCEO left unconnected. pull resistor should connected same supply voltage APEX APEX 20K, Mercury, ACEX FLEX device. pull resistor should APEX 20KE APEX 20KC devices.
device's pins toggled during configuration design meets specifications tCSSU, tWSP, tCSH Tables page signals also controlled directly microprocessor. signals active state (i.e., tied low) other signal toggled control configuration.
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116: Configuring SRAM-Based Devices
APEX APEX 20K, Mercury, ACEX FLEX devices serialize data internally without microprocessor. When APEX APEX 20K, Mercury, ACEX FLEX device ready next byte configuration data, drives RDYnBSY high. microprocessor senses high signal when polls RDYnBSY, microprocessor strobes next byte configuration data into device. Alternatively, signal strobed, causing RDYnBSY signal appear DATA7. Because RDYnBSY does need monitored, reading state configuration data strobing saves system port. Data should driven onto data while because causes contention DATA7. used monitor configuration, should tied high. simplify configuration, microprocessor wait total time tBUSY(max) tRDY2WS+ tW2SB before sending next data bit. After configuration, nCS, nRS, nWS, RDYnBSY pins user pins. However, when scheme chosen Quartus MAX+PLUS software, default these pins tri-stated user mode should driven microprocessor. change this default option MAX+PLUS software, select Global Project Device Option dialog Quartus software, select Device Option dialog Compiler Setting menu. APEX APEX 20K, Mercury, ACEX FLEX device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option been Quartus MAX+PLUS software, APEX APEX 20K, Mercury, ACEX FLEX device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure APEX APEX 20K, Mercury, ACEX FLEX 10K. this point, microprocessor does need pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. CONF_DONE must monitored microprocessor detect errors determine when programming completes. microprocessor sends configuration data starts initialization CONF_DONE asserted, microprocessor must reconfigure APEX APEX 20K, Mercury, ACEX FLEX device.
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116: Configuring SRAM-Based Devices
mode also used configure multiple APEX APEX 20K, Mercury, ACEX FLEX devices. Multi-device configuration similar single-device configuration, except that APEX APEX 20K, Mercury, ACEX FLEX devices cascaded. After first APEX APEX 20K, Mercury, ACEX FLEX device configured, nCEO asserted, which asserts second device, causing begin configuration. second APEX APEX 20K, Mercury, ACEX FLEX device begins configuration within write cycle first device; therefore, transfer data destinations transparent microprocessor. APEX APEX 20K, Mercury, ACEX FLEX device CONF_DONE pins tied together, devices initialize enter user mode same time. Figure Figure Multi-Device Configuration Circuit APEX APEX 20K, Mercury, ACEX FLEX Devices
Address Decoder ADDR Memory
APEX APEX 20K, ACEX Mercury, FLEX Device DATA[7.0] CONF_DONE nSTATUS
DCLK
ADDR DATA[7.0] APEX APEX 20K, ACEX Mercury, FLEX Device DATA[7.0] DCLK CONF_DONE nSTATUS nCEO N.C. MSEL1 nCONFIG MSEL0 RDYnBSY
Microprocessor nCONFIG RDYnBSY
nCEO
MSEL1 MSEL0
Notes Figure
used, connected directly. nCEO left unconnected last device chain. pull-up resistor should connected same supply voltage APEX APEX 20K, Mercury, ACEX FLEX device. pull-up resistor should APEX 20KE APEX 20KC devices.
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116: Configuring SRAM-Based Devices
Figure shows APEX APEX 20K, Mercury, ACEX FLEX timing waveforms configuration. Figure Timing Waveforms APEX FLEX Devices
tCFG tCF2ST1
nCONFIG nSTATUS CONF_DONE DATA[7.0]
tRDY2WS tST2WS
Byte
tDSU tCF2WS
Byte
Byte
Byte
tCSSU tCSH
tWSP
tSTATUS tCF2ST0 tCF2CD tWS2B tBUSY tCD2UM
RDYnBSY
User I/Os INIT_DONE
High-Z
Notes Figure
Upon power-up, nSTATUS held more than when reaches minimum requirement. Upon power-up, CONF_DONE low. After configuration, state nCS, nWS, RDYnBSY depends design programmed into APEX APEX 20K, Mercury, ACEX FLEX device. Device pins user mode.
Figure shows APEX APEX 20K, Mercury, ACEX FLEX timing waveforms when using strobed signal.
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116: Configuring SRAM-Based Devices
Figure Timing Waveforms Using
tCF2ST1 tCFG
nCONFIG nSTATUS
tCF2SCD tSTATUS
CONF_DONE
tCSSU
tCSH
DATA[7.0]
tWSP tRS2WS
Byte
tDSU
Byte
Byte
(3),
INIT_DONE
tWS2RS tCF2WS
tWS2RS tRDY2WS
User
tWS2B
tCD2UM tBUSY
DATA7/RDYnBSY
Notes Figure
user toggle during configuration design meets specification tCSSU, tWSP, tCSH. Device pins user mode. DATA0 should left floating. should driven high low, whichever more convenient. Only DATA[7.1] pins pins during user mode. DATA0 only input user mode. DATA7 bidirectional pin. input data input, output show status RDYnBSY.
Tables through define APEX APEX 20K, Mercury, ACEX FLEX timing parameters configuration.
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116: Configuring SRAM-Based Devices
Table Timing Parameters APEX APEX Devices Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tWS2RS tRS2WS tRSD7 tCD2UM tCF2CD tCF2ST0 tCF2ST1
Note Units
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high
tRDY2WS RDYnBSY rising edge rising edge
tSTATUS nSTATUS pulse width
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116: Configuring SRAM-Based Devices
Table Timing Parameters Mercury Devices Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tWS2RS tRS2WS tRSD7 tCD2UM tCF2CD tCF2ST0 tCF2ST1
Note
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high
Units
tRDY2WS RDYnBSY rising edge rising edge
tSTATUS nSTATUS pulse width
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116: Configuring SRAM-Based Devices
Table Timing Parameters ACEX Devices Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCD2UM tSTATUS tCF2CD tCF2ST0 tCF2ST1
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge rising edge rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode nSTATUS pulse width nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high
Units
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116: Configuring SRAM-Based Devices
Table Timing Parameters FLEX Devices Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCD2UM tSTATUS tCF2CD tCF2ST0 tCF2ST1
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge
Units
Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge rising edge rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode nSTATUS pulse width nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high
Notes Tables
Timing information APEX Mercury devices preliminary. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period APEX APEX devices Mercury devices obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width. This value only applies internal oscillator selected clock source starting device. clock source CLKUSR DCLK multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period obtain this value. This parameter value applies EPF10K10, EPF10K20, EPF10K40, EPF10K50, FLEX 10KA, FLEX 10KE devices. This parameter value applies EPF10K70 EPF10K100 devices only.
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116: Configuring SRAM-Based Devices
information create configuration programming files this configuration scheme, "Device Configuration Files" page
JTAG Programming Configuration (APEX APEX 20K, Mercury, ACEX FLEX Devices)
Joint Test Action Group (JTAG) developed specification boundary-scan testing. This boundary-scan test (BST) architecture offers capability efficiently test components PCBs with tight lead spacing. architecture test connections without using physical test probes capture functional data while device operating normally. JTAG circuitry also used shift configuration data into device.
more information JTAG boundary-scan testing, Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices). device operating JTAG mode uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. other pins tri-stated during JTAG configuration. should begin JTAG configuration until other configuration complete. Table shows each JTAG pin's function.
Table JTAG Descriptions
Description
Test data input Test data output
Function
Serial input instructions well test programming data. Data shifted rising edge TCK. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device.
Test mode select Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. Test clock input clock input circuitry. Some operations occur rising edge, while others occur falling edge. Active-low input asynchronously reset boundary-scan circuit. TRST optional according IEEE Std. 1149.1.
TRST Test reset input (optional) Note Table
FLEX devices 144-pin thin quad flat pack (TQFP) packages have TRST pin. Therefore, TRST ignored when using these devices.
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116: Configuring SRAM-Based Devices
During JTAG configuration, data downloaded device through MasterBlaster ByteBlasterMV header. Configuring devices through cable similar programming devices in-system, except TRST should connected VCC; this connection ensures that controller reset. Figure
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116: Configuring SRAM-Based Devices
Figure JTAG Configuration Single APEX APEX 20K, Mercury, ACEX FLEX Device
APEX APEX 20K, ACEX Mercury, FLEX Device
TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
MasterBlaster ByteBlasterMV 10-Pin Male Header (Top View)
Notes Figure
pull-up resistor should connected same supply voltage download cable. FLEX devices 144-pin TQFP packages have TRST pin. Therefore, TRST ignored when configuring FLEX devices 144-pin TQFP packages. nCONFIG, MSEL0, MSEL1 pins should connected support JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. pull-up resistor should APEX 20KE APEX 20KC devices.
configure single device JTAG chain, programming software places other devices BYPASS mode. BYPASS mode, devices pass programming data from through single bypass register without being affected internally. This scheme enables programming software program verify target device. Configuration data driven into device appears clock cycle later.
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116: Configuring SRAM-Based Devices
APEX APEX 20K, Mercury, ACEX FLEX devices have dedicated JTAG pins that always function JTAG pins. JTAG testing performed APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices both before after configuration, during configuration. chip-wide reset output enable pins APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices affect JTAG boundary-scan programming operations. Toggling these pins does affect JTAG operations (other than usual boundary-scan operation). When designing board JTAG configuration APEX APEX 20K, Mercury, ACEX FLEX devices, regular configuration pins should considered. Table shows these pins should connected during JTAG configuration. Table Descriptions Signal
Description
APEX APEX 20K, Mercury, ACEX FLEX devices chain should driven connecting ground, pulling down resistor, driving some control circuitry. Pulled 10-k resistor. When configuring multiple devices same JTAG chain, each nSTATUS should pulled individually. Pulled 10-k resistor. When configuring multiple devices same JTAG chain, each CONF_DONE should pulled individually. Driven high connecting VCC, pulling resistor, driven some control circuitry. These pins must left floating. These pins support whichever non-JTAG configuration used production. only JTAG configuration used, should both pins ground. Should left floating. Drive high, whichever more convenient. Should left floating. Drive high, whichever more convenient. This JTAG connected download cable. should driven logic high.
nSTATUS CONF_DONE nCONFIG MSEL0, MSEL1 DCLK DATA0 TRST Note Table
nSTATUS pulling middle JTAG configuration indicates that error occurred. CONF_DONE pulling high JTAG configuration indicates successful configuration.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
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116: Configuring SRAM-Based Devices
JTAG Programming Configuration Multiple Devices (APEX APEX 20K, Mercury, ACEX FLEX Devices)
When programming JTAG device chain, JTAG-compatible header, such ByteBlasterMV header, connected several devices. number devices JTAG chain limited only drive capability download cable. However, when more than five devices connected JTAG chain, Altera recommends buffering TCK, TDI, pins with on-board buffer. JTAG-chain device programming ideal when contains multiple devices, when testing using JTAG circuitry. Figure shows configuration. Figure Multi-Device JTAG Configuration
MasterBlaster ByteBlasterMV 10-Pin Male Header
Notes (1),
APEX APEX 20K, APEX APEX 20K, ACEX Mercury, ACEX Mercury, FLEX Device FLEX Device
APEX APEX 20K, ACEX Mercury, FLEX Device nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
Notes Figure
APEX APEX 20K, Mercury, ACEX FLEX 10K, devices placed within same JTAG chain device programming configuration. more information configuration pins connected this mode, refer Table page pull-up/pull-down resistors APEX 20KE APEX 20KC devices, pull resistors nSTATUS CONF_DONE nCONFIG, MSEL0, MSEL1 pins should connected support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. TRST only available APEX APEX 20K, Mercury, ACEX devices, FLEX devices except TQFP 144-pin package.
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116: Configuring SRAM-Based Devices
Successful JTAG configuration verified automatically Quartus MAX+PLUS software JTAG configuration. software checks state CONF_DONE through JTAG port configuration. CONF_DONE correct state, Quartus MAX+PLUS software indicates that configuration failed. CONF_DONE correct state, software indicates that configuration successful. When using JTAG pins configuration, VCCIO tied both pins JTAG port will drive 3.3-V levels.
JTAG non-JTAG configuration should attempted simultaneously. When configuring JTAG, allow non-JTAG configuration complete first. Figure shows JTAG configuration APEX APEX 20K, Mercury, ACEX FLEX device with microprocessor. Figure JTAG Configuration APEX APEX 20K, Mercury, ACEX FLEX Device with Microprocessor
Memory
ADDR DATA
APEX APEX 20K, ACEX Mercury, FLEX Device Microprocessor
nSTATUS CONF_DONE
Note Figure
pull-up resistors except APEX 20KE APEX 20KC devices, which
STAPL Programming Test Language
In-circuit configuration embedded processor enables easy design prototyping, streamlines production, allows quick efficient in-field upgrades. JamStandard Test Programming Language (STAPL) programming test language, standard file format using IEEE Std. 1149.1 (JTAG) interface, further simplifies in-circuit configuration providing small file sizes increased flexibility. Files Byte-Code Files (.jbc) contain both programming algorithm data required upgrade more devices. language supported MAX+PLUS software versions higher Quartus software.
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116: Configuring SRAM-Based Devices
estimate size using following equation: Size Where:
Data
Space used algorithm (see Table Data Space used compressed programming data (see Table Index representing family type(s) being targeted Number target devices chain
Table Algorithm Constants Device
APEX APEX 20KE ACEX FLEX FLEX 10KE FLEX 10KA
Typical File Algorithm Size (Kbytes)
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116: Configuring SRAM-Based Devices
Table Data Constants Device Typical STAPL Byte-Code Data Size (Kbytes) Compressed
EPF10K10, EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K10K50, EPF10K50V EPF10K50E EPF10K70 EPF10K100, EPF10K100A, EPF10K100B EPF10K100E EPF10130E EPF10K130V EPF10K200E EPF10K250A EP1K10 EP1K30 EP1K50 EP1K100 EP20K100 EP20K200 EP20K400 1,180
Uncompressed
Combining Different Configuration Schemes
more information configure devices using STAPL programming test language, Application Note (Using STAPL Embedded Processor). This section shows configure APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 devices using multiple configuration schemes same board. Figure shows configuration APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device using download cable configuration device. Figure multiple PLDs configured simultaneously with same data.
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116: Configuring SRAM-Based Devices
Figure Device Configuration with Download Cable Configuration Device
Note
APEX APEX 20K, Mercury, ACEX FLEX Device MSEL1 MSEL0
MasterBlaster ByteBlasterMV 10-Pin Male Header
DCLK CONF_DONE nCONFIG (10) nSTATUS DATA0
nCEO N.C.
APEX APEX 20K, Mercury, ACEX FLEX Device MSEL1 MSEL0
EPC16, EPC8, EPC2 Device DATA DCLK VCCSEL VPPSEL nCASC nINIT_CONF
DCLK CONF_DONE nCONFIG (10) nSTATUS DATA0
nCEO
N.C.
N.C.
APEX APEX 20K, Mercury, ACEX FLEX Device MSEL1 MSEL0
DCLK CONF_DONE nCONFIG (10) nSTATUS DATA0
nCEO
N.C.
Notes Figure
this Figure eight PLDs simultaneously configured with same data. should connected same supply voltage configuration device. pull-up resistors APEX 20KE APEX 20KC devices, pull-up resistors nSTATUS CONF_DONE pins nINIT_CONF pins EPC16, EPC8, EPC2 devices have internal user configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. download cable programs configuration device (EPC16, EPC8, EPC2 device). reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected single device configuration. 3.3-V supply voltage used, VCC, VCCSEL, VPP, VPPSEL pins should connected 3.3-V supply. 5.0-V supply voltage used, pins should connected 5.0-V supply, VCCSEL VPPSEL pins should connected ground. improve in-system programming times, connect VPPSEL ground. more information these pins, Table page configuration device configures APEX APEX 20K, Mercury, ACEX FLEX device. Figure shows connections EPC16, EPC8, EPC2 configuration device. other configuration device, connect pins appropriately. diode between APEX 20KE device's nCONFIG configuration device's nINIT_CONF isolate 1.8-V 3.3-V power supplies. Select diode with threshold voltage (VT) less than equal diode will make nINIT_CONF open-drain pin. These pins will only break drive tri-state. (10) ensure that configuration device successfully configures APEX 20KE APEX 20KC device possible power-up sequences, resistor pull nCONFIG VCCINT.
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116: Configuring SRAM-Based Devices
Figure shows schematic configuring APEX 20K, FLEX 10K, FLEX 6000 devices using download cables EPC2 device. Figure Device Configuration with Download Cable EPC2, EPC8, EPC16 Device
MasterBlaster JTAG ByteBlasterMV 10-Pin Male Header 10-Pin Male Header
APEX 20K, FLEX 10K, FLEX 6000 Device MSEL1 MSEL0
EPC16, EPC8, EPC2 Device
DCLK CONF_DONE nCONFIG nSTATUS DATA0
VCCINT VCCIO nCEO
N.C.
DATA DCLK
VCCSEL VPPSEL nCASC nINIT_CONF
Notes Figure
should connected same supply voltage configuration device. target APEX APEX 20K, Mercury, ACEX FLEX device configured either configuration device download cable. pull-up resistors APEX 20KE APEX 20KC devices, pull-up resistors nSTATUS CONF_DONE pins should download cable programs configuration device through JTAG circuitry. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. VCCINT VCCIO should applied according target device's VCCINT VCCIO. nCEO left unconnected. should attempt configuration with download cable while configuration device connected APEX APEX 20K, Mercury, ACEX FLEX device. perform this operation, should either remove configuration device from socket when using download cable, place switch five common signals between download cable configuration device. 3.3-V supply voltage used, VCC, VCCSEL, VPP, VPPSEL pins should connected 3.3-V supply voltage. 5.0-V supply voltage used, pins should connected 5.0-V supply voltage, VCCSEL VPPSEL pins should connected ground. improve in-system programming times, connect VPPSEL ground. more information these pins, Table page
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116: Configuring SRAM-Based Devices
Using Flash Memory Configure PLDs
Altera introduces higher-density PLDs, configuration stream size also increases. result, designs require more configuration devices store data configure these devices. disadvantage having multiple configuration devices only that they take valuable board space, multiple devices also increase board complexity. Flash memory used store configuration data. Flash memory controller required read write Flash memory perform configuration. 3000 7000 device implement Flash memory controller. There separate design files available both 7000 3000A devices Altera site (http://www.altera.com). download these files from application notes literature page underneath 116: Configuring SRAM-Based Devices.
Device Configuration Using Flash Memory 3000A Devices
Flash memory controller interface with microprocessor receive configuration data parallel port (Figure 39). controller generates programming command sequence program Flash memory extract configuration data configure PLDs. Flash memory controller supports various commands such
Programming Flash memory Configuring PLDs Verifying content Flash memory
Altera Corporation
116: Configuring SRAM-Based Devices
Figure Configuring through Flash Memory 3000A Controller
Flash Memory WP/ACC DQ[7.0] A[20.0] BYTE RY/BY Clock Clock O[7.0]
3000A Device
APEX 20KE Device MSEL0 nSTATUS CONF_DONE nCONFIG DCLK DATA0 nCEO INIT_DONE MSEL1
nSTATUS CONF_DONE nCONFIG DCLK DATA0
A[20.0] RY/BY
MasterBlaster ByteBlasterMV 10-Pin Male Header
MasterBlaster ByteBlasterMV 10-Pin Male Header
Restart MAX2PC_ACK CONF_STATUS7.0] PC2MAX_STB PC_DATA1 PC_DATA0 nSTATUS CONF_DONE nCONFIG DCLK DATA0
Computer Microprocessor
APEX 20KE Device MSEL0 MSEL1
nCEO INIT_DONE
Note Figure
resistors APEX 20KE APEX 20KC devices, resistors nSTATUS CONF_DONE pins.
Flash Memory Controller Design Specification
controller will check Flash memory programmed successfully after board powers Flash memory programmed successfully, then controller configures PLDs. Flash memory programmed successfully, then controller waits commands from microprocessor. receiver decodes commands receives from microprocessor following:
Program Flash memory Configure Verify Flash memory programming
After command executed, controller returns idle mode waits next command. Figure shows controller state machine.
Altera Corporation
116: Configuring SRAM-Based Devices
Figure Flash Memory Controller State Machine
Check Flash Memory been Programmed
Configure APEX Devices
IDLE Wait Commands from from
Done Programming
Decode Command
Program Flash Memory
Configure APEX Devices
Verify Flash Memory Content
Flash Memory Controller Functionality
controller writes byte special location Flash memory when programs memory. After POR, controller checks this special location Flash memory byte written there not. byte written, then Flash memory been programmed controller proceed configuring PLDs reading data from Flash memory. this byte there value expected, controller will idle wait programmed microprocessor.
Altera Corporation
116: Configuring SRAM-Based Devices
Getting Data from Microprocessor
microprocessor uses parallel port interface with controller. There types signals involved this connection (see Figure 41), 3-bit input signal from microprocessor controller, 2-bit output signal from controller microprocessor. input signal includes following three signals:
STB: Strobe signal from microprocessor indicate that microprocessor's data valid. data_mode: Indicates whether controller command mode data mode. When data_mode high, controller command mode; when data_mode low, controller data mode. data: Content this signal depends data_mode. data command mode data mode.
output signal contains following signals:
ACK: Acknowledge signal handshaking signal from controller microprocessor. conf_status: Indicates configuration status.
Figure Getting Data from Microprocessor
Data_mode
Mode
Data Mode
Data
Note Figure
Data sent both positive negative edges signal.
Altera Corporation
116: Configuring SRAM-Based Devices
controller receives data command from microprocessor rising falling edges signal. After receiving this data, controller will send acknowledgement signal microprocessor initiate sending next data. acknowledge signal (ACK) should same logic level last received signal. de-asserting ACK, controller stop microprocessor from sending data. Figure shows relationship. Figure Sending Acknowledge Signal (ACK) Microprocessor
Data_mode
Mode
Data Mode
Data
Note Figure
data received each signal edge (both positive negative).
Programming Flash Memory
After receiving command from microprocessor, controller first erases then starts programming Flash memory. separate state machine required generate programming command sequence programming pulse width. While programming Flash memory, controller must check command (data_mode=1) been received not. command indicates data from microprocessor, controller will exit Program_Flash_memory state into idle mode.
Altera Corporation
116: Configuring SRAM-Based Devices
Another state machine required read serialize byte data from Flash memory generate DCLK DATA0. controller needs monitor CONF_DONE signals from PLDs determine configuration complete. When configuration done, controller exits configure state goes back idle mode.
Flash Memory Content Verification
There types Flash memory controllers. works with AMD/ Fujitsu Flash memory, other works with Intel's Flash memory. Verification supported with AMD/ Fujitsu Flash Memory, supported with Intel's. verify that content Intel Flash memory same configuration file, verifying command necessary. Once issues verifying command, device will read back from Flash memory. Every time device reads byte, will send each data from that byte microprocessor through ByteBlasterMV cable. software running realigns each into byte then reconstructs file based byte data read back from device. During reconstruction, software adds required commas line breaks into file that will have exactly same format file Quartus software created. whole process stops when device finishes reading back from Flash memory. this time, software finished constructing file. this point, software will compare reconstructed file with original check they same. program will output message stating results comparison. error found during verification, controller will CONF_STATUS signal inform microprocessor that there verification error, returns idle state immediately. During verification, controller still needs check command (data_mode=1) been received not. This command indicates data from microprocessor. Following this, controller will exit Program_Flash_Memory state into idle mode.
Device Configuration Using Flash Memory 7000 Devices
Figure shows schematic this configuration scheme with 7000 device. sample design files 7000 device (Figure Design File Configuring APEX Devices Figure Design File Configuring FLEX FLEX 6000 Devices) available Altera site under 116: Configuring APEX 20K, FLEX FLEX 6000 Devices.
Altera Corporation
116: Configuring SRAM-Based Devices
Figure Device Configuration Using External Memory 7000 Device
Oscillator 7000 Device
nSTATUS
APEX APEX 20K, ACEX Mercury, FLEX 10K, FLEX 6000 Device MSEL0
nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Memory
DATA[] ADDR[] RESTART ADDR[] RESTART
INIT_DONE CONF_DONE DCLK DATA0 nCONFIG
APEX APEX 20K, ACEX Mercury, FLEX 10K, FLEX 6000 Device
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
N.C.
Notes Figure
FLEX 6000 devices have single MSEL pin, which tied ground, DATA0 renamed DATA. nCEO left unconnected last device chain. pull-up resistors APEX 20KE APEX 20KC devices, pull-up resistors nSTATUS, CONF_DONE, INIT_DONE pins should
Figure shows timing waveform configuring APEX APEX 20K, Mercury, ACEX FLEX 10K, FLEX 6000 device using external memory 7000 device.
Altera Corporation
116: Configuring SRAM-Based Devices
Figure Timing Waveform Configuration Using External Memory 7000 Device
nSTATUS nCONFIG DCLK DATA0 D[7.0] ADDR[15.0] CONF_DONE RESTART INIT_DONE
Device Options
ACEX FLEX 10K, FLEX 6000 device options Altera's MAX+PLUS development software choosing Global Project Device Options (Assign menu). also device options Quartus software using Device Option dialog box. choose this option, select Processing menu, choose Compiler Settings, then click Chips Devices tab. Table summarizes each these options.
Altera Corporation
116: Configuring SRAM-Based Devices
Table APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration Option Bits (Part Device Option
User-supplied start-up clock (ACEX FLEX 10K, FLEX 6000 devices only.)
Option Usage
complete initialization, device must clocked times after data transferred. CONF_DONE goes high after initialization process begun. select which clock source initialization choosing CLKUSR rather than DCLK.
Default Configuration (Option Off)
configuration schemes, device's internal oscillator supplies initialization clock.
Modified Configuration (Option
user provides clock CLKUSR pin. This clock synchronize initialization multiple devices. clock should supplied when configuration device, last data byte transferred. schemes, internal Supplying clock during oscillator disabled. Thus, configuration will affect external circuitry, such configuration process. configuration device download operation CLKUSR cable, must provide during user mode selected initialization clock DCLK software. pin. configuration device scheme, configuration device supplies clock; schemes, microprocessor supplies clock. user provides clock CLKUSR DCLK pin. Quartus software specifies which used. This clock synchronizes initialization multiple devices. clock should supplied when last data byte transferred. Supplying clock CLKUSR will affect configuration process. Quartus software specifies CLKUSR pin's operation mode. When using configuration device, CLKUSR synchronize initialization; DCLK used passive configuration only.
User-supplied start-up clock (APEX APEX 20K, Mercury devices only).
begin initialization, device's internal oscillator supplies start-up clock. device must clocked times APEX APEX devices times Mercury devices after data transferred. CONF_DONE goes high after initialization process begins. device initialized internal oscillator external clocks provided DCLK CLKUSR.
Altera Corporation
116: Configuring SRAM-Based Devices
Table APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration Option Bits (Part Device Option Option Usage Default Configuration (Option Off)
configuration process stops until direct device restart configuration. nSTATUS driven when error occurs. When nCONFIG pulled then high, device begins reconfigure.
Modified Configuration (Option
configuration process restarts automatically. nSTATUS drives releases. nSTATUS then pulled pullup resistor, indicating that configuration restart. configuration device scheme, target device's nSTATUS tied configuration device's pin, nSTATUS reset pulse resets configuration device automatically. configuration device releases (which pulled high) reconfiguration begins. error occurs during passive configuration, device reconfigured without system having pulse nCONFIG. After nSTATUS goes high, reconfiguration begin.
Auto-restart data error occurs during configuration configuration, frame error choose restart configuration.
Release clears During configuration, before tridevice pins states tri-stated. During initialization, choose order releasing tri-states clearing registers. Enable chipwide reset Enables single reset device registers.
device releases tri-states device releases clear pins before releasing signals registers before clear signal registers. releasing tri-states. this option allow design operate before drives out, outputs start low. Chip-wide reset enabled. Chip-wide reset enabled DEV_CLRn available registers device. user pin. registers cleared when DEV_CLRn driven low.
Altera Corporation
116: Configuring SRAM-Based Devices
Table APEX APEX 20K, Mercury, ACEX FLEX FLEX 6000 Configuration Option Bits (Part Device Option
Enable chipwide output enable
Option Usage
Default Configuration (Option Off)
Modified Configuration (Option
Chip-wide output enable enabled device tri-states. After configuration, user pins tri-stated when DEV_OE low. INIT_DONE signal available open-drain INIT_DONE pin. This drives during configuration. After initialization, released pulled high externally. INIT_DONE must connected pull-up resistor. INIT_DONE output used, INIT_DONE cannot used user pin. JTAG boundary-scan testing performed before after dev
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