AIN1 AIN8 2.5V IN/REF FEATURES Specified +2.7 +5.25 Flexible Powe
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+2.7 +5.25 Micropower, 8-Channel, kSPS, 12-Bit 16-Lead TSSOP AD7888
AIN1 AIN8 2.5V IN/REF
FEATURES Specified +2.7 +5.25 Flexible Power/Throughput Rate Management Shutdown Mode: Eight Single-Ended Inputs Serial Interface: SPITM/QSPITM/MICROWIRETM/DSP Compatible 16-Lead Narrow SOIC TSSOP Packages APPLICATIONS Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) Instrumentation Control Systems High Speed Modems
AD7888
COMP
CHARGE REDISTRIBUTION
CONTROL LOGIC
GENERAL DESCRIPTION
AGND SPORT
AGND
AD7888 high speed, power, 12-bit that operates from single +2.7 +5.25 power supply. AD7888 capable kSPS throughput rate. input track-andhold acquires signal features single-ended sampling scheme. AD7888 contains eight single-ended analog inputs, AIN1 through AIN8. analog input each these channels from VREF. part capable converting full power signals MHz. AD7888 features on-chip reference that used reference source converter. IN/REF allows user access this reference. Alternatively, this overdriven provide external reference voltage AD7888. voltage range this external reference from VDD. CMOS construction ensures power dissipation typically normal operation power-down mode. part available 16-lead narrow body small outline (SOIC) 16-lead thin shrink small outline (TSSOP) package.
DOUT
SCLK
PRODUCT HIGHLIGHTS
Smallest 12-bit 8-channel ADC; 16-lead TSSOP same area 8-lead SOIC less than half height. Lowest Power 12-bit 8-channel ADC. Flexible power management options including automatic power-down after conversion. Analog input range from VREF (VDD). Versatile serial port (SPI/QSPI/MICROWIRE/DSP Compatible).
QSPI trademarks Motorola, Inc. MICROWIRE trademark National Semiconductor Corporation.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
+5.25 REFIN/REFOUT AD7888-SPECIFICATIONS +2.7 ,tounless otherwise noted) +2.5 External/Internal Reference unless otherwise noted; +2.7 +5.25
SCLK
Parameter DYNAMIC PERFORMANCE Signal Noise Distortion Ratio2, (SNR) Total Harmonic Distortion2 (THD) Peak Harmonic Spurious Noise2 Intermodulation Distortion2 (IMD) Second Order Terms Third Order Terms Channel-to-Channel Isolation2 Full Power Bandwidth ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error Offset Error Match2 Gain Error2 Gain Error Match2 ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT REFIN Input Voltage Range Input Impedance REFOUT Output Voltage REFOUT Tempco LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, Output Voltage, Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Throughput Time Track/Hold Acquisition Time2 Conversion Time
Version VREF 2.5/VDD 2.45/2.55
Version VREF 2.5/VDD 2.45/2.55
Units Bits Volts min/max min/max ppm/°C
Test Conditions/Comments Sine Wave, fSAMPLE kSPS Sine Wave, fSAMPLE kSPS Sine Wave, fSAMPLE kSPS 9.983 kHz, 10.05 kHz, fSAMPLE kSPS 9.983 kHz, 10.05 kHz, fSAMPLE kSPS Channel
Guaranteed Missed Codes Bits Grade) Guaranteed Missed Codes Bits Grade) 4.75 5.25 (Typically LSB) (Typically LSB) Typically with Internal Reference
When Track When Hold Functional from Very High Impedance Internal Reference Disabled
+4.75 +5.25 +2.7 +3.6 +2.7 +5.25 Typically
Straight (Natural) Binary 14.5 14.5
ISOURCE +2.7 +5.25 ISINK
SCLK Cycles SCLK Cycles SCLK Cycles
Conversion Time Acquisition Time. kSPS with Clock 7.25 Clock)
REV.
AD7888
Parameter POWER REQUIREMENTS Normal Mode5 (Static) Normal Mode (Operational) Using Standby Mode Using Shutdown Mode Standby Mode6 Shutdown Mode6 Normal-Mode Power Dissipation Shutdown Power Dissipation Standby Power Dissipation Version
Version
Units min/max
Test Conditions/Comments
+2.7/+5.25
+2.7/+5.25
fSAMPLE kSPS fSAMPLE kSPS fSAMPLE kSPS fSAMPLE kSPS +2.7 +5.25 +4.75 +5.25 (0.5 typ) +2.7 +3.6
NOTES Temperature ranges follows: Version: -40°C +105°C; Version: +105°C. Terminology. calculation includes distortion noise components. Sample tested +25°C ensure compliance. digital inputs except VDD. load digital outputs. Analog inputs GND. SCLK when SCLK off. digital inputs except VDD. load digital outputs. Analog inputs GND. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
ORDERING GUIDE Linearity Error Package Package (LSB)1 Descriptions Options SOIC SOIC TSSOP TSSOP R-16A R-16A RU-16 RU-16
AGND -0.3 Analog Input Voltage AGND -0.3 Digital Input Voltage AGND -0.3 Digital Output Voltage AGND -0.3 REFIN/REFOUT AGND -0.3 Input Current Except Supplies2 Operating Temperature Range Commercial Version) -40°C +105°C Version) +105°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C SOIC, TSSOP Package, Power Dissipation Thermal Impedance 124.9°C/W (SOIC) 150.4°C/W (TSSOP) Thermal Impedance 42.9°C/W (SOIC) 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase secs) +215°C Infrared secs) +220°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latch-up.
Model AD7888AR AD7888BR2 AD7888ARU AD7888BRU2 EVAL-AD7888CB3 EVAL-CONTROL BOARD4
NOTES Linearity error here refers integral linearity error. Contact factory availability. This used stand-alone evaluation board conjunction with EVAL-CONTROL BOARD evaluation/demonstration purposes. This board complete unit allowing control communicate with Analog Devices evaluation boards ending designators.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7888 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7888 TIMING SPECIFICATIONS1
TMAX unless otherwise noted)
Parameter fSCLK tCONVERT tACQ
Limit TMIN, TMAX Versions) +4.75 +5.25 +2.7 +3.6 14.5 tSCLK tSCLK tSCLK tSCLK 14.5 tSCLK tSCLK tSCLK tSCLK
Units
Description
Throughput Time tCONVERT tACQ tSCLK SCLK Setup Time Delay from until DOUT 3-State Disabled Data Access Time after SCLK Falling Edge Data Setup Time Prior SCLK Rising Edge Data Valid SCLK Hold Time SCLK High Pulsewidth SCLK Pulsewidth Rising Edge DOUT High Impedance Power-Up Time from Shutdown
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Mark/Space ratio SCLK input 40/60 60/40. Measured with load circuit Figure defined time required output cross with time output cross with 10%. derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time, quoted timing characteristics true relinquish time part independent loading. Specifications subject change without notice.
OUTPUT
+1.6V 50pF
Figure Load Circuit Digital Output Timing Specifications
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AD7888
CONFIGURATIONS SOIC TSSOP
SCLK DOUT AGND
IN/REF AGND
AD7888
VIEW
AIN1 (Not Scale) AIN8 AIN2 AIN3 AIN4
AIN7 AIN6 AIN5
FUNCTION DESCRIPTIONS
Mnemonic IN/REF
Function Chip Select. Active logic input. This input provides dual function initiating conversions AD7888 also frames serial data transfer. Reference Input/Output. on-chip reference available this external AD7888. Alternatively, internal reference disabled external reference applied this input. voltage range external reference from +1.2 VDD. Power Supply Input. range AD7888 from +2.7 +5.25 Analog Ground. Ground reference point circuitry AD7888. analog input signals external reference signals should referred this AGND voltage. Both these pins should connect AGND plane system. Analog Input through Analog Input Eight single-ended analog input channels that multiplexed into on-chip track/hold. analog input channel converted selected using ADD0 through ADD2 bits Control Register. input range input channels VREF. unused input channels should connected AGND avoid noise pickup. Data Logic Input. Data written AD7888's Control Register provided this input clocked into register rising edge SCLK (see Control Register section). Data Out. Logic Output. conversion result from AD7888 provided this output serial data stream. bits clocked falling edge SCLK input. data stream consists four leading zeros followed bits conversion data, which provided first. Serial Clock. Logic Input. SCLK provides serial clock accessing data from part writing serial data Control Register. This clock input also used clock source AD7888's conversion process.
AGND
5-12
AIN1-AIN8
DOUT
SCLK
REV.
AD7888
TERMINOLOGY Integral Nonlinearity Peak Harmonic Spurious Noise
This maximum deviation from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition, full scale, point above last code transition.
Differential Nonlinearity
Peak harmonic spurious noise defined ratio value next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, ADCs where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
This difference between measured ideal change between adjacent codes ADC.
Offset Error
This deviation first code transition 000) 001) from ideal, i.e., AGND LSB.
Offset Error Match
This difference offset error between channels.
Gain Error
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation distortion terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). AD7888 tested using CCIF standard where input frequencies near input bandwidth used. this case, second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamentals expressed dBs.
Channel-to-Channel Isolation
This deviation last code transition (111 110) (111 111) from ideal (i.e., VREF LSB) after offset error been adjusted out. Gain Error Match This difference gain error between channels.
Track/Hold Acquisition Time
track/hold amplifier returns into track mode conversion. Track/Hold acquisition time time required output track/hold amplifier reach final value, within LSB, after conversion.
Signal (Noise Distortion) Ratio
This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02 1.76) Thus 12-bit converter, this
Total Harmonic Distortion
Channel-to-channel isolation measure level crosstalk between channels. measured applying full-scale sine wave signal nonselected input channels determining much that signal attenuated selected channel. figure given worst case across four eight channels AD7888.
(Power Supply Rejection)
Variations power supply will affect full-scale transition, converter's linearity. Power supply rejection maximum change full-scale transition point change power-supply voltage from nominal value.
Total harmonic distortion (THD) ratio harmonics fundamental. AD7888, defined (dB)
where amplitude fundamental amplitudes second through sixth harmonics.
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AD7888
CONTROL REGISTER
Control Register AD7888 8-bit, write-only register. Data loaded from AD7888 rising edge SCLK. data transferred line same time conversion result read from part. This requires serial clocks every data transfer. Only information provided first rising clock edges (after falling edge) loaded Control Register. denotes first data stream. functions outlined Table default contents Control Register power-up zeros.
Table Control Register Function Description
DONTC ZERO ADD2 ADD1 ADD0
Mnemonic DONTC ZERO ADD2 ADD1 ADD0
Comment Don't Care. value written this Control Register don't care, i.e., doesn't matter zero must written this ensure correct operation AD7888. These three address bits loaded present conversion sequence select which analog input channel converted next conversion. selected input channel decoded shown Table Reference Bit. With this bit, on-chip reference enabled. With this bit, on-chip reference disabled. obtain best performance from AD7888, internal reference should disabled when using externally applied reference source. (See On-Chip Reference section.) Power Management Bits. These bits decode mode operation AD7888 shown Table III.
PM1,
PERFORMANCE CURVES
Figure shows typical plot AD7888 sample rate input frequency.
Figure shows typical plot frequency supply with external reference.
73.0
4096 POINT SAMPLING 100kSPS 10kHz 70dB
REFERENCE 72.5
72.0
71.5
-110
12.21
24.41 FREQUENCY
36.62
48.83
71.0
10.89 31.59 21.14 INPUT FREQUENCY
42.14
Figure Dynamic Performance
Figure Input Frequency
REV.
AD7888
Figure shows typical power supply rejection ratio frequency part. power supply rejection ratio defined ratio power output frequency power full-scale sine wave applied frequency PSRR (dB) (Pf/Pfs) Power frequency output, power frequency full scale input. Here peak-to-peak sine wave coupled onto supply. Both +2.7 +5.5 supply performances shown.
PSRR
CHARGE REDISTRIBUTION
AGND
SAMPLING CAPACITOR CONTROL LOGIC ACQUISITION PHASE COMPARATOR
(REF IN/REF OUT)/2
Figure Acquisition Phase
+5.5V/+2.7V 100mV SINE WAVE REFIN 2.488V REFERENCE
When starts conversion, (see Figure will open will move Position causing comparator become unbalanced. control logic charge redistribution used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. When comparator rebalanced, conversion complete. control logic generates output code. Figure shows transfer function.
CHARGE REDISTRIBUTION
2.65 12.85 23.15 43.85 33.65 INPUT FREQUENCY 54.35 64.15
SAMPLING CAPACITOR CONTROL LOGIC CONVERSION PHASE COMPARATOR
AGND
Figure PSRR Frequency
CIRCUIT INFORMATION
(REF IN/REF OUT)/2
AD7888 fast, power, 12-bit, single supply, 8channel converter. part operated from (+2.7 +3.6 supply from (+4.75 +5.25 supply. When operated from either supply supply, AD7888 capable throughput rates kSPS when provided with clock. AD7888 provides user with 8-channel multiplexer, on-chip track/hold, converter, reference serial interface housed tiny 16-lead TSSOP package, which offers user considerable space saving advantages over alternative solutions. serial clock input accesses data from part also provides clock source successive-approximation converter. analog input range VREF (where externally-applied VREF between +1.2 VDD). 8-channel multiplexer controlled part's Control Register. This Control Register also allows user power-off internal reference determine Modes Operation.
CONVERTER OPERATION
Figure Conversion Phase
TRANSFER FUNCTION
output coding AD7888 straight binary. designed code transitions occur successive integer values (i.e., LSB, LSBs, etc.). size VREF/4096. ideal transfer characteristic AD7888 shown Figure below.
111.111 111.110
CODE
111.000 1LSB VREF/4096 011.111
AD7888 successive-approximation analog-to-digital converter based around charge redistribution DAC. Figures show simplified schematics ADC. Figure shows during acquisition phase. closed Position comparator held balanced condition sampling capacitor acquires signal AIN.
000.010 000.001 000.000 0.5LSB ANALOG INPUT +VREF 1.5LSB
Figure Transfer Characteristic
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AD7888
TYPICAL CONNECTION DIAGRAM
Figure shows typical connection diagram AD7888. Both AGND pins connected analog ground plane system. VREF connected well decoupled provide analog input range VDD. conversion result output 16-bit word with four leading zeroes followed 12-bit result. applications where power consumption concern, automatic power down conversion should used improve power performance. Modes Operation section data sheet.
SUPPLY +2.7V +5.25V SERIAL INTERFACE
applications, removing high frequency components from analog input signal recommended lowpass filter relevant analog input pin. applications where harmonic distortion signal noise ratio critical analog input should driven from impedance source. Large source impedances will significantly affect performance ADC. This necessitate input buffer amplifier. choice will function particular application. When amplifier used drive analog input source impedance should limited values. maximum source impedance will depend amount total harmonic distortion (THD) that tolerated. will increase source impedance increases performance will degrade. Figure shows graph total harmonic distortion versus analog input signal frequency different source impedances.
FREQUENCY DIFFERENT SOURCE IMPEDANCES REFERENCE 100pF
AD7888
INPUT AIN1 AIN2 AIN8 AGND AGND SCLK DOUT
2.2nF
Figure Typical Connection Diagram
Analog Input
Figure shows equivalent circuit analog input structure AD7888. diodes provide protection analog inputs. Care must taken ensure that analog input signal never exceeds supply rails more than This will cause these diodes become forwardbiased start conducting current into substrate. maximum current these diodes conduct without causing irreversible damage part. However, worth noting that small amount current being conducted into substrate overvoltage unselected channel, cause inaccurate conversions selected channel. capacitor Figure typically about primarily attributed capacitance. resistor lumped component made resistance multiplexer switch. This resistor typically about capacitor sampling capacitor capacitance typically. Note: analog input capacitance seen when track hold track mode typically while hold mode typically
10nF 0.15 10.89 21.14 31.59 INPUT FREQUENCY 42.14 49.86
Figure Analog Input Frequency
Analog Input Selection
power-up, default selection AIN1. When returning normal operation from power-down, selected will same that selected prior power-down being initiated. Table below shows multiplexer address corresponding each analog input from AIN1 AIN8 AD7888.
Table Channel Configurations
ADD2
ADD1
ADD0
Analog Input Channel AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8
20pF
CONVERSION PHASE SWITCH OPEN TRACK PHASE SWITCH CLOSED
On-Chip Reference
Figure Equivalent Analog Input Circuit
AD7888 on-chip reference. This reference enabled disabled clearing setting Control Register, respectively. on-chip reference used externally system, must buffered before applied elsewhere. external reference applied device, internal reference automatically overdriven. However,
REV.
AD7888
order obtain optimum performance from device advised disable internal reference setting Control Register when external reference applied. When internal reference disabled, Figure will open input impedance seen IN/REF input impedance reference buffer, which region giga When reference enabled, input impedance seen typically
IN/REF 2.5V
only fully power again reprogram power management bits i.e., normal mode. this case device will power 16th SCLK rising edge after falling edge this when power management bits become effective. AD7888 approximate power-up time when powering from standby when using external reference. When first connected, AD7888 will fully power i.e., powers normal mode. part into shutdown, subsequent power-up will take approximately AD7888 wake-up time very short autostandby mode possible wake part carry valid conversion same read/write operation.
POWER THROUGHPUT RATE Power-Up Times
Figure On-Chip Reference Circuitry
Table III. Power Management Options
Mode Normal Operation. this mode, AD7888 remains full power mode regardless status logic inputs. This mode allows fastest possible throughput rate from AD7888. Full Shutdown. this mode, AD7888 full shutdown mode with circuitry AD7888, including on-chip reference, entering power-down mode. AD7888 retains information control Register bits while full shutdown. part remains full shutdown until these bits changed. Autoshutdown. this mode, AD7888 automatically enters full shutdown mode each conversion. Wake-up time from full shutdown user should ensure that have elapsed before attempting perform valid conversion part this mode. Autostandby. this standby mode, portions AD7888 powered down onchip reference voltage remains powered should ensure on-chip reference enabled. This mode similar autoshutdown allows part power-up much faster.
operating AD7888 autoshutdown autostandby mode average power consumption AD7888 decreases lower throughput rates. Figure shows throughput rate reduced, device remains power-down state longer average power consumption over time drops accordingly. example, AD7888 were operated continuous sampling mode, with throughput rate kSPS SCLK (VDD i.e., device autoshutdown mode on-chip reference used, power consumption calculated follows. power dissipation during normal operation (VDD power-up time remaining conversionplus-acquisition time 15.5 tSCLK, i.e., approximately 7.75 (see Figure 14a), AD7888 said dissipate 12.75 during each conversion cycle. throughput rate kSPS, cycle time average power dissipated during each cycle (12.75/100) (3.5 446.25 SCLK MHz, device again autoshutdown mode using on-chip reference, power dissipation during normal operation AD7888 said dissipate 12.75 during each conversion cycle. With throughput rate kSPS, average power dissipated during each cycle (12.75/100) (2.1 267.75 Figure shows power throughput rate automatic shutdown with both supplies.
POWER-DOWN OPTIONS
AD7888 provides flexible power management allow user achieve best power performance given throughput rate. power management options selected programming power management bits (i.e., PM0) control register. Table summarizes options available. When power management bits programmed either auto power-down modes, part will enter power-down mode 16th rising SCLK edge after falling edge first falling SCLK edge after falling edge will cause part power again. When AD7888 full shutdown, -10-
POWER
SCLK 2MHz
SCLK 2MHz
0.01 THROUGHPUT kSPS
Figure Power Throughput
REV.
AD7888
SCLK PART REMAINS POWERED TIMES
DOUT
LEADING ZEROES CONVERSION RESULT
DATA
CONTROL REGISTER DATA LOADED FIRST CLOCKS. KEEP PART THIS MODE
Figure Normal-Mode Operation
MODES OPERATION Full Shutdown (PM1
AD7888 number different modes operation. These designed provide flexible power management options. These options chosen optimize power dissipation/throughput rate ratio differing application requirements. modes operation controlled bits Control Register outlined previously.
Normal Mode (PM1
This mode intended fastest throughput rate performance user does have worry about power-up times with AD7888 remaining fully powered time. Figure shows general diagram operation AD7888 this mode. data presented AD7888 line during first eight clock cycles data transfer loaded Control Register. part will remain powered conversion long were zero write during that conversion. continue operate this mode, user must ensure that both loaded with every data transfer. falling edge initiates sequence input signal sampled second rising edge SCLK input. Sixteen serial clock cycles required complete conversion access conversion result. Once data transfer complete returned high), another conversion initiated immediately bringing again.
PART ENTERS SHUTDOWN CONVERSION
this mode, internal circuitry AD7888, including on-chip reference, powered-down. part retains information Control Register during full shutdown. part remains full shutdown until power management bits changed. power management bits changed i.e., autoshutdown mode, part will remain shutdown (now autoshutdown) will power once conversion initiated after that (see Power-Up Times section). part changes mode soon control register been updated, part full shutdown mode power management bits changed i.e., normal mode, then part will power 16th SCLK rising edge.
Autoshutdown (PM1
this mode, AD7888 automatically enters power-down mode every conversion. Figure shows general diagram operation AD7888 this mode. When goes from high low, on-chip circuitry will start power next falling edge SCLK. sixteenth SCLK rising edge part will power down again. takes approximately AD7888 internal circuitry fully powered result, conversion sample-and-hold acquisition) should initiated during this input signal sampled second rising edge SCLK following falling edge. user should ensure that elapse between first falling edge SCLK after falling edge
PART POWERS FROM SHUTDOWN SCLK FALLING EDGE
SCLK
DOUT LEADING ZEROES CONVERSION RESULT LEADING ZEROES CONVERSION RESULT
DATA
DATA
CONTROL REGISTER DATA LOADED FIRST CLOCKS.
KEEP PART THIS MODE
Figure 14a. Autoshutdown Operation
REV.
-11-
AD7888
PART ENTERS SHUTDOWN CONVERSION SCLK PART BEGINS POWERUP FROM SHUTDOWN PART REMAINS POWERED PART ENTERS SHUTDOWN CONVERSION
DOUT
LEADING ZEROES CONVERSION RESULT
LEADING ZEROES CONVERSION RESULT
LEADING ZEROES CONVERSION RESULT
DATA
DATA
DATA
CONTROL REGISTER DATA LOADED FIRST CLOCKS.
PLACE PART NORMAL MODE
PLACE PART BACK AUTOSHUTDOWN MODE
Figure 14b. Autoshutdown Operation
second rising edge SCLK shown Figure 14a. microcontroller applications, this readily achievable driving input from port lines ensuring that serial data read (from microcontrollers serial port) initiated applications, where generally derived from serial frame synchronization line, possible separate first falling edge second rising edge SCLK after falling edge Therefore, user will need write Control Register exit this mode writing part into normal mode. second conversion will then need initiated when part powered obtain conversion result shown Figure 14b.
Autostandby (PM1
this mode, AD7888 automatically enters standby sleep) mode every conversion. this standby mode, on-chip circuitry, apart from on-chip reference, powered down. This mode similar autoshutdown this case, power-up time much shorter on-chip reference remains powered times. Figure shows general diagram operation AD7888 this mode. first falling SCLK edge after goes low, AD7888 comes standby. AD7888 wake-up time very short this mode possible wake part carry valid conversion same read/ write operation. input signal sampled second rising edge SCLK following falling edge. conversion (last rising edge SCLK) part automatically enters standby mode.
PART ENTERS STANDBY CONVERSION SCLK
PART POWERS FROM STANDBY SCLK FALLING EDGE
DOUT
LEADING ZEROES CONVERSION RESULT
LEADING ZEROES CONVERSION RESULT
DATA
DATA
CONTROL REGISTER DATA LOADED FIRST CLOCKS.
KEEP PART THIS MODE
Figure Autostandby Operation
-12-
REV.
AD7888
SERIAL INTERFACE
Figure shows detailed timing diagram serial interfacing AD7888. serial clock provides conversion clock also controls transfer information from AD7888 during conversion. initiates data transfer conversion process. autoshutdown mode, first falling edge SCLK after falling edge wakes part. cases, gates serial clock AD7888 puts on-chip track/hold into track mode. input signal sampled second rising edge SCLK input after falling edge Thus, first one-half clock cycles after falling edge when acquisition input signal takes place. This time denoted acquisition time (tACQ). autoshutdown mode, acquisition time must allow wake-up time on-chip track/hold goes from track mode hold mode second rising edge SCLK conversion also initiated this edge. conversion process takes further fourteen one-half SCLK cycles complete. rising edge will back into three-state. left conversion will initiated. input channel that sampled selected previous write Control Register. Thus, user must
write ahead channel conversion. other words, user must write channel address next conversion while present conversion progress. Writing information Control Register takes place first eight rising edges SCLK data transfer. Control Register always written when data transfer takes place. user must careful always correct information line when reading data from part. Sixteen serial clock cycles required perform conversion process access data from AD7888. applications where first serial clock edge, following going low, falling edge, this edge clocks first leading zero. Thus, first rising clock edge SCLK clock first leading zero provided. applications where first serial clock edge, following going low, rising edge, first leading zero time processor read correctly. However, subsequent bits clocked falling edge SCLK they provided processor following rising edge. Thus, second leading zero clocked falling edge subsequent first rising edge. final data transfer valid 16th rising edge, having being clocked previous falling edge.
CONVERT
SCLK THREESTATE
LEADING ZEROS
DB11 DB10
DOUT
THREESTATE
DONTC ZERO ADD2 ADD1 ADD0
Figure Serial Interface Timing Diagram
REV.
-13-
AD7888
MICROPROCESSOR INTERFACING
serial interface AD7888 allows part directly connected range many different microprocessors. This section explains interface AD7888 with some more common microcontroller serial interface protocols.
AD7888 TMS320C5x
serial interface TMS320C5x uses continuous serial clock frame synchronization signals synchronize data transfer operations with peripheral devices like AD7888. input allows easy interfacing with inverter between serial clock TMS320C5x AD7888 being only glue logic required. serial port TMS320C5x operate burst mode with internal CLKX serial clock) frame sync). serial port control register (SPC) must have following setup: connection diagram shown Figure
AD7888*
SCLK
Timer Registers, etc., loaded with value that will provide interrupt required sample interval. When interrupt received, value transmitted with TFS/DT (ADC control word). used control hence reading data. frequency serial clock SCLKDIV Register. When instruction transmit with given, (i.e., TX0), state SCLK checked. will wait until SCLK gone high, high before transmission will start. timer SCLK values chosen such that instruction transmit occurs near rising edge SCLK, data transmitted wait until next clock edge. example, ADSP-2111 master clock frequency MHz. SCLKDIV Register loaded with value SCLK obtained, eight master clock periods will elapse every SCLK period. timer registers loaded with value 803, then 100.5 SCLKs will occur between interrupts subsequently between transmit instructions. situation will result nonequidistant sampling transmit instruction occurring SCLK edge. number SCLKs between interrupts figure N.5, equidistant sampling will implemented DSP.
AD7888*
SCLK DOUT
TMS320C5x*
CLKX CLKR
DOUT
ADSP-21xx*
SCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing TMS320C5x
AD7888 ADSP-21xx
ADSP-21xx family DSPs interfaced AD7888 with inverter between serial clock ADSP-21xx AD7888. This only glue logic required. SPORT control register should follows: TFSW RFSW Alternate Framing INVRFS INVTFS Active Frame Signal DTYPE Right Justify Data SLEN 1111, 16-Bit Data Words ISCLK Internal Serial Clock TFSR RFSR Frame Every Word IRFS ITFS connection diagram shown Figure ADSP21xx SPORT tied together with output input. operated Alternate Framing Mode SPORT Control Register described. frame synchronization signal generated tied and, with signal processing applications, equidistant sampling necessary. However, this example timer interrupt used control sampling rate and, under certain conditions, equidistant sampling achieved.
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing ADSP-21xx
AD7888 DSP56xxx
connection diagram Figure shows AD7888 connected (Synchronous Serial Interface) DSP56xxx family DSPs from Motorola. operated synchronous mode (SYN with internally generated 1-bit clock period frame sync both (bits FSL1 FSL0 CRB). word length setting bits CRA. inverter also necessary between SCLK from DSP56xxx SCLK AD7888 shown Figure
AD7888*
SCLK DOUT
DSP56xxx*
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing DSP56xxx
-14-
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AD7888
AD7888 MC68HC11
Serial Peripheral Interface (SPI) MC68HC11 configured Master Mode (MSTR Clock Polarity (CPOL) Clock Phase (CPHA) configured writing Control Register (SPCR)-see 68HC11 User Manual. serial transfer will take place 8-bit operations. connection diagram shown Figure
MC68HC11*
SCLK/PD4 MISO/PD2 MOSI/PD3
APPLICATION HINTS Grounding Layout
AD7888 very good immunity noise power supplies seen PSRR Frequency graph. However, care should still taken with regard grounding layout. printed circuit board that houses AD7888 should designed analog digital sections separated confined certain areas board. This facilitates ground planes that easily separated. minimum etch technique generally best ground planes gives best shielding. Digital analog ground planes should joined only place. Both AGND pins AD7888 should sunk AGND plane. AGND plane DGND plane connection should made point only, star ground point that should established close possible AGND AD7888. Avoid running digital lines under device these will couple noise onto die. analog ground plane should allowed under AD7888 avoid noise coupling. power supply lines AD7888 should large trace possible provide impedance paths reduce effects glitches power supply line. Fast switching signals like clocks should shielded with digital ground avoid radiating noise other sections board, clock signals should never near analog inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough through board. microstrip technique best always possible with double-sided board. this technique, component side board dedicated ground planes while signals placed solder side. Good decoupling also important. analog supplies should decoupled with tantalum parallel with capacitors AGND. achieve best from these decoupling components, they must placed close possible device, ideally right against device.
Evaluating AD7888 Performance
AD7888*
SCLK DOUT
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing MC68HC11
AD7888 8051
possible implement serial interface using data ports 8051. This allows full duplex serial transfer implemented. technique involves "bit-banging" port (e.g., P1.0) generate serial clock using other ports (e.g., P1.1 P1.2) shift data out-see Figure
AD7888*
SCLK DOUT P1.0 P1.1 P1.2 P1.3
8051*
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing 8051 Using Ports
AD7888 PIC16C6x/7x
PIC16C6x Synchronous Serial Port (SSP) configured Master with Clock Polarity This done writing Synchronous Serial Port Control Register (SSPCON). user PIC16/17 Microcontroller User Manual. Figure shows hardware connections needed interface PIC16/17. this example port being used pulse This microcontroller only transfers eight bits data during each serial transfer operation. Therefore, consecutive read/write operations needed.
AD7888*
SCLK DOUT
recommended layout AD7888 outlined evaluation board AD7888. evaluation board package includes fully assembled tested evaluation board, documentation, software controlling board from EVAL-CONTROL BOARD. EVAL-CONTROL BOARD used conjunction with AD7888 evaluation board, well many other Analog Devices evaluation boards ending designator, demonstrate/evaluate performance AD7888. software allows user perform (fast Fourier transform) (histogram codes) tests AD7888.
PIC16C6x/7x*
SCK/RC3 SDO/RC5 SDI/RC4
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing PIC16C6x/17x
REV.
-15-
AD7888
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Lead Small Outline (SOIC) (R-16A)
C3450-8-2/99
0.0196 (0.50) 0.0099 (0.25) 0.0500 (1.27) 0.0160 (0.41) 0.3937 (10.00) 0.3859 (9.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0500 SEATING (1.27) PLANE
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
16-Lead Thin Shrink Small Outline (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) 0.0118 (0.30) 0.0075 (0.19)
0.256 (6.50) 0.246 (6.25)
0.0256 SEATING (0.65) PLANE
0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-16-
REV.
PRINTED U.S.A.
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