1999, ver. Introduction time-to-market pressures increase, d

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In-System Programmability Guidelines
1999, ver.
Introduction
time-to-market pressures increase, design engineers require advanced system-level products ensure problem-free development manufacturing. Programmable logic devices (PLDs) with in-system programmability (ISP) help accelerate development time, facilitate in-field upgrades, simplify manufacturing flow, lower inventory costs, improve printed circuit board (PCB) testing capabilities. Altera® ISP-capable devices programmed reprogrammed in-system IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. This interface allows devices programmed functionally tested single manufacturing step, saving testing time assembly costs. This application note describes guidelines should follow design successfully with ISP, including:
General Guidelines IEEE Std. 1149.1 Signals Sequential Concurrent Programming Troubleshooting Guidelines Embedded Processors In-Circuit Testers
General Guidelines
This section provides guidelines that will help design successfully ISP-capable devices. These guidelines should used regardless your specific design implementation.
Operating Conditions
Each Altera device several parametric ratings, operating conditions, that required proper operation. Although Altera devices exceed these conditions when user mode still operate correctly, these conditions should exceeded during in-system programming. Violating operating conditions during in-system programming result programming failures incorrectly programmed devices.
Altera Corporation
A-AN-100-03
100: In-System Programmability Guidelines
VCCISP Voltage
Altera ISP-capable devices have specification called VCCISP. VCCISP level must maintained VCCINT pins (i.e., VCCINT VCCISP) during in-system programming ensure that device's EEPROM cells programmed correctly. VCCISP specification applies both commercial- industrial-temperaturegrade devices. Because power consumption during in-system programming exceed power consumption during user mode, need adjust your in-system programming setup maintain correct voltage levels during both modes. Altera recommends that test VCCISP levels device's VCCINT pins using oscilloscope. First, test VCCISP levels with oscilloscope's trigger level minimum level listed recommended operating conditions table appropriate device family data sheet. Measure voltage between VCCINT ground, probed pins device. Then, repeat this test with oscilloscope's trigger level maximum level listed recommended operating conditions table. oscilloscope triggered either voltage level, should adjust your programming setup.
Input Voltages
Each device family data sheet lists device input voltage specifications absolute maximum ratings recommended operating conditions tables. input voltages absolute maximum ratings tables refer voltages beyond which device risks permanent damage. example, MAX® 9000 devices have maximum input voltage minimum input voltage -2.0 recommended operating conditions tables specify voltage range safe device operation. devices operate safely with input voltages between (ground (VCCINT with input currents Make sure pins that transition during in-system programming have ground overshoot. Overshoot problems typically occur free-running clocks data buses that toggle during in-system programming. pins that have overshoot greater than must have series termination.
more information operating conditions termination, Operating Requirements Altera Devices Data Sheet Application Note (High-Speed Board Designs), respectively.
Altera Corporation
100: In-System Programmability Guidelines
Interrupting In-System Programming
Altera does recommend interrupting programming process because partially programmed devices operate unpredictably. Partially programmed devices also cause signal conflicts, which lead permanent device damage affect proper operation other devices board.
MultiVolt Devices Power-Up Sequences
JTAG circuitry operate correctly during in-system programming boundary-scan testing, devices JTAG chain must same state. Therefore, systems with multiple power supply voltages, JTAG pins must held test-logic-reset state until devices chain completely powered This procedure particularly important because systems with multiple power supplies cannot power voltage levels simultaneously. Altera devices with MultiVoltfeature power supply voltages: VCCINT VCCIO. VCCINT provides power JTAG circuitry; VCCIO provides power output drivers pins, including TDO. Therefore, when these devices power supply voltages, JTAG circuitry must held test-logic-reset state until both power supplies turned JTAG pins held test-logic-reset state, in-system programming errors occur.
VCCINT Powered before VCCIO
VCCINT powered before VCCIO, JTAG circuitry active unable drive signals out. Thus, transition cause state machine transition unknown JTAG state. connected VCCIO VCCIO powered JTAG signals left floating. These floating values cause device transition unintended JTAG states, leading incorrect operation when VCCIO finally powered Therefore, JTAG signals must disabled described "Disabling IEEE Std. 1149.1 Circuitry" page
VCCIO Powered before VCCINT
VCCIO powered before VCCINT, JTAG circuitry active tri-stated. Even though JTAG circuitry active, next device JTAG chain powered with same trace VCCIO, JTAG circuitry must stay test-logic-reset state. Because signals common, they must disabled devices chain. Therefore, JTAG pins must disabled pulling low.
Altera Corporation
100: In-System Programmability Guidelines
Pins Tri-Stated during In-System Programming
device pins tri-stated during in-system programming. addition, 7000S, 7000A, 7000AE, 7000B, 3000A devices have weak pull-up resistor. purpose this weak pull-up resistor eliminate need external pull-ups unused pins. value this pull-up resistor listed individual device family data sheets. Sufficient pull-up pull-down resistors must added signals that require particular value during in-system programming (e.g., output enable chip enable signals). pull-up pull-down resistor added, device could have high current during in-system programming (caused conflicts board), in-system programming failures with either unrecognized device verify errors, power-up after in-system programming fails.
IEEE Std. 1149.1 Signals
This section provides guidelines programming with IEEE Std. 1149.1 (JTAG) interface.
Signal
Most in-system programming failures caused noisy signal. Noisy transitions rising falling edges cause incorrect clocking IEEE Std. 1149.1 Test Access Port (TAP) controller. Incorrect clocking cause state machine transition unknown state, leading in-system programming failures. Further, because signal must drive IEEE Std. 1149.1 devices chain parallel, signal have high fan-out. Like other high fan-out user-mode clock, must manage clock tree maintain signal integrity. Typical errors that result from clock integrity problems invalid messages, blank-check errors, verification errors. Altera recommends pulling signal through resistor. Typical resistor values depending amount current being consumed number devices board. Fast edges combined with board inductance cause overshoot problems. When this combination occurs, must either reduce inductance trace reduce switching rate selecting transistor-to-transistor logic (TTL) driver chip with slower slew rate. Altera does recommend using resistor capacitor (RC) networks slow down edge rates, because they violate device's input specifications. most cases, using driver chip prevents edge rate from being slow. Altera recommends using driver chips that glitch upon power-up.
Altera Corporation
100: In-System Programmability Guidelines
Programming Download Cable
using MasterBlasterTM, ByteBlasterMVTM, ByteBlasterTM, BitBlasterdownload cable your JTAG chain contains three more devices, Altera recommends adding buffer chain. should select buffer with slow transitions minimize noise. must extend download cable, attach standard parallel serial port cable download cable. extend 10-pin header portion download cable; extending this portion cable cause noise in-system programming problems.
more information using MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables, MasterBlaster Serial/USB Communications Cable Data Sheet, ByteBlasterMV Parallel Port Download Cable Data Sheet, ByteBlaster Parallel Port Download Cable Data Sheet, BitBlaster Serial Download Cable Data Sheet.
Disabling IEEE Std. 1149.1 Circuitry
your design does boundary-scan test (BST) circuitry, Altera recommends disabling IEEE Std. 1149.1 circuitry. Table summarizes disable IEEE Std. 1149.1 circuitry when use.
Table Disabling IEEE Std. 1149.1 Circuitry
Devices Permanently Disabled Enabled BST, Disabled During User Mode
Either pull high low, pull high before pulling high.
7000S MAX+PLUS® 7000B software, turn Enable 7000A JTAG Support option. 7000AE 3000A 9000 9000A Either pull high low, pull high before pulling high.
Either pull high low, pull high before pulling high.
Notes:
Information 7000B, 7000A, 7000AE, 3000A devices preliminary. Typical pull-up resistor values This value vary depending amount current being consumed number devices board.
Altera Corporation
100: In-System Programmability Guidelines
JTAG Permanently Disabled (MAX 7000S, 7000B, 7000A, 7000AE 3000A Devices)
7000S, 7000B, 7000A, 7000AE, 3000A device JTAG pins used either JTAG ports pins. should specify pins will used before compiling your design MAX+PLUS software turning Enable JTAG Support option off. When Enable JTAG Support option turned pins JTAG ports in-system programming boundary-scan testing; when Enable JTAG Support option turned off, pins pins cannot perform in-system programming boundary-scan testing.
more information disable JTAG circuitry using MAX+PLUS software, search "Classic Global Project Device Options Dialog Box" "Classic Individual Device Options Dialog Box" MAX+PLUS Help.
JTAG Permanently Disabled (MAX 9000 9000A Devices)
JTAG circuitry always enabled 9000 9000A devices because they have dedicated JTAG pins circuitry. Therefore, plan circuitry, disable circuitry through JTAG pins. disable JTAG, JTAG specification instructs pull high does explain what with TCK. Altera recommends pulling high low. Pulling ensures that rising edge does occur during power-up sequence. pull high, must first pull high. Pulling high first ensures that rising edge edges cause JTAG state machine leave test-logic-reset state.
JTAG Enabled ISP/BST Disabled User Mode
Altera ISP-capable devices that JTAG either in-system programming boundary-scan testing, JTAG circuitry must enabled during disabled other times. control JTAG operation through JTAG pins. permanently disable JTAG circuitry 9000 devices, either pull high low, pull high before pulling high.
Altera Corporation
100: In-System Programmability Guidelines
Working with Different Voltage Levels
When devices JTAG chain operate different voltage levels, device's output voltage specification must meet subsequent device's input voltage specification. devices meet this criteria, must additional circuitry, such level-shifter, adjust voltage levels. example, when 5.0-V device drives 2.5-V device, must adjust 5.0-V device's output voltage meet 2.5-V device's input voltage specification. Because devices JTAG chain tied together, must also ensure that first device's output meets subsequent device's input voltage specification program chain devices successfully. Altera ISP-capable devices include MultiVolt feature, which allows these devices interface with systems that have different supply voltages. 5.0-V MultiVolt devices 3.3-V 5.0-V operation. 3.3-V MultiVolt devices 2.5-V, 3.3-V, 5.0-V operation.
Sequential Concurrent Programming
This section describes program multiple devices using sequential concurrent programming. more information sequential concurrent programming, Product Information Bulletin (Concurrent Programming through JTAG Interface Devices).
Sequential Programming
Sequential programming process programming multiple devices chain device time. After first device chain finished being programmed, next device programmed. This sequence continues until specified devices JTAG chain programmed. After device programmed, uses JTAG BYPASS instruction pass data subsequent devices chain. However, device loaded with JTAG BYPASS instruction will, definition, operate normal user mode.
Altera Corporation
100: In-System Programmability Guidelines
Concurrent Programming
Concurrent programming used program devices from same family parallel. time required program multiple devices concurrently only slightly longer than time required "burn" data into largest device's EEPROM FLASH cells, resulting considerably faster programming times than sequential programming. Higher clock rates shifting data result even greater time savings. However, using parallel port rather than serial port transfer data greatly reduces time savings because serial ports have limited bandwidth. Because FLEX® devices SRAM-based, they "burn" data thus support serial configuration only.
Selecting Sequential Concurrent Programming
When programming using Programmer Object File (.pof) MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cable, sequential programming selected automatically. When using JamFile (.jam) Serial Vector Format (.svf) File, devices programmed configured following order: FLEX devices sequentially APEX20K devices sequentially 7000S 7000A devices concurrently 7000AE 3000A devices concurrently EPC2 devices sequentially 9000 devices concurrently
perform sequential programming with File create individual files each device. this scheme, FLEX APEX devices will begin configuration until click Configure button MAX+PLUS Programmer.
Devices Different Modes
Errors occur some devices chain operational while others still being programmed. this reason, 7000S, 7000A, 7000AE, 7000B, 3000A devices special instruction that prevents devices from entering normal operation until devices chain finish in-system programming. this mode, these devices pass boundary-scan data synchronously wait other devices same family complete programming before beginning operation. Thus, these devices begin operation simultaneously. APEX 20K, FLEX 10K, 9000, 9000A devices currently support this mode. These devices held tri-state mode programming software until device families have been programmed configured.
Altera Corporation
100: In-System Programmability Guidelines
Troubleshooting Guidelines
This section provides tips troubleshooting ISP-related problems.
Invalid Unrecognized Device Messages
first step during in-system programming check device's silicon silicon does match, Invalid Unrecognize Device error generated. Typical causes this error shown below:
Download cable connected incorrectly connected Incomplete JTAG chain Noisy signal Player ported incorrectly
Download Cable Connected Incorrectly
will receive error download cable connected incorrectly parallel port receiving power from your board.
more information installing MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cable, MasterBlaster Serial/USB Communications Cable Data Sheet, ByteBlasterMV Parallel Port Download Cable Data Sheet, ByteBlaster Parallel Port Download Cable Data Sheet, BitBlaster Serial Download Cable Data Sheet.
Connected
will receive error port device chain connected. During in-system programming, data must shifted each device JTAG chain through JTAG pins. Therefore, each device's port must connected subsequent device's port, last device's port must connected download cable's port.
Incomplete JTAG Chain
will receive error JTAG chain complete. check incomplete JTAG chain causing error, oscilloscope monitor vectors coming each device chain. each device's port does toggle during in-system programming, your JTAG chain complete.
Altera Corporation
100: In-System Programmability Guidelines
Noisy Signal
Noise signal most common reason in-system programming errors. Noisy transitions rising falling edges cause incorrect clocking IEEE Std. 1149.1 controller, causing state machine lost in-system programming fail. more information dealing with noisy signals, "TCK Signal" page
Player Ported Incorrectly
will receive error Player ported correctly your platform. check Player causing error, apply IDCODE instruction target device using File. File load IDCODE instruction then shift IDCODE value. This test determines JTAG chain correctly read write JTAG chain properly. Figure page shows sample file read IDCODE.
Troubleshooting Tips
This section discusses some additional suggestions troubleshooting issues.
Verify JTAG Chain Continuity
in-system programming occur successfully, number devices physically JTAG chain must match number reported MAX+PLUS software. following steps show simple verify that JTAG chain connected properly. MAX+PLUS Programmer, choose Multi-Device JTAG Chain Setup. Multi-Device JTAG Chain Setup dialog box, click Detect JTAG Chain Info button. MAX+PLUS software reports many devices found JTAG chain.
Check Level Board During In-System Programming
Using oscilloscope, monitor VCCINT signal your JTAG chain trigger minimum level listed recommended operating conditions table appropriate device family data sheet. trigger occurs during in-system programming, devices need more current than being supplied existing power supply. replacing existing power supply with that provides more current.
Altera Corporation
100: In-System Programmability Guidelines
Power-Up Problems
Excessive voltage current pins during power-up cause devices JTAG chain experience latch-up. Check devices touch; devices have probably experienced latch-up have been damaged. this situation, check voltage sources make sure that excessive voltage current being into device. Then, replace affected device programming again.
Random Signals JTAG Pins
During normal operation, each device's controller must test-logic-reset state. force device back into this state, pulling signal high pulsing clock signal times. device then powers-up successfully, must higher pull-down resistor signal.
Software Issues
Failures during in-system programming occasionally related MAX+PLUS software. software-related issues documented Altera Technical Support (AtlasSM) section Altera site http://www.altera.com. Simply search Atlas database information relating software issues that interfere with in-system programming.
Embedded Processors
This section provides guidelines programming ISP-capable devices using programming test language embedded processor.
Processor Memory Requirements
Byte-Code Player supports 8-bit higher processors; ASCII Player supports 16-bit higher processors. Player uses memory predictable manner, which simplifies in-field upgrades confining updates File. Player memory uses both dynamic memory (RAM). used store Player binary File; dynamic memory used when Player called.
information estimate maximum amount required Player, Application Note (Using Language Embedded Processor).
Altera Corporation
100: In-System Programmability Guidelines
Porting Player
Altera Player (both Byte-Code ASCII versions) works with parallel port. port Player your processor, only need modify jamstub.c jbistub.c file (for ASCII Player Byte-Code Player, respectively). other files should remain same. Player ported incorrectly, Unrecognized Device error generated. most common causes this error listed below:
After porting Player, value read reversed polarity. This problem occur because default code Player assumes parallel port. Refer Player readme.txt file Altera Digital Library CD-ROM more detailed information solve problem. Although signals clocked rising edge TCK, outputs change until falling edge TCK. This situation causes half clock cycle reading values. transition expected rising edge, data appears offset clock. Altera recommends using registers synchronize output transitions. addition, some processor data ports register synchronize output signals. example, reading writing PC's parallel port accomplished reading writing registers. these registers must taken into consideration when reading writing JTAG chain. Incorrect accounting these registers cause values either lead expected value.
test File determine Player ported correctly. Figure shows sample File that helps debug potential porting problems, including three issues discussed previously. download this example file from literature page Altera's site http://www.altera.com.
Altera Corporation
100: In-System Programmability Guidelines
Figure Sample File Debugging Porting Problems (Part
NOTE JAM_VERSION "1.1 NOTE DESIGN "IDCODE.jam version 4/28/98"; '#This File compares IDCODE read from JTAG chain with '#expected IDCODE. There parameters that when executing '#this code. '#COMP_IDCODE_[device #]=1, example -dCOMP_IDCODE_9400=1 '#compares IDCODE with EPM9400 IDCODE. '#PRE_IR=[IR_LENGTH] length instruction registers want '#to bypass after target device. default your '#JTAG length don't need enter value. '#POST_IR=[IR_LENGTH] length instruction registers '#want bypass before target device. default '#your JTAG length don't need enter value. '#PRE_DR=[DR_LENGTH] length data registers want '#to bypass after target device. default your '#JTAG length don't need enter value. '#POST_DR=[DR_LENGTH] length data registers want '#to bypass before target device. default your '#JTAG length don't need enter value. '#Example: This example reads IDCODE second device '#chain below: '#TDI EPM7128S EPM7064S EPM7256S EPM7256S '#In this example, IDCODE compared EPM7064S IDCODE. JTAG '#chain properly, IDCODEs should match. C:\> -dCOMP_IDCODE_7064S=1 -dPRE_IR=20 -dPOST_IR=10 -dPRE_DR=2 '#-dPOST_DR=1 -p378 IDCODE.jam Example: This example reads IDCODE single device JTAG chain compares EPM9480 IDCODE: C:\> -dCOMP_IDCODE_9480=1 -p378 IDCODE.jam '######################### Initialization ######################## BOOLEAN BOOLEAN BOOLEAN BOOLEAN read_data[32]; I_IDCODE[10] 1001101000; I_ONES[10] 1111111111; ONES_DATA[32]= FFFFFFFF;
Altera Corporation
100: In-System Programmability Guidelines
Figure Sample File Debugging Porting Problems (Part
BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN INTEGER INTEGER INTEGER INTEGER BOOLEAN BOOLEAN BOOLEAN BOOLEAN ID_9320[32] ID_9400[32] ID_9480[32] ID_9560[32] ID_7032S[32] ID_7064S[32] ID_7128S[32] ID_7128A[32] ID_7160S[32] ID_7192S[32] ID_7256S[32] ID_7256A[32] COMP_9320_IDCODE COMP_9400_IDCODE COMP_9480_IDCODE COMP_9560_IDCODE COMP_7032S_IDCODE COMP_7064S_IDCODE COMP_7096S_IDCODE COMP_7128S_IDCODE COMP_7128A_IDCODE COMP_7160S_IDCODE COMP_7192S_IDCODE COMP_7256S_IDCODE COMP_7256A_IDCODE COMP_7032AE_IDCODE COMP_7064AE_IDCODE COMP_7128AE_IDCODE COMP_7256AE_IDCODE COMP_7512AE_IDCODE PRE_IR PRE_DR POST_IR POST_DR SET_ID_EXPECTED[32]; COMPARE_FLAG1 COMPARE_FLAG2 COMPARE_FLAG
This information what expected shifted instruction register BOOLEAN expected_data[10] 0101010101; BOOLEAN ir_data[10];
Altera Corporation
100: In-System Programmability Guidelines
Figure Sample File Debugging Porting Problems (Part
These values default have single device JTAG chain, have these values. PREIR PRE_IR; POSTIR POST_IR; PREDR PRE_DR; POSTDR POST_DR; INTEGER ######################### Determine Action ######################## COMPARE_FLAG1= COMP_9320_IDCODE COMP_9400_IDCODE COMP_9480_IDCODE COMP_9560_IDCODE COMP_7032S_IDCODE COMP_7064S_IDCODE COMP_7096S_IDCODE COMP_7032AE_IDCODE COMP_7064AE_IDCODE COMP_7128AE_IDCODE; COMPARE_FLAG2 COMP_7128S_IDCODE COMP_7128A_IDCODE COMP_7160S_IDCODE COMP_7192S_IDCODE COMP_7256S_IDCODE COMP_7256A_IDCODE COMP_7256AE_IDCODE COMP_7512AE_IDCODE; COMPARE_FLAG COMPARE_FLAG1 COMPARE_FLAG2; COMPARE_FLAG THEN GOTO NO_OP; COMP_9320_IDCODE COMP_9400_IDCODE COMP_9480_IDCODE COMP_9560_IDCODE COMP_7032S_IDCODE COMP_7064S_IDCODE COMP_7128S_IDCODE COMP_7128A_IDCODE COMP_7160S_IDCODE COMP_7192S_IDCODE COMP_7256S_IDCODE COMP_7256A_IDCODE COMP_7032AE_IDCODE COMP_7064AE_IDCODE COMP_7128AE_IDCODE COMP_7256AE_IDCODE COMP_7512AE_IDCODE
THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN THEN
SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i] SET_ID_EXPECTED[i]
ID_9320[i]; ID_9400[i]; ID_9480[i]; ID_9560[i]; ID_7032S[i]; ID_7064S[i]; ID_7128S[i]; ID_7128A[i]; ID_7160S[i]; ID_7192S[i]; ID_7256S[i]; ID_7256A[i]; ID_7032AE[i]; ID_7064AE[i]; ID_7128AE[i]; ID_7256AE[i]; ID_7512AE[i];
NEXT
Altera Corporation
100: In-System Programmability Guidelines
Figure Sample File Debugging Porting Problems (Part
######################### Actual Loading ######################## IRSTOP IRPAUSE; STATE RESET; IRSCAN I_IDCODE[0.9], CAPTURE ir_data[0.9]; STATE IDLE; DRSCAN ONES_DATA[0.31], CAPTURE read_data[0.31]; ######################### Printing ######################## PRINT "EXPECTED IRSCAN 1010101010"; PRINT "ACTUAL IRSCAN: ",ir_data[0], ir_data[1], ir_data[2], ir_data[3], ir_data[4], ir_data[5], ir_data[6], ir_data[7], ir_data[8], ir_data[9]; PRINT "";PRINT "EXPECTED IDCODE SET_ID_EXPECTED[0], SET_ID_EXPECTED[1], SET_ID_EXPECTED[2], SET_ID_EXPECTED[3], SET_ID_EXPECTED[4], SET_ID_EXPECTED[5], SET_ID_EXPECTED[6], SET_ID_EXPECTED[7], SET_ID_EXPECTED[8], SET_ID_EXPECTED[9], SET_ID_EXPECTED[10], SET_ID_EXPECTED[11], SET_ID_EXPECTED[12], SET_ID_EXPECTED[13], SET_ID_EXPECTED[14], SET_ID_EXPECTED[15], SET_ID_EXPECTED[16], SET_ID_EXPECTED[17], SET_ID_EXPECTED[18], SET_ID_EXPECTED[19], SET_ID_EXPECTED[20], SET_ID_EXPECTED[21], SET_ID_EXPECTED[22], SET_ID_EXPECTED[23], SET_ID_EXPECTED[24], SET_ID_EXPECTED[25], SET_ID_EXPECTED[26], SET_ID_EXPECTED[27], SET_ID_EXPECTED[28], SET_ID_EXPECTED[29], SET_ID_EXPECTED[30], SET_ID_EXPECTED[31]; PRINT "ACTUAL IDCODE READ_DATA[0], READ_DATA[1], READ_DATA[2], READ_DATA[3], READ_DATA[4], READ_DATA[5], READ_DATA[6], READ_DATA[7], READ_DATA[8], READ_DATA[9], READ_DATA[10], READ_DATA[11], READ_DATA[12], READ_DATA[13], READ_DATA[14], READ_DATA[15], READ_DATA[16], READ_DATA[17], READ_DATA[18], READ_DATA[19], READ_DATA[20], READ_DATA[21], READ_DATA[22], READ_DATA[23], READ_DATA[24], READ_DATA[25], READ_DATA[26], READ_DATA[27], READ_DATA[28], READ_DATA[29], READ_DATA[30], READ_DATA[31]; GOTO END;
Altera Corporation
100: In-System Programmability Guidelines
Figure Sample File Debugging Porting Problems (Part
######################### parameters ######################## NO_OP: PRINT "jam [-d<var=val>] [-p<port>] [-s<port>] IDCODE.jam"; PRINT initialize variable specified value"; PRINT parallel port number address <for ByteBlaster>"; PRINT serial port name <for BitBlaster>"; PRINT PRINT "Example: compare IDCODE device chain Altera PRINT "devices with EPM7192S IDCODE"; PRINT PRINT "jam -dCOMP_7192S_IDCODE=1 -dPRE_IR=10 -dPOST_IR=30 -dPRE_DR=1"; PRINT "dPOST_DR=3 -p378 IDCODE.jam"; PRINT END: EXIT
In-Circuit Testers
This section addresses specific issues associated with programming ISP-capable devices in-circuit testers.
Using Non-"F" Devices
devices either fixed algorithms ("F") branching algorithms (non-"F"). Most in-circuit tester file formats, e.g., SVF, Hewlett-Packard's Pattern Capture Format (.pcf), DTS, ASC, "fixed" deterministic, which means they only support fixed algorithm without branching. MAX+PLUS software generates Files devices. Because algorithms Files constant, always these files program future devices. Altera does recommend programming non-"F" devices in-circuit testers. Non-"F" devices require branching based three variables read from device: programming pulse time, erase pulse time, manufacturer silicon These three variables programmed into non-"F" Altera devices. Using only devices eliminates problems experience these variables change.
Altera Corporation
100: In-System Programmability Guidelines
Maximum Vectors File
file formats "bed nails" in-circuit testers generally require very large vector files in-system programming. When file larger than tester's available memory, file must divided into smaller files. example, Altera's svf2pcf utility automatically divides single File into several smaller files. addition, utility allows users either specify maximum number vectors file default value. many vectors single file, error message occurs. receive this error, simply reduce number vectors file.
Pull-Up Pull-Down Resistors
Testers require pull-up pull-down resistors various signal traces. Contact in-circuit tester manufacturer directly specific information.
Summary
information provided this document based development experiences customer issues resolved Altera. more information resolving in-system programming problems, contact Altera Applications (800) 800-3753, e-mail sos@altera.com. Twenty-four hour support available through Atlas section Altera site http://www.altera.com.
Altera Corporation
100: In-System Programmability Guidelines
Notes:
Altera Corporation
100: In-System Programmability Guidelines
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, Atlas, APEX, APEX 20K, FLEX, FLEX 10K, MAX, MAX+PLUS, MAX+PLUS 9000, 9000A, 7000S, 7000B, 7000A, 7000AE, 3000A, MasterBlaster, BitBlaster, ByteBlaster, ByteBlasterMV, EPM7128S, EPM7256S, EPM7064S, EPM9400, EPM9480, trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
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1999, ver. Introduction time-to-market pressures increase, d

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