Dual MSPS, 12-Bit, 2-Channel with Serial Interface AD7866 VREF DC

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Dual MSPS, 12-Bit, 2-Channel with Serial Interface AD7866 VREF DC

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FEATURES Dual 12-Bit, 2-Channel Fast Throughput Rate MSPS Specified 5.25 Power 11.4 MSPS with Supplies MSPS with Supplies Wide Input Bandwidth Input Frequency Onboard Reference Flexible Power/Throughput Rate Management Simultaneous Conversion/Read Pipeline Delays High-Speed Serial Interface TM/QSPITM/ MICROWIRE TM/DSP Compatible Shut-Down Mode 20-Lead TSSOP Package
Dual MSPS, 12-Bit, 2-Channel with Serial Interface AD7866
VREF DCAPA SELECT AVDD DVDD 2.5V 12-BIT SUCCESSIVEAPPROXIMATION
AD7866
OUTPUT DRIVERS DOUTA
CONTROL LOGIC
RANGE SCLK VDRIVE
12-BIT SUCCESSIVEAPPROXIMATION
OUTPUT DRIVERS
DOUT
AGND
AGND
DCAPB
DGND
GENERAL DESCRIPTION
AD7866 dual 12-bit high-speed, power, successiveapproximation ADC. part operates from single 5.25 power supply features throughput rates MSPS. device contains ADCs, each preceded low-noise, wide bandwidth track/hold amplifier which handle input frequencies excess MHz. conversion process data acquisition controlled using standard control inputs allowing easy interfacing microprocessors DSPs. input signal sampled falling edge conversion also initiated this point. conversion time determined SCLK frequency. There pipelined delays associated with part. AD7866 uses advanced design techniques achieve very power dissipation high throughput rates. With supplies MSPS throughput rate, part consumes maximum With supplies MSPS, current consumption maximum part also offers flexible power/ throughput rate management when operating sleep mode. analog input range part selected VREF range VREF range with either straight binary two's complement output coding. AD7866 on-chip reference which overdriven external
reference preferred. Each on-board also supplied with separate individual external reference. AD7866 available 20-lead thin shrink small outline (TSSOP) package.
PRODUCT HIGHLIGHTS
AD7866 features complete functions allowing simultaneous sampling conversion channels. Each 2-channel input multiplexer. conversion result both channels available simultaneously separate data lines, both taken data line only serial port available. High Throughput with Power Consumption-The AD7866 offers MSPS throughput rate with 11.4 maximum power consumption when operating Flexible Power/Throughput Rate Management-The conversion rate determined serial clock allowing power consumption reduced conversion time reduced through SCLK frequency increase. Power efficiency maximized lower throughput rates part enters sleep during conversions. Pipeline Delay-The part features standard successiveapproximation ADCs with accurate control sampling instant input once conversion control.
QSPI trademarks Motorola Inc. MICROWIRE trademark National Semiconductor Corporation.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
AD7866-SPECIFICATIONS1 External
MAX,
CAPA
5.25 VDRIVE 5.25 Reference DCAPB, fSCLK MHz, unless otherwise noted.)
Unit Bits min/V min/V ppm/°C -VREF +VREF Biased about VREF with Two's Complement Output Coding Test Conditions/Comments Sine Wave, MSPS Sine Wave, MSPS Sine Wave, MSPS
Parameter DYNAMIC PERFORMANCE Signal Noise Distortion (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Channel Channel Isolation SAMPLE HOLD Aperture Delay3 Aperture Jitter3 Aperture Delay Matching3 Full Power Bandwidth ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity VREF Input Range Offset Error Offset Error Match Gain Error Gain Error Match VREF Input Range Positive Gain Error Zero Code Error Zero Code Error Match Negative Gain Error ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT Reference Input Voltage Reference Input Voltage Range4 Leakage Current Input Capacitance Reference Output Voltage5 VREF Output Impedance6 Reference Temperature Coefficient Error (TMIN TMAX) LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, Output Voltage, Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding
Version1
Version1
-0.95/+1.25 -0.95/+1.25 VREF VREF 2.45/2.55 VDRIVE VDRIVE
Grade, VREF range only; ±0.5 VREF range; Guaranteed Missed Codes Bits Straight Binary Output Coding
VREF VREF 2.45/2.55 VDRIVE VDRIVE
RANGE upon Falling Edge RANGE High upon Falling Edge When Track When Hold Specified Performance SELECT Tied High VREF Pin; DCAPA, DCAPB Pins;
Typically VDRIVE
VDRIVE VDRIVE Straight (Natural) Binary Two's Complement
ISOURCE ISINK 5.25 Selectable with Either Input Range REV.
AD7866
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDRIVE IDD7 Normal Mode (Static) Version1 2.7/5.25 2.7/5.25 Operational, MSPS Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation7 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down (Static) 11.4 1.68 Version1 2.7/5.25 2.7/5.25 11.4 1.68 Unit Test Conditions/Comments SCLK cycles with SCLK MSPS Serial Interface Section min/max min/max Digital I/Ps VDRIVE 4.75 5.25 Typical Using Internal Reference 0.35 Typical Using Internal Reference 4.75 5.25 Typical Using Internal Reference Typical Using Internal Reference kSPS, fSCLK Using Internal Reference (Static) Typical Using Internal Reference SCLK Off. SCLK Off. SCLK Off. SCLK Off. SCLK Off.
NOTES Temperature ranges follows: Versions: -40°C +85°C. Terminology section. Sample tested 25°C ensure compliance. External reference range that applied REF, DCAPA, DCAPB. Relates pins VREF, DCAPA, DCAPB. Reference section CAPA, DCAPB output impedances. Power Versus Throughput Rate section. Specifications subject change without notice.
REV.
AD7866 TIMING SPECIFICATIONS1
Parameter fSCLK
5.25 VDRIVE 5.25 VREF TMIN TMAX, unless otherwise noted.)
Limit TMIN, TMAX tSCLK tSCLK tSCLK
Unit
Description
tCONVERT tQUIET
tSCLK 1/fSCLK fSCLK Minimum Time Between Serial Read Next Falling Edge SCLK Setup Time Delay from Until DOUTA DOUTB Three-State Disabled Data Access Time After SCLK Falling Edge. VDRIVE VDRIVE SCLK Pulsewidth SCLK High Pulsewidth SCLK Data Valid Hold Time Rising Edge DOUTA, DOUTB, High Impedance SCLK Falling Edge DOUTA, DOUTB, High Impedance SCLK Falling Edge DOUTA, DOUTB, High Impedance
NOTES Sample tested 25°C ensure compliance. input signals specified with (10% DRIVE) timed from voltage level Mark/Space ratio input 40/60 60/40. Measured with load circuit Figure defined time required output cross derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that times quoted timing characteristics true relinquish times part independent loading. Specifications subject change without notice.
OUTPUT
1.6V 50pF
Figure Load Circuit Digital Output Timing Specifications
ABSOLUTE MAXIMUM RATINGS
unless otherwise noted)
AVDD AGND -0.3 DVDD DGND -0.3 VDRIVE DGND -0.3 DVDD VDRIVE AGND -0.3 AVDD AVDD DVDD -0.3 +0.3 AGND DGND -0.3 +0.3 Analog Input Voltage AGND -0.3 AVDD Digital Input Voltage DGND -0.3 VREF AGND -0.3 AVDD Digital Output Voltage DGND -0.3 VDRIVE Input Current Except Supplies2 Operating Temperature Range Commercial Versions) -40oC +85oC
Storage Temperature Range -65oC +150oC Junction Temperature 150oC TSSOP Package, Power Dissipation Thermal Impedance 143°C/W (TSSOP) Thermal Impedance 45°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase secs) 215°C Infrared secs) 220°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latch
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7866 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7866
ORDERING GUIDE
Model AD7866ARU AD7866BRU EVAL-AD7866CB1 EVAL-CONTROL BRD22
Temperature Range -40°C +85°C -40°C +85°C Evaluation Board Controller Board
Resolution (Bits)
Package Description Thin Shrink (TSSOP) Thin Shrink (TSSOP) (TSSOP)
Package Option RU-20 RU-20
NOTES This used stand-alone evaluation board conjunction with evaluation board controller evaluation/demonstration purposes. This evaluation board controller complete unit, allowing control communicate with Analog Devices evaluation boards ending designators.
CONFIGURATION
SELECT DCAPB
SCLK VDRIVE
AGND
AD7866
DOUTB
VIEW OUTA (Not Scale) DGND AGND DCAPA VREF
DVDD AVDD RANGE
FUNCTION DESCRIPTIONS
Mnemonic SELECT
Function Internal/External Reference Selection Pin. Logic Input. this tied GND, on-chip reference used reference source both addition, pins VREF, DCAPA, DCAPB must tied decoupling capacitors. SELECT tied logic high, external reference supplied AD7866 through VREF pin, which case decoupling capacitors required DCAPA DCAPB. However, VREF tied AGND while SELECT tied logic low, individual external reference applied both through pins DCAPA DCAPB, respectively. Reference section. Decoupling capacitors connected these pins decouple reference buffer each respective ADC. on-chip reference taken from these pins applied externally rest system. Depending polarity SELECT configuration VREF pin, these pins also used input separate external reference each ADC. range external reference dependent analog input range selected. Reference section. Analog Ground. Ground reference point analog circuitry AD7866. analog input signals external reference signal should referred this AGND voltage. Both these pins should connect AGND plane system. AGND DGND voltages should ideally same potential must more than apart even transient basis. Analog Inputs Single-ended analog input channels. input range each channel VREF VREF range depending polarity RANGE upon falling edge Analog Inputs Single-ended analog input channels. input range each channel VREF VREF range depending polarity RANGE upon falling edge Reference Decoupling External Reference Selection Pin. This connected internal reference requires decoupling capacitor. nominal reference voltage this appears pin; however, internal reference used externally system, must taken from either DCAPA DCAPB pins. This also used conjunction with SELECT when applying external reference AD7866. SELECT description.
DCAPB, DCAPA
AGND
VB2, VA2, VREF
REV.
AD7866
FUNCTION DESCRIPTIONS (continued)
Mnemonic RANGE
Function Analog Input Range Output Coding Selection Pin. Logic Input. polarity this will determine what input range analog input channels AD7866 will have, will also select what type output coding will conversion result. falling edge polarity this checked determine analog input range next conversion. this tied logic low, analog input range VREF output coding from part will straight binary (for next conversion). this tied logic high when goes low, analog input range VREF output coding part will two's complement. However, after falling edge logic level RANGE changed upon eighth SCLK falling edge, output coding will change other option without change analog input range. (See Analog Input Transfer Function sections.) Analog Supply Voltage, 5.25 This only supply voltage analog circuitry AD7866. AVDD DVDD voltages should ideally same potential must more than apart even transient basis. This supply should decoupled AGND. Digital Supply Voltage, 5.25 This supply voltage digital circuitry AD7866. DVDD AVDD voltages should ideally same potential must more than apart even transient basis. This supply should decoupled DGND. Digital Ground. This ground reference point digital circuitry AD7866. DGND AGND voltages should ideally same potential must more than apart even transient basis. Serial Data Outputs. data output supplied this serial data stream. bits clocked falling edge SCLK input. data appears both pins simultaneously from simultaneous conversions both ADCs. data stream consists leading zero followed three STATUS bits, followed bits conversion data. data provided first. held further SCLK cycles after conversion data been output either DOUTA DOUTB, data from other follows DOUT pin. This allows data from simultaneous conversion both ADCs gathered serial format either DOUTA DOUTB alone using only serial port. Serial Interface section. Logic Power Supply Input. voltage supplied this determines what voltage interface will operate This should decoupled DGND. Serial Clock. Logic Input. serial clock input provides SCLK accessing data from AD7866. This clock also used clock source conversion process. Chip Select. Active logic input. This input provides dual function initiating conversions AD7866 also frames serial data transfer. Multiplexer Select. Logic Input. This input used select pair channels converted simultaneously, i.e. Channel both Channel both logic state this checked upon falling edge multiplexer next conversion. low, following conversion will performed Channel each ADC; high, following conversion will performed Channel each ADC.
AVDD
DVDD
DGND
DOUTA, DOUTB
VDRIVE SCLK
REV.
AD7866
TERMINOLOGY Integral Nonlinearity
This maximum deviation from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition, full scale, point above last code transition.
Differential Nonlinearity
half sampling frequency (fS/2), excluding ratio dependent number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02 1.76) Thus 12-bit converter, this
Total Harmonic Distortion
This difference between measured ideal change between adjacent codes ADC.
Offset Error
Total harmonic distortion (THD) ratio harmonics fundamental. AD7866, defined
This applies when using Straight Binary output coding. deviation first code transition 000) 001) from ideal, i.e., AGND LSB.
Offset Error Match
This difference Offset Error between channels.
Gain Error
where amplitude fundamental amplitudes second through sixth harmonics.
Peak Harmonic Spurious Noise
This applies when using Straight Binary output coding. deviation last code transition (111 110) (111 111) from ideal (i.e., VREF LSB) after offset error been adjusted out.
Gain Error Match
This difference Gain Error between channels.
Zero Code Error
This applies when using two's complement output coding option, particular with VREF input range -VREF +VREF biased about VREF point. deviation midscale transition (all from ideal voltage, i.e., VREF LSB.
Zero Code Error Match
Peak harmonic spurious noise defined ratio value next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, ADCs where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
This difference Zero Code Error between channels.
Positive Gain Error
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation distortion terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb), 2fb). AD7866 tested using CCIF standard where input frequencies near input bandwidth used. this case, second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamentals expressed
Channel-to-Channel Isolation
This applies when using two's complement output coding option, particular with VREF input range -VREF +VREF biased about VREF point. deviation last code transition (011 110) (011 111) from ideal (i.e., +VREF LSB) after Zero Code Error been adjusted out.
Negative Gain Error
This applies when using two's complement output coding option, particular with VREF input range -VREF +VREF biased about VREF point. deviation first code transition (100 000) (100 001) from ideal (i.e., -VREF LSB) after Zero Code Error error been adjusted out.
Track/Hold Acquisition Time
track/hold amplifier returns into track mode after conversion. Track/Hold acquisition time time required output track/hold amplifier reach final value, within LSB, after conversion.
Signal (Noise Distortion) Ratio
Channel-to-channel isolation measure level crosstalk between channels. measured applying full-scale VREF), sine wave signal selected input channels determining much that signal attenuated selected channel with signal VREF). figure given worst-case across four channels AD7866.
(Power Supply Rejection)
Performance Curves section.
This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals
REV.
AD7866
PERFORMANCE CURVES
shows typical plot AD7866 sample rate input frequency. shows signal-to(noise distortion) ratio performance versus input frequency various supply voltages while sampling MSPS with SCLK MHz. through show power supply rejection ratio versus AVDD supply ripple frequency AD7866 under different conditions. power supply rejection ratio defined ratio power output full-scale frequency power sine wave applied AVDD supply frequency PSRR (dB) (Pf/PfS)
Power frequency output, power frequency coupled onto AVDD supply. Here peak-to-peak sine wave coupled onto AVDD supply while digital supply left unaltered. TPCs show PSRR AD7866 when there decoupling supply, while TPCs show PSRR with decoupling capacitors supply. show typical plots AD7866. shows graph total harmonic distortion versus analog input frequency various source impedances. shows graph total harmonic distortion versus analog input frequency various supply voltages. Analog Input section.
Typical Performance Characteristics
4098 POINT fSAMPLE 1MSPS
300kHz 70.31dB -85.47dB SFDR -86.64dB
PSRR
100mV SINEWAVE AVDD 2.5V REFERENCE VREF
5.25V 2.7V
3.6V 100k AVDD RIPPLE FREQUENCY
4.75V
-115 FREQUENCY
-100
Dynamic Performance
PSRR Supply Ripple Frequency, without Supply Decoupling
100mV SINEWAVE AVDD 2.5V REFERENCE DCAPA, DCAPB
VDRIVE 2.7V VDRIVE 3.6V
SINAD
PSRR
2.7V 5.25V
VDRIVE 5.25V VDRIVE 4.75V
4.75V 3.6V 100k AVDD RIPPLE FREQUENCY -100
100k INPUT FREQUENCY
1000k
SINAD Input Frequency
PSRR Supply Ripple Frequency, without Supply Decoupling
REV.
AD7866
PSRR
100mV SINEWAVE AVDD 2.5V REFERENCE VREF
-0.2 -0.4 -0.6
2.7V -100 100k AVDD RIPPLE FREQUENCY 3.6V
-0.8 -1.0 1000 1500 2000 2500 Code 3000 3500 4000
PSRR Supply Ripple Frequency, with Supply Decoupling
Plot
PSRR
100mV SINEWAVE AVDD 2.5V REFERENCE DCAPA, DCAPB
4.75V
-100 100k AVDD RIPPLE FREQUENCY 3.6V 4.75V 2.7V
100k INPUT FREQUENCY
1000k
PSRR Supply Ripple Frequency, with Supply Decoupling
Analog Input Frequency Various Source Impedances
VDRIVE 2.7V
VDRIVE 3.6V
-0.2 -0.4 -0.6 -0.8 -1.0 1000 1500 2000 2500 Code 3000 3500 4000
VDRIVE 5.25V VDRIVE 4.75V 100k INPUT FREQUENCY 1000k
Plot
Analog Input Frequency Various Supply Voltages
REV.
AD7866
CIRCUIT INFORMATION
AD7866 fast, micropower, dual 12-bit, single supply, converter that operates from 5.25 supply. When operated from either supply supply, AD7866 capable throughput rates MSPS when provided with clock. AD7866 contains on-chip track/hold amplifiers, successive-approximation converters, serial interface with separate data output pins, housed 20-lead TSSOP package, which offers user considerable space-saving advantages over alternative solutions. serial clock input accesses data from part also provides clock source each successive-approximation converter. analog input range part selected VREF input VREF input with either straight binary two's complement output coding. AD7866 on-chip reference which overdriven external reference preferred. addition, each supplied with individual separate external reference. AD7866 also features power-down options allow power saving between conversions. power-down feature implemented across standard serial interface described Modes Operation section.
CONVERTER OPERATION
CAPACITIVE COMPARATOR AGND CONTROL LOGIC
Figure Conversion Phase
ANALOG INPUT
AD7866 successive-approximation analog-to-digital converters, each based around capacitive DAC. Figures show simplified schematics these ADCs. comprised control logic, SAR, capacitive DAC, which used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. Figure shows during acquisition phase. closed position comparator held balanced condition sampling capacitor acquires signal example.
CAPACITIVE COMPARATOR AGND CONTROL LOGIC
Figure shows equivalent circuit analog input structure AD7866. diodes provide protection analog inputs. Care must taken ensure that analog input signal never exceeds supply rails more than This will cause these diodes become forwardbiased start conducting current into substrate. maximum current these diodes conduct without causing irreversible damage part. capacitor Figure typically about primarily attributed capacitance. resistor lumped component made resistance switch. This resistor typically about capacitor sampling capacitor capacitance typically. applications, removing high-frequency components from analog input signal recommended low-pass filter relevant analog input pin. applications where harmonic distortion signal-to-noise ratio critical, analog input should driven from impedance source. Large source impedances will significantly affect performance ADC. This necessitate input buffer amplifier. choice will function particular application.
CONVERT PHASE SWITCH OPEN TRACK PHASE SWITCH CLOSED
Figure Equivalent Analog Input Circuit Figure Acquisition Phase
When starts conversion (see Figure will open will move position causing comparator become unbalanced. Control Logic capacitive used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. When comparator rebalanced conversion complete. Control Logic generates output code. Figures show transfer functions.
When amplifier used drive analog input source impedance should limited values. maximum source impedance will depend amount total harmonic distortion (THD) that tolerated. will increase source impedance increases performance will degrade (see
Analog Input Ranges
analog input range AD7866 selected VREF VREF with either straight binary two's complement output coding. RANGE used select both analog input range output coding, shown Figures through falling edge point logic level RANGE checked determine analog input range next conversion. this tied logic then
-10-
REV.
AD7866
analog input range will VREF output coding from part will straight binary (for next conversion). this logic high when goes low, then analog input range will VREF output coding part will two's complement. However, after falling edge logic level RANGE changed upon eighth falling SCLK edge, point output coding will change other option without change analog input range. next conversion, two's complement output coding could selected with VREF input range, example, RANGE upon falling edge high upon eighth falling SCLK edge, shown Figure Figures through show examples timing diagrams when selecting particular analog input range with particular output coding format. Table also summarizes required logic level RANGE each selection. Logic Input used select pair channels converted simultaneously. Logic state this also checked upon falling edge multiplexers next conversion. low, following conversion will performed Channel each ADC; high, following conversion will performed Channel each ADC.
Handling Bipolar Input Signals
Figure shows useful combination VREF input range two's complement output coding scheme handling bipolar input signals. bipolar input signal biased about VREF two's complement output coding selected, then VREF becomes zero code point, -VREF negative fullscale +VREF becomes positive full-scale, with dynamic range VREF.
Transfer Functions
designed code transitions occur successive integer values (i.e., LSB, LSBs, etc.). size VREF/4096. ideal transfer characteristic AD7866 when straight binary coding selected shown Figure ideal transfer characteristic AD7866 when two's complement coding selected shown Figure
Table Analog Input Output Coding Selection
Range Level Point High High
Range Level Point High High
Input Range3 VREF VREF VREF VREF VREF VREF
Output Coding3 Straight Binary Two's Complement Two's Complement Straight Binary
NOTES Point Falling edge Point Eighth falling edge SCLK. Selected NEXT conversion.
SCLK
INPUT RANGE
RANGE
DOUTA DOUTB
STRAIGHT BINARY
Figure Selecting VREF Input Range with Straight Binary Output Coding
SCLK
INPUT RANGE
RANGE
DOUTA DOUTB
TWO'S COMPLEMENT
Figure Selecting VREF VREF Input Range with Two's Complement Output Coding
REV.
-11-
AD7866
SCLK
INPUT RANGE
RANGE
DOUTA DOUTB
TWO'S COMPLEMENT
Figure Selecting VREF/2 VREF/2 Input Range with Two's Complement Output Coding
SCLK
INPUT RANGE
RANGE
DOUTA DOUTB
STRAIGHT BINARY
Figure Selecting VREF Input Range with Straight Binary Output Coding
VREF 100nF SELECT VREF 470nF +VREF VREF) 470nF DCAPA DCAPB VDRIVE TWO'S COMPLEMENT
DSP/
AD7866
DOUT
VREF
-VREF
Figure Handling Bipolar Signals with AD7866
1LSB 011.111 011.110
CODE
111.111 111.110
CODE
VREF/4096
111.000 1LSB VREF/4096 011.111 000.010 000.001 000.000 1LSB ANALOG INPUT VREF 1LSB
000.001 000.000 111.111 100.010 100.001 100.000 -VREF 1LSB +VREF 1LSB VREF 1LSB ANALOG INPUT
Figure Straight Binary Transfer Characteristic with VREF Input Range
Figure Two's Complement Transfer Characteristic with VREF VREF Input Range
-12-
REV.
AD7866
Digital Inputs
digital inputs applied AD7866 limited maximum ratings which limit analog inputs. Instead, digital inputs applied restricted limit analog inputs. maximum ratings. Another advantage SCLK, RANGE, SELECT, being restricted limit fact that power supply sequencing issues avoided. these digital inputs applied before VDD, there risk latch-up there would analog inputs signal greater than were applied prior VDD.
VDRIVE
470nF
DCAPA
AD7866
470nF DCAPB
100nF
VREF
Figure Relevant Connections When Using Internal Reference
AD7866 also VDRIVE feature. VDRIVE controls voltage which serial interface operates. VDRIVE allows easily interface both processors. example, AD7866 operated with VDRIVE could powered from supply, allowing large dynamic range with voltage digital processors. example, AD7866 could used with VREF input range, with while still being able interface digital parts.
REFERENCE SECTION
AD7866 various reference configuration options. SELECT allows choice using internal reference applying external reference, even individual external reference each on-chip desired. SELECT tied AGND then on-chip reference used reference source both addition, pins VREF, DCAPA, DCAPB must tied decoupling capacitors (100 recommended, respectively). SELECT tied logic high, then external reference supplied AD7866 through VREF overdrive on-chip reference, which case decoupling capacitors required DCAPA DCAPB again. However, VREF tied AGND while SELECT tied logic low, then individual external reference applied both through pins DCAPA DCAPB, respectively. Table summarizes these reference options. specified performance last configuration used, with same reference voltage applied both DCAPA DCAPB. connections relevant reference pins shown typical connection diagrams. internal reference being used, VREF should have capacitor connected AGND very close VREF pin. These connections shown Figure
Figure shows connections required when external reference applied DCAPA DCAPB. this example same reference voltage applied each pin; however, different voltage applied each these pins each on-chip ADC. external reference applied these pins have range from specified performance must within Figure shows third option which overdrive internal reference through VREF pin. This possible series resistance from VREF internal reference. This external reference have range from again close possible specified performance reference desirable. DCAPA DCAPB decouple each on-chip reference buffer shown Figure on-chip reference being used, applied externally rest system,
DCAPA VREF DCAPB
AD7866
VREF SELECT
Figure Relevant Connections When Applying External Reference DCAP and/or DCAP
DCAPA
470nF
AD7866
DCAPB VDRIVE
470nF VREF
VREF
SELECT
Figure Relevant Connections When Applying External Reference VREF
Table Reference Selection
Reference Option Internal Externally through VREF Externally through DCAP and/or DCAPB
SELECT High
VREF1 Decoupling Capacitor External Reference AGND
DCAP DCAPB2 Decoupling Capacitor Decoupling Capacitor External Reference and/or Reference
NOTES Recommended value decoupling capacitor Recommended value decoupling capacitor
REV.
-13-
AD7866
100nF VREF DCAPA 470nF
provide flexible power management options. These options chosen optimize power dissipation/throughput rate ratio differing application requirements.
Normal Mode
2.5V
DCAPB 470nF
This mode intended fastest throughput rate performance user does have worry about power-up times with AD7866 remaining fully powered time. Figure shows general diagram operation AD7866 this mode. conversion initiated falling edge described Serial Interface section. ensure part remains fully powered times must remain until least SCLK falling edges have elapsed after falling edge brought high time after 10th SCLK falling edge, before 16th SCLK falling edge, part will remain powered conversion will terminated DOUTA DOUTB will back into three-state. Sixteen serial clock cycles required complete conversion access conversion result. DOUT line will return three-state after SCLK cycles have elapsed, instead when brought high again. left further SCLK cycles then result from other board will also accessed same DOUT line shown Figure (see Serial Interface section). STATUS bits provided prior each conversion result will identify which following result will from. Once SCLK cycles have elapsed, DOUT line will return three-state 32nd SCLK falling edge. brought high prior this, DOUT line will return three-state that point. Hence, idle after SCLK cycles, until brought high again sometime prior next conversion (effectively idling low), desired, will still return three-state upon completion dual result read. Once data transfer complete DOUTA DOUTB have returned three-state, another conversion initiated after quiet time, tQUIET, elapsed bringing again.
Partial Power-Down Mode
Figure Reference Circuit
taken from either VREF DCAPA DCAPB pins. taken from VREF pin, must buffered before being applied elsewhere will capable sourcing more than microamps. reference voltage taken from either DCAPA DCAPB pin, buffer strictly necessary. Either capable sourcing current region however, larger source current requirement, greater voltage drop seen pin. output impedance each these pins typically addition, this point represents actual voltage applied internally voltage drop current load disturbance dynamic load will directly affect conversion. this reason, large current source necessary, dynamic load present, recommended buffer output drive device. Examples suitable external reference devices that applied pins VREF, DCAPA, DCAPB AD780, REF192, REF43, AD1582.
MODES OPERATION
mode operation AD7866 selected controlling (logic) state signal during conversion. There three possible modes operation, Normal Mode, Partial Power-Down Mode, Full Power-Down Mode. point which pulled high after conversion been initiated will determine which power-down mode, any, device will enter. Similarly, already power-down mode, control whether device will return normal operation remain power-down. These modes operation designed
This mode intended applications where slower throughput rates required. Either powered down between each conversion, series conversions performed high throughput rate then powered down relatively long duration between these bursts several conversions. When AD7866 Partial Power-Down, analog circuitry powered down except on-chip reference reference buffer.
SCLK
DOUTA DOUTB
STATUS BITS CONVERSION RESULT
Figure Normal Mode Operation
-14-
REV.
AD7866
enter Partial Power-Down, conversion process must interrupted bringing high anywhere after second falling edge SCLK before 10th falling edge SCLK shown Figure Once been brought high this window SCLKs, part will enter Partial Power-Down conversion that initiated falling edge will terminated DOUTA DOUTB will back into three-state. brought high before second SCLK falling edge, part will remain normal mode will power down. This will avoid accidental power-down glitches line. order exit this mode operation power AD7866 again, dummy conversion performed. falling edge device will begin power will continue power long held until after falling edge 10th SCLK. case external reference, device will fully powered once SCLKs have elapsed valid data will result from next conversion shown Figure brought high before second falling edge SCLK, AD7866 will again into partial power-down. This avoids accidental power-up glitches line; although device begin power falling edge will power down again rising edge AD7866 already Partial Power-Down mode brought high between second tenth falling edges SCLK, device will enter Full Power-Down mode. more information power-up times associated with partial powerdown various configurations, Power-Up Times section.
Full Power-Down Mode
Full Power-Down, analog circuitry powered down. Full Power-Down entered similar Partial Power-Down, except timing sequence shown Figure must executed twice. conversion process must interrupted similar fashion bringing high anywhere after second falling edge SCLK before 10th falling edge SCLK. device will enter Partial Power Down this point. reach Full PowerDown, next conversion cycle must interrupted same way, shown Figure Once been brought high this window SCLKs, part will power down completely. NOTE: necessary complete SCLKs once been brought high enter power-down mode. exit Full Power-Down, power AD7866 again, dummy conversion performed, when powering from Partial Power-Down. falling edge device will begin power will continue power long held until after falling edge 10th SCLK. power-up time required must elapse before conversion initiated shown Figure Power-up Times section power-up times associated with AD7866.
POWER-UP TIMES
This mode intended applications where slower throughput rates required than those Partial PowerDown mode, power-up from Full Power-Down takes substantially longer than that from partial power-down. This mode more suited applications where series conversions performed relatively high throughput rate would followed long period inactivity hence power-down. When AD7866
AD7866 power-down modes, Partial PowerDown Full Power-Down, which described detail Modes Operation section. This section deals with power-up time required when coming either these modes. should noted that power-up times quoted apply with recommended capacitors VREF, CAPA, CAPB pins place. power from Full Power-Down approximately should allowed from falling edge shown Figure tPOWER Powering from Partial Power-Down requires much less time. internal reference being used, power-up
SCLK
DOUTA DOUTB
THREE-STATE
Figure Entering Partial Power-Down Mode
PART BEGINS POWER
PART FULLY POWERED POWER-UP TIMES SECTION
SCLK DOUTA DOUTB
INVALID DATA
VALID DATA
Figure Exiting Partial Power-Down Mode
REV.
-15-
AD7866
PART ENTERS PARTIAL POWER-DOWN PART BEGINS POWER-UP PART ENTERS FULL POWER-DOWN
SCLK
DOUTA DOUTB
THREE-STATE INVALID DATA INVALID DATA
THREE-STATE
Figure Entering Full Power-Down Mode
PART BEGINS POWER PART FULLY POWERED
tPOWER
SCLK
DOUTA DOUTB
INVALID DATA
VALID DATA
Figure Exiting Full Power-Down Mode
time typically external reference being used, power-up time typically This means that with frequency SCLK MHz, dummy cycle will always sufficient allow device power from Partial Power-Down (see Figure when using external reference. Once dummy cycle complete, will fully powered input signal will acquired properly. dummy cycle well sufficient power part when using internal reference also, provided SCLK slow enough allow required powerup time elapse before valid conversion requested. addition this, should ensured that quiet time, tQUIET, still been allowed from point where goes back into threestate after dummy conversion next falling edge Alternatively, instead slowing SCLK make dummy cycle long enough, high time could just extended include required power-up time Figure when powering from Full Power-Down. difference power-up time needed, when coming Partial Power-Down, between cases where internal external reference being used, primarily on-chip reference buffers. These power down Partial Power-Down mode must powered again internal reference being used, need powered again external reference being used. time needed power these buffers just their power-up time also time required charge decoupling capacitors present pins VREF, DCAPA, DCAPB. should also noted that when powering from Partial Power-Down, track-and-hold, which hold mode while part powered down, returns track mode after first SCLK edge part receives after falling edge This shown point Figure When power supplies first applied AD7866, power either power-down modes normal
mode. Because this, best allow dummy cycle elapse ensure part fully powered before attempting valid conversion. Likewise, intended keep part partial power-down mode immediately after supplies applied, dummy cycles must initiated. first dummy cycle must hold until after 10th SCLK falling edge (see Figure 16); second cycle must brought high before 10th SCLK edge after second SCLK falling edge (see Figure 17). Alternatively, intended place part Full PowerDown mode when supplies have been applied, three dummy cycles must initiated. first dummy cycle must hold until after 10th SCLK falling edge (see Figure 16); second third dummy cycles place part Full PowerDown (see Figure 19). Modes Operation section. Once supplies applied AD7866, enough time must allowed external reference power charge reference capacitor final value, enough time must allowed internal reference buffer charge various reference buffer decoupling capacitors their final values. Then, place AD7866 normal mode, dummy cycle approximately) should initiated. first valid conversion then performed directly after dummy conversion, care must taken ensure that adequate acquisition time been allowed. mentioned earlier, when powering from power-down mode, part will return track upon first SCLK edge applied after falling edge However, when powers initially after supplies applied, trackand-hold will already track. This means that (assuming facility monitor supply current) powers desired mode operation thus dummy cycle required change mode, then neither dummy cycle required place track-and-hold into track. current monitoring facility available, relevant dummy cycle(s) should performed ensure part required mode. REV.
-16-
AD7866
POWER VERSUS THROUGHPUT RATE
using Partial Power-Down mode AD7866 when converting, average power consumption decreases lower throughput rates. Figure shows throughput rate reduced, part remains partial power-down state longer average power consumption over time drops accordingly.
SCLK 20MHz
POWER
SCLK 20MHz
during each conversion cycle. remainder conversion cycle, part remains Partial Power-Down mode. AD7866 said dissipate remaining conversion cycle. throughput rate kSPS, cycle time average power dissipated during each cycle (2/10) (8/10) (2.8 7.04 SCLK device again Partial Power-Down mode between conversions, power dissipated during normal operation AD7866 said dissipate during each conversion cycle 1.68 remaining where part Partial Power-Down. With throughput rate kSPS, average power dissipated during each conversion cycle (2/10) (8.4 (8/10) (1.68 3.02 Figure shows power versus throughput rate when using Partial Power-Down mode between conversions with both supplies AD7866.
SERIAL INTERFACE
0.01 THROUGHPUT kSPS
Figure shows detailed timing diagram serial interfacing AD7866. serial clock provides conversion clock also controls transfer information from AD7866 during conversion. signal initiates data transfer conversion process. falling edge puts track-and-hold into hold mode, takes three-state analog input sampled this point. conversion also initiated this point will require SCLK cycles complete. Once SCLK falling edges have elapsed, then track hold will back into track next SCLK rising edge shown Figure point rising edge conversion will terminated DOUTA DOUTB will back into three-state. brought high, instead held further SCLK cycles
Figure Power Throughput Partial Power-Down
example, AD7866 operated continuous sampling mode with throughput rate kSPS SCLK (VDD device placed Partial Power-Down mode between conversions, then power consumption calculated follows. maximum power dissipation during normal operation (VDD power-up time allowed from Partial Power-Down dummy cycle, i.e., (assumes external reference) remaining conversion time another cycle, i.e., then AD7866 said dissipate
SCLK
DOUTA DOUTB THREESTATE RANGE
DB11 DB10
QUIET
THREESTATE
LEADING ZERO, STATUS BITS
Figure Serial Interface Timing Diagram
SCLK
DOUTA THREESTATE
RANGE ZERO
DB11A
DB1A DB0A ZERO RANGE DB11B DB1B
DB0B
THREESTATE
LEADING ZERO, STATUS BITS
LEADING ZERO, STATUS BITS
Figure Reading Data from Both ADCs DOUT Line
REV.
-17-
AD7866
Table III. STATUS Description
Name ZERO RANGE
Comment Leading Zero. This will always zero output. polarity this reflects analog input range that been selected with RANGE pin. means that previous transfer upon falling edge range logic providing analog input range from VREF this conversion. means that previous transfer upon falling edge RANGE logic high resulting analog input range VREF selected this conversion. Analog Input section. This indicates which channel conversion being performed, Channel Channel question. this conversion result will from Channel ADC, result will from Channel question. This indicates which conversion result from. this result from result from This especially useful only serial port available DOUT line used, shown Figure SPORT0 control register should follows: TFSW RFSW Alternate Framing INVRFS INVTFS Active Frame Signal DTYPE Right Justify Data SLEN 1111, 16-Bit Data Words ISCLK Internal Serial Clock TFSR RFSR Frame Every Word IRFS ITFS SPORT1 control register should follows: TFSW RFSW Alternate Framing INVRFS INVTFS Active Frame Signal DTYPE Right Justify Data SLEN 1111, 16-Bit Data Words ISCLK External Serial Clock TFSR RFSR Frame Every Word IRFS ITFS implement power-down modes AD7866 SLEN should 1001 issue 8-bit SCLK burst. connection diagram shown Figure ADSP-218x TFS0 RFS0 SPORT0 RFS1 SPORT1 tied together, with TFS0 output both RFS0 RFS1 inputs. operates Alternate Framing Mode SPORT control register described. Frame synchronization signal generated tied with signal processing applications equidistant sampling necessary. However, this example, timer interrupt used control sampling rate under certain conditions, equidistant sampling achieved. Timer other registers loaded with value that will provide interrupt required sample interval. When interrupt received, value transmitted with TFS/DT (ADC control word). used control hence reading data. frequency serial clock SCLKDIV register. When instruction transmit with given, (i.e., TX0), state SCLK checked. will wait until SCLK gone High, Low, High before transmission will start. timer SCLK values chosen such that instruction transmit occurs near rising edge SCLK, data transmitted wait until next clock edge. REV.
DOUTA, data from conversion will output DOUTA. Likewise, held further SCLK cycles DOUTB, data from conversion will output DOUTB. This illustrated Figure where case DOUTA shown. Note that this case DOUT line will back into three-state 32nd SCLK rising edge rising edge whichever occurs first. Sixteen serial clock cycles required perform conversion process access data from conversion either data line AD7866. going provides leading zero read microcontroller DSP. remaining data then clocked subsequent SCLK falling edges, beginning with first three data STATUS bits, thus first falling clock edge serial clock leading zero provided also clocks first three STATUS bits. final data transfer valid 16th falling edge, having being clocked previous (15th) falling edge. applications with slower SCLK, possible read data each SCLK rising edge, i.e., first rising edge SCLK after falling edge would have leading zero provided 15th rising SCLK edge would have provided.The three STATUS bits that follow leading zero provide information with respect conversion result that follows them DOUT line use. Table shows these identification bits interpreted.
MICROPROCESSOR INTERFACING
serial interface AD7866 allows parts directly connected range many different microprocessors. This section explains interface AD7866 with some more common microcontroller serial interface protocols.
AD7866 ADSP-218x
ADSP-218x family DSPs directly interfaced AD7866 without glue logic required. VDRIVE AD7866 takes same supply voltage that ADSP-218x. This allows operate higher supply voltage than serial interface, i.e., ADSP-218x, necessary. This example shows both DOUT DOUT AD7866 connected both serial ports ADSP-218x.
-18-
AD7866
example, ADSP-2189 crystal, such that master clock frequency then master cycle time would SCLKDIV register loaded with value SCLK obtained, eight master clock periods will elapse every SCLK period. Depending throughput rate selected, timer register loaded with value, 803, (803 804) 100.5 SCLKs will occur between interrupts subsequently between transmit instructions. This situation will result non-equidistant sampling transmit instruction occurring SCLK edge. number SCLKs between interrupts whole integer figure equidistant sampling will implemented DSP.
AD7866*
SCLK
connection diagram shown Figure should noted that signal processing applications, imperative that frame synchronization signal from TMS320C541 will provide equidistant sampling. VDRIVE AD7866 takes same supply voltage that TMS320C541. This allows operate higher voltage than serial interface, i.e., TMS320C541, necessary.
AD7866 DSP-563xx
ADSP-21xx*
SCLK0 SCLK1 TFS0 RFS0 RSF1
DOUTA DOUTB VDRIVE
connection diagram Figure shows AD7866 connected ESSI (Synchronous Serial Interface) DSP-563xx family DSPs from Motorola. Each ESSI (two on-board) operated Synchronous Mode (Bit register) with internally generated word length frame sync both (bits FSL1 FSL0 CRB). Normal operation ESSI selected making CRB. word length setting bits CRA. implement power-down modes AD7866 word length changed eight bits setting bits CRA. should frame sync negative. should noted that signal processing applications, imperative that frame synchronization signal from DSP-563xx will provide equidistant sampling. example shown Figure serial clock taken from ESSI0 SCK0 must output, SCKD while SCK1 input, SCKD frame sync signal taken from SC02 ESSI0, SCD2 while ESSI1, SCD2 SC12 configured input. VDRIVE AD7866 takes same supply voltage that DSP-563xx. This allows operate higher voltage than serial interface, i.e., DSP-563xx, necessary.
AD7866*
SCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing AD7866 ADSP-218x
AD7866*
SCLK
TMS320C541*
CLKX0 CLKR0 CLKX1 CLKR1
DSP-563xx*
SCK0 SCK1
DOUTA DOUTB VDRIVE
FSX0 FSR0 FSR1
DOUTA DOUTB
SRD0 SRD1
SC02 SC12
VDRIVE
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing AD7866 TMS320C541
AD7866 TMS320C541
*ADDITIONAL PINS OMITTED CLARITY
serial interface TMS320C541 uses continuous serial clock frame synchronization signals synchronize data transfer operations with peripheral devices like AD7866. input allows easy interfacing between TMS320C541 AD7866 without glue logic required. serial ports TMS320C541 operate burst mode with internal CLKX serial clock serial port FSX0 frame sync from serial port serial port control registers (SPC) must have following setup: SPC0: SPC1: format bit, word length bits, order implement power-down modes AD7866.
Figure Interfacing DSP-563xx
APPLICATION HINTS Grounding Layout
analog digital supplies AD7866 independent separately pinned minimize coupling between analog digital sections device. AD7866 very good immunity noise power supplies seen PSRR Supply Ripple Frequency plots, However, care should still taken with regard grounding layout. printed circuit board that houses AD7866 should designed such that analog digital sections separated confined certain areas board. This facilitates ground planes that easily separated. minimum etch technique generally best ground planes gives best -19-
REV.
AD7866
shielding. Both AGND pins AD7866 should sunk AGND plane. Digital analog ground planes should joined only place. AD7866 system where multiple devices require AGND-to-DGND connection, connection should still made point only, star ground point that should established close possible AD7866. Avoid running digital lines under device these will couple noise onto die. analog ground plane should allowed under AD7866 avoid noise coupling. power supply lines AD7866 should large trace possible provide impedance paths reduce effects glitches power supply line. Fast switching signals like clocks should shielded with digital ground avoid radiating noise other sections board, clock signals should never near analog inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough through board. microstrip technique best always possible with double-sided board. this technique, component side board dedicated ground planes while signals placed solder side. Good decoupling also important. analog supplies should decoupled with tantalum parallel with capacitors AGND. digital supplies should have least disc ceramic capacitor DGND. VDRIVE should have ceramic capacitor DGND. achieve best from these decoupling components, they must placed close possible device, ideally right against device. capacitors should have Effective Series Resistance (ESR) Effective Series Inductance (ESI), such common ceramic surface mount types, which provide impedance path ground high frequencies handle transient currents internal logic switching. Figure shows recommended supply decoupling scheme. information decoupling requirements each reference configuration, Reference section.
C02672-0-1/02(0)
AVDD AGND AGND
DVDD DGND VDRIVE
AD7866
Figure Recommended Supply Decoupling Scheme
Evaluating AD7866 Performance
recommended layout AD7866 outlined evaluation board AD7866. evaluation board package includes fully assembled tested evaluation board, documentation, software controlling board from EVALBOARD CONTROLLER. EVAL-BOARD CONTROLLER used conjunction with AD7866 Evaluation board, well many other Analog Devices evaluation boards ending designator, demonstrate/evaluate performance AD7866. software allows user perform (fast Fourier transform) (histogram codes) tests AD7866.
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Lead Thin Shrink Small Outline Package (RU-20)
0.260 (6.60) 0.252 (6.40)
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10)
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-20-
REV.
PRINTED U.S.A.

Dual MSPS, 12-Bit, 2-Channel with Serial Interface AD7866 VREF DC

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