Altera Devices July 2001, ver. Introduction critical el
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Evaluating Power
Altera Devices
July 2001, ver.
Introduction
critical element system reliability capacity electronic devices safely dissipate heat generated during operation. thermal characteristics circuit depend device package used, operating temperature, operating current, system's ability dissipate heat. should complete power evaluation early design process help identify potential heat-related problems system prevent system from exceeding device's maximum allowed junction temperature. This application note discusses evaluate manage power, provides sample worksheets performing power evaluation.
Power Evaluation
actual power dissipated most applications significantly lower than power package dissipate. However, thermal analysis should performed projects. evaluate power usage your system, following steps: Estimate power consumption application. Calculate maximum power device package. Compare estimated maximum power values.
Table shows variables used estimating power consumption. Table Variables Used Evaluating Power Consumption (Part Variable
ICCCSTANDBY fMAX ICCINT PINT MCTON MCDEV MCUSED PDCOUT µA/(MHz
Unit
Altera Corporation
A-AN-074-3.1
Evaluating Power Altera Devices
Table Variables Used Evaluating Power Consumption (Part Variable
CAVE PACOUT PEST PMAX
Unit
Estimating Power Consumption
following formula compute estimated power consumption (PEST) application: PEST PINT Where: PINT ICCINT VCCINT PACOUT PDCOUT
Therefore: PEST (ICCINT VCCINT) (PACOUT PDCOUT) no-load power (PINT) value obtained from "Power Consumption" section each device family data sheet. Because this value "unloaded," necessary power dissipated buffers-PDCOUT from steady-state outputs PACOUT current from frequently switching outputs. PDCOUT depends number steady-state outputs, logic levels they drive, resistive load each output, shown following formula: PDCOUT Where:
PDCn
Number outputs output power output Voltage swing output Switching frequency output
PDCn
Altera Corporation
Evaluating Power Altera Devices
Table shows power dissipated output drivers device with VCCIO under typical types loads. power dissipated output driver does equal ICCIO value because most power consumed load. using 2.5-V 3.3-V device non-5.0-V VCCIO, compute power based device's figures shown device family data sheet. Table Power Dissipated Load Driven
pull-up resistor outputs pull-down resistor high outputs Bipolar outputs Bipolar high outputs CMOS inputs
PDCn (mW)
0.49 5.04 0.16 0.0576 Negligible
PACOUT depends capacitive load each output frequency which each output switches, shown following formula: PACOUT Where:
VCCIO
Number outputs Capacitive load output Voltage swing output Switching frequency output
following equation shows frequency each output (fn), terms maximum clock frequency (fMAX) design average ratio pins toggling each clock (togIO): (0.5) fMAX togIO Inserting equation into PACOUT equation resolving summation average capacitive load yields following formula: PACOUT (0.5) CAVE fMAX togIO VCCIO Where: Total number output bidirectional pins
Altera Corporation
Evaluating Power Altera Devices
Table shows VCCIO values Altera® devices. Table VCCIO Values VCCIO
example, following equation provides power consumed driving capacitive load applications with VCCIO PACOUT (0.5) CAVE fMAX togIO
Calculating Maximum Power Device Package
following formulas used calculate maximum allowed power MAX) device:
maximum allowed power dependent maximum allowed junction temperature (TJ) silicon, ambient temperature operation (TA), package's thermal resistance (JA) when configured system. maximum junction temperature specified Altera device family data sheets. ambient temperature depends application. worst-case value estimated using formula with junction-to-ambient thermal resistance. value Altera devices provided still (with convection cooling only), forced-air flow feet/second, feet/second, feet/second. heat-sinking used dissipate heat heat sink given, should case temperature (TC) junctionto-case thermal resistance calculate device. measure lowest possible thermal resistance.
thermal resistance values Altera devices, refer Altera Device Packaging Information Data Sheet.
Altera Corporation
Evaluating Power Altera Devices
Comparing Maximum Allowed Power Estimated Power
avoid reliability problems, should compare values calculated maximum allowed power estimated power. estimated power should smaller values. estimated power exceeds maximum allowed power, refer "Thermal Management" page suggestions reduce power requirements design. Figure shows sample worksheet evaluating power. Figure Power Evaluation Worksheet (Part
Design_ Device_
Estimating Power Consumption Application
Internal Power Calculation Altera Devices FLEX 10K, FLEX 8000 FLEX 6000 Devices Standby current (ICCSTANDBY) Coefficient calculation. appropriate device family data sheet this value. Maximum clock frequency (fMAX) Total number logic elements (LEs) used device Average ratio logic cells toggling (togLC) each clock (typically 0.125) Total internal current (ICCINT) ICCINT ICC0 fMAX togLC Total internal power (PINT) PINT ICCINT 9000, 7000 3000A Devices Coefficients calculation. appropriate device family data sheet these values. Number macrocells with Turbo Biton (MCTON) Number macrocells device (MCDEV) Number macrocells design (MCUSED) Maximum clock frequency (fMAX) Average ratio logic cells toggling (togLC) each clock (typically 0.125) Total internal current (ICCINT) ICCINT MCTON) (MCDEV MCTON)] MCUSED fMAX togLC) Total internal power (PINT) PINT ICCINT PINT MCTON MCDEV MCUSED fMAX togLC ICCINT mA/LE mA/LE mA/(MHz PINT ICCSTANDBY fMAX togLC ICCINT µA/(MHz
Altera Corporation
Evaluating Power Altera Devices
Figure Power Evaluation Worksheet (Part
External Power Calculation Altera Devices Power consumed output load (PDCOUT) PDCOUT PDCn Average capacitive load (CAVE) output pins Number output/bidirectional pins design (OUT) Average ratio pins toggling (togIO) each clock (typically 0.125) Power consumed output load (PACOUT) PACOUT CAVE fMAX togIO VCCIO 0.001 Total external power (PIO) PDCOUT PACOUT Total Power Calculation Altera Devices Estimated total power (PEST) PEST PINT PEST CAVE togIO PACOUT PDCOUT
Calculating Maximum Allowed Power Device Package
Thermal resistance device Maximum junction temperature (TJ) specified appropriate device family data sheet. Ambient temperature (TA) design Maximum power (PMAX) allowed device PMAX PMAX
Comparing Maximum Power Allowed Estimated Power
PEST PMAX?
Altera Corporation
Evaluating Power Altera Devices
Tables show design parameters sample power evaluations shown Figures design parameters unique sample designs found device family data sheets. Table Parameters Sample FLEX Design Parameter
CMOS inputs CAVE fMAX PDCOUT
Description
Number outputs Type load Average capacitance Number logic elements used Maximum operating frequency Static power consumed outputs 2,747
Value
Number pull-up resistors Type load
(0.49 231) 24.5
Table Parameters Sample 9000 Design Parameter
MCTON MCDEV MCUSED MCTOFF fMAX CMOS inputs CAVE PDCOUT (5.04 201)
Value
Number pull-down resistors
Figures provide power evaluations sample designs implemented FLEX® MAX® 9000 devices, respectively.
Altera Corporation
Evaluating Power Altera Devices
Figure Sample Power Evaluation FLEX Device (Part dsp_fir.tdf Design_ EPF10K50VBC356-2 Device_
Estimating Power Consumption Application Internal Power Calculation FLEX 10K, FLEX 8000 FLEX 6000 Devices Standby current (ICCSTANDBY) Coefficient calculation. appropriate device family data sheet this value. Maximum clock frequency (fMAX) Total number logic elements used device Average ratio logic cells toggling (togLC) each clock (typically 0.125) Total internal current (ICCINT) ICCINT ICCSTANDBY fMAX togLC Total internal power (PINT) PINT ICCINT External Power Calculation Altera Devices Power consumed output load (PDCOUT) PDCOUT PDCn Average capacitive load (CAVE) output pins Number output/bidirectional pins design (OUT) Average ratio pins toggling (togIO) each clock (typically 0.125) Power consumed output load (PACOUT) PACOUT CAVE fMAX togIO 0.001 Total external power (PIO) PDCOUT PACOUT Total Power Calculation Altera Devices Estimated total power (PEST) PEST PINT PEST 2,764.9 213.66 CAVE togIO PACOUT 0.125 178.66 PDCOUT PINT 2,551.2 ICCSTANDBY fMAX togLC ICCINT 0.500 2,747 0.125 773.09 µA/(MHz
Altera Corporation
Evaluating Power Altera Devices
Figure Sample Power Evaluation FLEX Device (Part
Calculating Maximum Allowed Power Device Package Thermal resistance device Maximum junction temperature (TJ) specified appropriate device family data sheet. Ambient temperature (TA) design Maximum power (PMAX) allowed device PMAX Comparing Maximum Power Allowed Estimated Power PEST PMAX? PMAX 5.625
Figure Sample Power Evaluation 9000 Device (Part atm_pkt.tdf Design_ EPM9560ARC304-10 Device_
Estimating Power Consumption Application Internal Power Calculation 9000, 7000 3000A Devices Coefficients calculation. appropriate device family data sheet these values. Number macrocells with Turbo (MCTON) Number macrocells device (MCDEV) Number macrocells design (MCUSED) Maximum clock frequency (fMAX) Average ratio logic cells toggling (togLC) each clock (typically 0.125) Total internal current (ICCINT) ICCINT MCTON) (MCDEV MCTON)] MCUSED fMAX togLC) Total internal power (PINT) PINT ICCINT External Power Calculation Altera Devices Power consumed output load (PDCOUT) PDCOUT PDCn Average capacitive load (CAVE) output pins Number output/bidirectional pins design (OUT) Average ratio pins toggling (togIO) each clock (typically 0.125) Power consumed output load (PACOUT) CAVE togIO PACOUT 0.125 350.79 PDCOUT PINT 1,669.9 MCTON MCDEV MCUSED fMAX togLC ICCINT 0.68 0.26 0.052 0.125 333.98 mA/LE mA/LE mA/(MHz
Altera Corporation
Evaluating Power Altera Devices
Figure Sample Power Evaluation 9000 Device (Part
PACOUT CAVE fMAX togIO 0.001 Total external power (PIO) PDCOUT PACOUT Total Power Calculation Altera Devices Estimated total power (PEST) PEST PINT Calculating Maximum Allowed Power Device Package Thermal resistance device Maximum junction temperature (TJ) specified appropriate device family data sheet. Ambient temperature (TA) design Maximum power (PMAX) allowed device PMAX Comparing Maximum Power Allowed Estimated Power PEST PMAX? PMAX PEST 2,070.69 400.79
Thermal Management
following guidelines reduce power dissipation heat build-up application:
available low-power features device. turning Turbo Bitoff, Classicdevices individual macrocells 9000, 7000, 3000A devices configured lowpower operation, with only nominal increase propagation delays. Macrocells 9000, 7000, 3000A devices that need high-performance mode should low-power mode. Choose different device package. ceramic higher-pin-count package used. Ceramic packages dissipate more heat than plastic packages. Also, packages with higher counts dissipate more heat through connections printed circuit board (PCB). forced-air cooling and/or heat-sinking. Forced-air cooling improves efficiency convection cooling, which reduces surface temperature device. heat sink connected device significantly increases heat dissipation radiating heat metal mass.
Altera Corporation
Evaluating Power Altera Devices
Slow operation portions circuit. proportional frequency operation. Slowing parts circuit lowers hence reduces power. Altera devices provide global array clock sources registers. Signals that require high-speed operation slower array clock that significantly reduces system power consumption. Reduce number outputs. current required support pins device. Reducing number pins reduce current necessary device, thereby reduce power. Reduce amount circuitry device. Power depends amount internal logic that switches given time. Reducing amount logic device reduces current device. same effect achieved using larger device, which also provides increased heat dissipation maintains single-device solution. Choose different device family. Some device families consume less power than others. example, 7000 family provides more power-saving features than 5000 family. Classic family provides power-saving features low-density designs, low-speed designs consume less power when implemented FLEX devices. Modify design reduce power. Identify areas design that revised reduce power requirements. Common solutions include reducing number switching nodes and/or required logic, removing redundant unnecessary signals. assistance locating less obvious changes, contact Altera Applications (800) 800-EPLD.
Revision History
information contained Application Note (Evaluating Power Altera Devices) version supersedes information published previous versions. version 3.1, device Figure updated.
Altera Corporation
Operating Requirements Altera Devices
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (408) 3-ALTERA lit_req@altera.com
Altera, MAX, FLEX registered trademarks Altera Corporation. following trademarks Altera Corporation: Classic, 7000, 3000A, 9000, FineLine BGA, FLEX 10K, FLEX 8000, FLEX 6000, Turbo Bit. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Printed Recycled Paper.
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