AVDD LC2MOS 16-Bit Converter AD7701 FUNCTIONAL BLOCK DIAGRAM

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AVDD LC2MOS 16-Bit Converter AD7701 FUNCTIONAL BLOCK DIAGRAM

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FEATURES Monolithic 16-Bit 0.0015% Linearity Error On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter Corner Frequency +2.5 Analog Input Range kSPS Output Data Rate Flexible Serial Interface Ultralow Power APPLICATIONS Industrial Process Control Weigh Scales Portable Instrumentation Remote Data Acquisition
AVDD
LC2MOS 16-Bit Converter AD7701
FUNCTIONAL BLOCK DIAGRAM
DVDD AVSS DVSS
AD7701
CALIBRATION SRAM CALIBRATION MICROCONTROLLER
16-BIT CONVERTER ANALOG MODULATOR 6-POLE GAUSSIAN LOW-PASS DIGITAL FILTER
BP/UP
VREF
SLEEP
AGND
CLOCK GENERATOR SERIAL INTERFACE LOGIC SDATA SCLK
DGND
CLKIN
CLKOUT
MODE
DRDY
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7701 16-bit which uses sigma-delta conversion technique. analog input continuously sampled analog modulator whose mean output duty cycle proportional input signal. modulator output processed on-chip digital filter with six-pole Gaussian response, which updates output data register with 16-bit binary words word rates kHz. sampling rate, filter corner frequency output word rate master clock input that supplied externally, crystal-controlled onchip clock oscillator. inherent linearity excellent, endpoint accuracy ensured self-calibration zero full scale which initiated time. self-calibration scheme also extended null system offset gain errors input channel. output data accessed through flexible serial port, which asynchronous mode compatible with UARTs synchronous modes suitable interfacing shift registers serial ports industry-standard microcontrollers. CMOS construction insures power dissipation, power down mode reduces idle power consumption only
AD7701 offers 16-bit resolution coupled with outstanding 0.0015% accuracy. missing codes ensures true, usable, 16-bit dynamic range, removing need programmable gain level-setting circuitry. effects temperature drift eliminated on-chip self-calibration, which removes zero gain error. External circuits also included calibration loop remove system offsets gain errors. flexible synchronous/asynchronous interface allows AD7701 interface directly UARTs serial ports industry-standard microcontrollers. operating power consumption ultralow power standby mode make AD7701 ideal loop-powered remote sensing applications, battery-powered portable instruments.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7701-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity TMIN TMAX Differential Nonlinearity TMIN TMAX Positive Full-Scale Error3 Full-Scale Drift4 Unipolar Offset Error3 Unipolar Offset Drift4 Bipolar Zero Error3 Bipolar Zero Drift4 Bipolar Negative Full-Scale Error3 Bipolar Negative Full-Scale Drift4 Noise (Referred Output) DYNAMIC PERFORMANCE Sampling Frequency, Output Update Rate, fOUT Filter Corner Frequency, Settling Time 0.0007% SYSTEM CALIBRATION Positive Full-Scale Overrange Positive Full-Scale Overrange Negative Full-Scale Overrange Maximum Offset Calibration Range5, Unipolar Input Range Bipolar Input Range Input Span7 Versions2
AVDD DVDD AVSS DVSS VREF +2.5 fCLKIN 4.096 MHz; Bipolar Mode: MODE Source Resistance with AGND AIN, unless otherwise noted.)
Versions2 Units Test Conditions/Comments
0.0007 0.0015 0.125 0.13 Version) 0.25 (+3/-25 Version) 0.25 (+1.5/-12.5 Version) Version)
Bits Guaranteed Missing Codes
0.003 0.125 0.13 Version) 0.25 (+3/-25 Version) 0.25 (+1.5/-12.5 Version) Version)
fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF VREF -(VREF 0.1) -(VREF 0.1) -0.4 VREF +0.4 VREF VREF VREF +2.5
fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF VREF -(VREF 0.1) -(VREF 0.1) -0.4 VREF +0.4 VREF VREF VREF +2.5
Full-Scale Input Step Applies Unipolar Bipolar Ranges. After Calibration, VREF, Device Will Output (Unipolar) -VREF (Bipolar), Device Will Output
ANALOG INPUT Unipolar Input Range Bipolar Input Range Input Capacitance Input Bias Current1 LOGIC INPUTS Inputs Except CLKIN VINL, Input Voltage VINH, Input High Voltage CLKIN VINL, Input Voltage VINH, Input High Voltage IIN, Input Current LOGIC OUTPUTS VOL, Output Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance
Volts Volts
ISINK ISOURCE
DVDD
DVDD
REV.
AD7701
Parameter POWER REQUIREMENTS8 Power Supply Voltages Analog Positive Supply (AVDD) Digital Positive Supply (DVDD) Analog Negative Supply (AVSS) Digital Negative Supply (DVSS) Calibration Memory Retention Power Supply Voltage Power Supply Currents8 Analog Positive Supply (AIDD) Digital Positive Supply (DIDD) Analog Negative Supply (AISS) Digital Negative Supply (DISS) Power Supply Rejection9 Positive Supplies Negative Supplies Power Dissipation Normal Operation Standby Operation10 Versions2 Versions2 Units Test Conditions/Comments
4.5/5.5 4.5/AVDD -4.5/-5.5 -4.5/-5.5 Version)
4.5/5.5 4.5/AVDD -4.5/-5.5 -4.5/-5.5 Version)
min/V min/V min/V min/V SLEEP Logic Typically SLEEP Logic Typically Typically Typically Typically Typically 0.03
NOTES presents very high impedance dynamic load which varies with clock frequency. Temperature ranges follows: Versions; -40°C +85°C; Versions; -55°C +125°C. Apply after calibration temperature interest. Full-scale error applies both unipolar bipolar input ranges. Total drift over specified temperature range since calibration power-up This guaranteed design and/or characterization. Recalibration temperature will remove these errors. unipolar mode offset have negative value (-VREF) such that unipolar mode mimic bipolar mode operation. specifications input overrange input span apply additional constraints offset calibration range. unipolar mode, input span difference between full scale zero scale. bipolar mode, input span difference between positive negative full-scale points. When using less than maximum input span, span range placed anywhere within range (VREF +0.1) digital outputs unloaded. digital inputs CMOS levels. Applies bandwidth. PSRR will exceed digital filter. CLKIN stopped. digital inputs grounded. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
DVDD AGND -0.3 DVDD AVDD -0.3 +0.3 DVSS AGND +0.3 AVDD AGND -0.3 AVSS AGND +0.3 AGND DGND -0.3 +0.3 Digital Input Voltage DGND -0.3 DVDD +0.3 Analog Input Voltage AGND AVSS AVDD Input Current Except Supplies2 Operating Temperature Range Commercial Plastic Versions) -40°C +85°C
Industrial Cerdip Versions) -40°C +85°C Extended Cerdip Versions) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latch-up.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this device features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7701
FUNCTION DESCRIPTION
Mnemonic MODE
Description Selects Serial Interface Mode. MODE tied AD7701 will operate asynchronous communications (ac) mode. SCLK configured input, data transmitted bytes, each with start stop bits. MODE tied DGND, synchronous external clocking (SEC) mode selected. SCLK configured input, output appears without formatting, coming first. MODE tied AD7701 operates synchronous self-clocking (SSC) mode. SCLK configured output, with clock frequency fCLKlN/4 duty-cycle. Clock Output generate Internal Master Clock connecting crystal between CLKOUT CLKIN. external clock used, CLKOUT connected. Clock Input External Clock. System Calibration Pins. state these pins, when taken high, determines type calibration performed. Digital Ground. Ground reference digital signals. Digital Negative Supply, nominal. Analog Negative Supply, nominal. Analog Ground. Ground reference analog signals. Analog Input. Voltage Reference Input, +2.5 nominal. This determines value positive full-scale unipolar mode both positive negative full-scale bipolar mode. Sleep mode pin. When this taken low, AD7701 goes into low-power mode with typically power consumption. Bipolar/Unipolar Mode Pin. When this low, AD7701 configured unipolar input range going from AGND VREF. When high, AD7701 configured bipolar input range, VREF. Calibration Mode Pin. When taken high more than cycles, AD7701 reset performs calibration cycle when brought again. also used strobe synchronize operation several AD7701s. Analog Positive Supply, nominal. Digital Positive Supply, nominal. Chip Select Input. When brought low, AD7701 will begin transmit serial data format determined state MODE pin. Data Ready output. DRDY when valid data available output register. goes high after transmission word completed. also goes high four clock cycles when data word being loaded into output register, indicate that valid data available, irrespective whether data transmission complete not. Serial Clock Input/Output. SCLK configured input output, dependent type serial data transmission that been selected MODE pin. When configured output synchronous self-clocking mode, frequency fCLKIN/4 duty cycle 25%. Serial Data Output. AD7701's output data available this 16-bit serial word. transmission format determined state MODE pin.
ORDERING GUIDE
CLKOUT CLKIN SC1, DGND DVSS AVSS AGND VREF SLEEP BP/UP
AVDD DVDD DRDY
SCLK
SDATA
CONFIGURATIONS DIP, Cerdip, SOIC SSOP
MODE CLKOUT CLKIN DGND DVSS AVSS SDATA SCLK DRDY
MODE CLKOUT CLKIN DGND DVSS AVSS AGND VREF
Model
SDATA SCLK DRDY VIEW (Not Scale) DVDD AVDD BP/UP SLEEP
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C
Linearity Package Error FSR) Options* 0.003 0.0015 0.003 0.0015 0.003 0.003 0.0015 0.003 0.0015 N-20 N-20 R-20 R-20 RS-28 Q-20 Q-20 Q-20 Q-20
VIEW (Not Scale) DVDD AVDD BP/UP SLEEP
AD7701
AD7701
AGND VREF
AD7701AN AD7701BN AD7701AR AD7701BR AD7701ARS AD7701AQ AD7701BQ AD7701SQ AD7701TQ
CONNECT
NOTES Plastic DIP; Cerdip; SOIC; SSOP.
REV.
AD7701 TIMING CHARACTERISTICS1,
Parameter fCLKIN3, Limit TMIN, TMAX Versions) 1000 3/fCLKIN l/fCLKIN +200 (4/fCLKIN) +200 1000 3/fCLKIN l/fCLKIN +200 (4/fCLKIN) +200
(AVDD DVDD 10%; AVSS DVSS 10%; AGND DGND CLKIN 4.096 MHz; Input Levels: Logic Logic DVDD)
Conditions/Comments Master Clock Frequency: Internal Gate Oscillator Typically 4.096 Master Clock Frequency: Externally Supplied Digital Output Rise Time. Typically Digital Output Fall Time. Typically SC1, High Setup Time SC1, Hold Time After Goes High SLEEP High CLKIN High Setup Time Data Access Time Data Valid) SCLK Falling Edge Data Valid Delay typ) Data Setup Time. Typically SCLK High Pulse Width. Typically SCLK Pulse Width. Typically SCLK Rising Edge Hi-Z Delay (l/fCLKIN typ) High Hi-Z Delay Serial Clock Input Frequency SCLK Input High Pulse Width SCLK Pulse Width Data Access Time Data Valid). Typically SCLK Falling Edge Data Valid Delay. Typically High Hi-Z Delay SCLK Falling Edge Hi-Z Delay. Typically Setup Time. Typically Data Delay Time. Typically SCLK Falling Edge Hi-Z Delay. Typically
Limit TMIN, TMAX Versions) Units
Mode t108, Mode fSCLK t137, t1411 t158 t168 Mode
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Figures CLKIN Duty Cycle range 80%. CLKIN must supplied whenever AD7701 SLEEP mode. clock present this case, device draw higher current than specified possibly become uncalibrated. AD7701 production tested with CLKIN 4.096 MHz. guaranteed characterization operate kHz. Specified using points waveform interest. order synchronize several AD7701s together using SLEEP pin, this specification met. measured with load circuit Figure defined time required output cross t10, derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time quoted Timing Characteristics true relinquish time part such independent external loading capacitance. returned high before bits output, SDATA SCLK outputs will complete current data then high impedance. activated asynchronously DRDY, will recognized occurs when DRDY high four clock cycles. propagation delay time great CLKIN cycles plus guarantee proper clocking SDATA when using asynchronous SCLK input should taken high sooner than CLKIN cycles plus after goes low. SDATA clocked falling edge SCLK input.
REV.
AD7701
1.6mA
OUTPUT
CLKIN
+2.1V 100pF
SC1,
SLEEP
SC1,SC2 VALID
200µA
Figure Load Circuit Access Time Relinquish Time
Figure Calibration Control Timing
DRDY
Figure SLEEP Mode Timing
SDATA DATA VALID HI-Z
SDATA DATA VALID
HI-Z
SCLK
SDATA HI-Z
DB15 DB14
HI-Z
Figure Mode Data Hold Time
CLKIN
Figure Mode Data Hold Time
Figure Mode Timing Diagram
DRDY
SCLK HI-Z
SCLK
SDATA HI-Z DB15 DB14
SDATA
HI-Z
HI-Z START
STOP
HI-Z
STOP
HIGH BYTE
BYTE
Figure Mode Timing Diagram
Figure Mode Timing Diagram
TERMINOLOGY
LINEARITY ERROR BIPOLAR ZERO ERROR
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function Zero-Scale (not confused with Bipolar Zero), point below first code transition (000 001) Full-Scale, point above last code transition (111 111). error expressed percentage full scale.
DIFFERENTIAL LINEARITY ERROR
This deviation midscale transition (0111 1000 000) from ideal (AGND LSB) when operating bipolar mode. expressed microvolts.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This deviation first code transition from ideal (-VREF LSB), when operating bipolar mode. expressed microvolts.
POSITIVE FULL-SCALE OVERRANGE
This difference between code's actual width ideal LSB) width. Differential Linearity Error expressed LSBs. differential linearity specification less guarantees monotonicity.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Overrange amount overhead available handle input voltages greater than +VREF example, noise peaks excess voltages system gain errors system calibration routines) without introducing errors overloading analog modulator overflowing digital filter. expressed millivolts.
NEGATIVE FULL-SCALE OVERRANGE
Positive Full-Scale Error deviation last code transition (111 111) from ideal (VREF -3/2 LSBs). applies both positive negative analog input ranges expressed microvolts.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error deviation first code transition from ideal (AGND LSB) when operating unipolar mode. expressed microvolts.
This amount overhead available handle voltages below -VREF without overloading analog modulator overflowing digital filter. Note that analog input will accept negative voltage peaks even unipolar mode. overhead expressed millivolts.
REV.
AD7701
OFFSET CALIBRATION RANGE
system calibration modes (SC2 low) AD7701 calibrates offset with respect pin. Offset Calibration Range specification defines range voltages, expressed percentage VREF that AD7701 accept still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
AD7701 perform self-calibration using on-chip calibration microcontroller SRAM store calibration parameters. calibration cycle initiated time using control input. Other system components also included calibration loop remove offset gain errors input channel. battery operation, AD7701 also offers standby mode that reduces idle power consumption typically
THEORY OPERATION
This range voltages that AD7701 accept system calibration mode still calibrate full-scale correctly.
INPUT SPAN
system calibration schemes, voltages applied sequence AD7701's analog input define analog input range. input span specification defines minimum maximum input voltages from zero full-scale that AD7701 accept still calibrate gain accurately. input span expressed percentage VREF.
GENERAL DESCRIPTION
general block diagram sigma-delta shown Figure contains following elements. sample-hold amplifier. differential amplifier subtracter. analog low-pass filter. 1-bit converter (comparator). 1-bit DAC. digital low-pass filter. operation, analog signal sample subtracter, along with output 1-bit DAC. filtered difference signal comparator, whose output samples difference signal frequency many times that analog signal sampling frequency (oversampling).
ANALOG LOW-PASS FILTER COMPARATOR DIGITAL FILTER
AD7701 16-bit converter with on-chip digital filtering, intended measurement wide dynamic range, frequency signals such those representing chemical, physical biological processes. contains charge-balancing (sigma-delta) ADC, calibration microcontroller with on-chip static RAM, clock oscillator serial communications port. analog input signal AD7701 continuously sampled rate determined frequency master clock, CLKIN. charge-balancing converter (Sigma-Delta Modulator) converts sampled signal into digital pulse train whose duty cycle contains digital information. six-pole Gaussian digital low-pass filter processes output modulator updates 16-bit output register rate. output data read from serial port randomly periodically rate kHz.
ANALOG SUPPLY
DIGITAL DATA
Figure General Sigma-Delta
0.1µF 10µF AVDD VOLTAGE REFERENCE 2.5V VREF DVDD SLEEP MODE DRDY RANGE SELECT CALIBRATE BP/UP SCLK SDATA DATA READY READ (TRANSMIT) SERIAL CLOCK SERIAL DATA 0.1µF
Oversampling fundamental operation sigma-delta ADCs. Using quantization noise formula ADC: (6.02 number bits 1.76) 1-bit comparator yields 7.78 AD7701 samples input signal kHz, which spreads quantization noise from kHz. Since specified analog input bandwidth AD7701 only noise energy this bandwidth would only 1/800 total quantization noise, even noise energy spread evenly throughout spectrum. reduced still further analog filtering modulator loop, which shapes quantization noise spectrum move most noise energy frequencies above performance range conditioned 16-bit level this fashion. output comparator provides digital input 1-bit DAC, that system functions negative feedback loop that tries minimize difference signal. digital data that represents analog input voltage contained duty cycle pulse train appearing output comparator. retrieved parallel binary data word using digital filter.
AD7701
CLKIN ANALOG INPUT CLKOUT ANALOG GROUND 0.1µF AVSS ANALOG SUPPLY 0.1µF DVSS AGND DGND 0.1µF
10µF
Figure Typical System Connection Diagram
REV.
AD7701
Sigma-delta ADCs generally described order analog low-pass filter. simple example first order sigmadelta shown Figure This contains only first-order low-pass filter integrator. also illustrates derivation alternative name these devices: Charge-Balancing ADCs.
DIGITAL FILTER INTEGRATOR +VREF -VREF 1-BIT STROBED COMPARATOR CLOCK
FILTER CHARACTERISTICS
cutoff frequency digital filter fCLK /409600. maximum clock frequency 4.096 MHz, cutoff frequency filter output rate kHz. Figure shows filter frequency response. This 6-pole Gaussian response that provides rejection cutoff frequency. clock frequency halved give cutoff, rejection better than normalized s-domain pole-zero plot filter shown Figure response filter defined H(x) 0.693x2 0.240x4 0.0555x6 0.00962x8 0.00133x10 0.000154x12] -0.5 where: f/f3 fCLKIN/409600, frequency interest.
fCLK 4MHz GAIN fCLK 2MHz
Figure Basic Charge-Balancing
term charge-balancing comes from fact that this system negative feedback loop that tries keep charge integrator capacitor zero, balancing charge injected input voltage with charge injected 1-bit DAC. When analog input zero, only contribution integrator output comes from 1-bit DAC. charge integrator capacitor zero, output must spend half time half time Assuming ideal components, duty cycle comparator will 50%. When positive analog input applied, output 1-bit must spend larger proportion time duty cycle comparator increases. When negative input voltage applied, duty cycle decreases. AD7701 uses second-order sigma-delta modulator sophisticated digital filter that provides rolling average sampled output. After power-up there step change input voltage, there settling time that must elapse before valid data obtained.
DIGITAL FILTERING
-100 -120 fCLK 1MHz -140 -160 FREQUENCY
Figure Frequency Response AD7701 Filter
AD7701's digital filter behaves like similar analog filter, with minor differences. First, since digital filtering occurs after conversion process, remove noise injected during conversion process. Analog filtering cannot this. other hand, analog filtering remove noise superimposed analog signal before reaches ADC. Digital filtering cannot this noise peaks riding signals near full scale have potential saturate analog modulator digital filter, even though average value signal within limits. alleviate this problem, AD7701 overrange headroom built into sigma-delta modulator digital filter which allows overrange excursions noise signals larger than this, consideration should given analog input filtering, reducing gain input channel that full-scale input (2.5 gives only half-scale input AD7701 (1.25 This will provide overrange capability greater than 100% expense reducing dynamic range (50%).
S1,2 -1.4663 j1.8191
S3,4 -1.7553 j1.0005 S5,6 -1.8739 j0.32272
Figure Normalized Pole-Zero Plot AD7701 Filter
Since AD7701 contains this on-chip, low-pass filtering, there settling time associated with step function inputs, data will invalid after step change until settling time elapsed. AD7701 therefore unsuitable high speed multiplexing, where channels switched converted sequentially high rates, switching between channels cause step change input. Rather, intended distributed converter systems using channel. However, slow multiplexing AD7701 possible, provided that settling time allowed elapse before data channel accessed. REV.
AD7701
output settling AD7701 response step input change shown Figure Gaussian response fast settling with overshoot, worst-case settling time 0.0007% LSB) with 4.096 master clock frequency. input sampling frequency, output data rate, filter characteristics calibration time directly related master clock frequency fCLKIN ratios given specification table. Therefore, first step system design with AD7701 select master clock frequency suitable bandwidth output data rate required application. ANALOG INPUT RANGES AD7701 performs conversion relative externally supplied reference voltage, which allows easy interfacing ratiometric systems. addition, either unipolar bipolar input voltage range selected using BP/UP input. With tied low, input range unipolar span +VREF. With BP/UP tied high, input range bipolar span VREF. bipolar mode both positive negative full scale directly determined VREF. This offers superior tracking positive negative full scale better midscale (bipolar zero) stability than bipolar schemes that simply scale offset input range. digital output coding unipolar range Unipolar Binary; bipolar range Offset Binary. weights unipolar bipolar modes shown Table input voltages output codes unipolar bipolar ranges, using recommended +2.5 reference, shown Table
Table Weight Table (2.5 Reference Voltage)
PERCENT FINAL VALUE
TIME
Figure AD7701 Step Response
USING AD7701
SYSTEM DESIGN CONSIDERATIONS
AD7701 operates differently from successive approximation ADCs other integrating ADCs. Since samples signal continuously, like tracking ADC, there need start convert command. 16-bit output register updated rate, output read time, either synchronously asynchronously.
CLOCKING
Unipolar Mode LSBs 0.26 1.00 2.00 4.00 0.0004 0.0008 0.0015 0.0031 0.0061
Bipolar Mode LSBs 0.13 0.26 1.00 2.00 0.0002 0.0004 0.0008 0.0015 0.0031
AD7701 requires master clock input, which external TTL/CMOS compatible clock signal applied CLKIN (CLKOUT used). Alternatively, crystal correct frequency connected between CLKIN CLKOUT, when clock circuit will function crystalcontrolled oscillator.
Table Output Coding
Unipolar Mode Input Relative AGND +VREF +VREF +VREF +VREF/2 +VREF/2 +VREF/2 AGND AGND AGND
Input Volts
Bipolar Mode Input Relative AGND +VREF +VREF +VREF AGND AGND AGND
Input Volts
Output Data 1111 1111 1111 1111 1111 1111 1111 1110 1111 1111 1111 1101 1111 1111 1111 1100 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0000 0000 0000 0011 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000
+2.499943 +2.499905 +2.499867
+2.499886 +2.499810 +2.499733
+1.250019 +1.249981 +1.249943
+0.000038 -0.000038 -0.000114
+0.000095 +0.000057 +0.000019
-VREF -VREF -VREF
-2.499810 -2.499886 -2.499962
NOTES VREF +2.5 AGND Unipolar Mode, V/655536 0.000038 Bipolar Mode, V/65536 0.000076 Inputs voltages code transitions.
REV.
AD7701
INPUT SIGNAL CONDITIONING
Reference voltages from used with AD7701, with little degradation performance. Input ranges that cannot accommodated this range reference voltages achieved input signal conditioning. This take form gain accommodate smaller signal range, passive attenuation reduce larger input voltage range. Source Resistance passive attenuators used front AD7701, care must taken ensure that source impedance sufficiently low. AD7701 analog input with over input resistance. parallel with this there small dynamic load which varies with clock frequency (see Figure 13). Each time analog input sampled, capacitor draws charge packet maximum
filter added front AD7701 reduce high frequency noise. With external capacitor added from AGND, following equation will specify maximum allowable source resistance:
(Max) CLKIN
practical limit maximum value source resistance thermal (Johnson) noise. practical resistor modeled ideal (noiseless) resistor series with noise voltage source parallel with noise current source. kTRf Volts Amperes where: Boltzmann's constant (1.38 10-23 J/K) temperature degrees Kelvin 273). Active signal conditioning circuits such amps generally suffer from problems high source impedance. Their open loop output resistance normally only tens ohms and, case, most modern general purpose amps have sufficiently fast closed loop settling time this problem. Offset voltage amps eliminated system calibration routine. With wide dynamic range small size AD7701, noise also problem, digital filter will reject most broadband noise above cutoff frequency. However, certain applications there need analog input filtering.
Antialias Considerations
AD7701
CEXT 10pF 100mV AGND
Figure Equivalent Input Circuit Input Attenuator
from analog source with frequency fCLKIN/256. 4.096 CLKIN, this yields average current draw After each sample AD7701 allows clock periods input voltage settle. equation which defines settling time e-t/RC] where: final settled value, value input signal, value input source resistance, sample capacitor, equal 62/fCLKIN.
digital filter AD7701 does provide rejection integer multiples sampling frequency (nfCLKlN/256, where With 4.096 master clock there narrow bands kHz, kHz, kHz, etc., where noise passes unattenuated output. However, AD7701's high oversampling ratio these bands occupy only small fraction spectrum, most broadband noise filtered. reduction broadband noise given
eOUT 0.035
From this, following equation developed which gives maximum allowable source resistance, RS(MAX), error
(MAX
CLKIN (100mV
where: eOUT noise terms referred input filter corner frequency (fCLKIN/409600) sampling frequency (fCLKIN/256). Since ratio fCLKIN fixed, digital filter reduces broadband white noise 96.5% independent master clock frequency.
Provided source resistance less than this value, analog input will settle within desired error band requisite clock periods. Insufficient settling leads offset errors. These calibrated system calibration schemes. limit (0.25 bits) maximum offset voltage, then maximum allowable source resistance from above equation, assuming that there external stray capacitance.
-10-
REV.
AD7701
VOLTAGE REFERENCE CONNECTIONS GROUNDING SUPPLY DECOUPLING
voltage applied VREF defines analog input range. specified reference voltage AD7701 will operate with reference voltages from with little degradation performance. reference input presents exactly same dynamic load analog input, case reference input, source resistance long settling time introduce gain errors rather than offset errors. Fortunately, most precision references have sufficiently output impedance wide enough bandwidth settle within clock cycles.
AVDD
AGND ground reference voltage AD7701, completely independent DGND. noise riding AGND input with respect system analog ground will cause conversion errors. AGND should therefore used system ground also ground analog input reference voltage. analog digital power supplies AD7701 independent separately pinned out, minimize coupling between analog digital sections device. digital filter will provide rejections broadband noise power supplies, except integer multiples sampling frequency. Therefore, analog supplies should decoupled AGND using ceramic capacitors provide power supply noise rejections these frequencies. digital supplies should similarly decoupled DGND.
ACCURACY AUTOCALIBRATION
LT1019
AD7701
VREF
AGND
Figure Typical External Reference Connections
digital filter AD7701 removes noise from reference input, just does with noise analog input, same limitations apply regarding lack noise rejection integer multiples sampling frequency. reference noise problem, some voltage references offer noise reduction schemes using external capacitor. Alternatively, simple filter used, shown Figure
AVDD
Sigma-delta ADCs, like VFCs other integrating ADCs, contain source nonmonotonicity inherently offer no-missing-codes performance. AD7701 achieves excellent linearity 0.0007%) high quality, on-chip silicon dioxide capacitors, which have very capacitance/voltage coefficient. AD7701 offers self-calibration modes using on-chip calibration microcontroller SRAM. Table truth table calibration control inputs SC2. self-calibration mode, zero-scale calibrated against AGND full scale calibrated against VREF pin, remove internal errors. Note that bipolar mode AD7701 calibrates positive full scale midscale (bipolar zero).
AD580
VREF 100pF AGND
AD7701
system-calibration mode, AD7701 calibrates zero full scale voltages present analog input sequential steps. This allows system offsets and/or gain errors nulled out.
AD7701
MICRO COMPUTER
Figure Filtered Reference Input
SYSTEM SYSTEM ANALOG SIGNAL CONDITIONING
SCLK SDATA
same considerations apply this filter filter analog input. this case:
CLKIN (CIN
Figure Typical Connections System Calibration
where: fCLKIN master clock frequency VFSE maximum desired error volts.
typical system calibration scheme shown Figure normal operation analog signal AD7701 analog multiplexer. When system calibrated, first switched system multiplexer strobed high, with both high. then switched system strobed, with high. this way, effect error sources
REV.
-11-
AD7701
Table III. Calibration Truth Table
TYPE Self-Cal System Offset System Gain System Offset
ZERO REFERENCE AGND
REFERENCE VREF VREF
SEQUENCE Step Step Step Step
CALIBRATION TIME 3,145,655 Clock Cycles 1,052,599 Clock Cycles 1,068,813 Clock Cycles 2,117,389 Clock Cycles
NOTE DRDY remains high throughout calibration sequence. Self-Cal mode, DRDY falls once AD7701 settled analog input. other modes DRDY falls device begins settle.
between multiplexer AD7701 removed. amps other signal conditioning circuits used front AD7701, without worrying about their absolute gain offset errors. Note that absolute value reference supplied AD7701 longer important, provided adequate short-term stability between calibration cycles, full scale calibrated system reference. system offset errors important system gain errors not, then step system calibration performed with high low. this case, offset calibrated against AIN, which should connected system during calibration, full scale calibrated against AD7701's VREF input. System calibration schemes will yield better accuracy than selfcalibration, even there system errors. Using selfcalibration, errors arise mismatch source impedances between references during calibration (AGND VREF) analog input during normal operation. system calibration, source impedances inherently remain identical, such that theoretical limit system accuracy calibration resolution. practical limit noise floor AD7701. Note that system calibration, "REF does necessarily mean system ground zero volts. AD7701 calibrated measure between voltages that within calibration range deliberately making nonzero. example, +0.5 +2.5 unipolar span will between these limits.
CALIBRATION RANGE
type calibration cycle initiated determined inputs, accordance with Table III. power dissipation temperature drift AD7701 warm-up time required before initial calibration performed. However, system reference must have stabilized before calibration initiated.
POWER SUPPLY SEQUENCING
positive digital supply (DVDD) must never exceed positive analog supply (AVDD) more than Power supply sequencing therefore important. separate analog digital supplies used, care must taken ensure that analog supply powered first. also important that power applied AD7701 before signals VREF, logic input pins order avoid possibility latch-up. separate supplies used AD7701 system digital circuitry, then AD7701 should powered first. typical scheme powering AD7701 from single rails shown system connection diagram, Figure this circuit AVDD DVDD brought along separate tracks from same supply. Thus, there possibility digital supply coming before analog supply.
GROUNDING
AD7701 uses analog ground connection, AGND, measurement reference node. should used reference node both analog input signal reference voltage VREF pin. analog digital power supplies AD7701 pinned separately minimize coupling between analog digital sections chip. four supplies should decoupled separately their respective grounds shown Figure on-chip digital filtering AD7701 further enhances power supply rejection attenuating noise injected into conversion process.
SINGLE SUPPLY OPERATION
When designing system calibration schemes, care must taken ensure that worst-case system errors cause overrange headroom AD7701 exceeded. Although measurement error caused offset gain errors nulled out, actual error voltages will still present analog input cause overloading analog modulator overflow digital filter. With reference, maximum input voltage (+VREF mV), minimum input voltage (-VREF mV).
POWER-UP CALIBRATION
calibration cycle must carried after power-up initialize device consistent starting condition correct calibration. must held high least four clock cycles, after which calibration initiated falling edge takes maximum 3,145,655 clock cycles (approximately with 4.096 clock). Table III.
Figure shows circuit power AD7701 from single supply, using provide half supply reference point AGND DGND. digital pins referenced this point, level shifting required external digital communications. galvanic isolation required system, level shifting isolation both provided opto-isolators.
-12-
REV.
AD7701
0.1µF
SYNCHRONOUS SELF-CLOCKING MODE (SSC)
0.1µF
AVDD VREF
DVDD
AD7701
AD707 DGND
mode (MODE high) allows easy interfacing serial-parallel conversion circuits systems with parallel data communication. This mode allows interfacing 74XX299 Universal Shift registers without additional decoding. mode also used with microprocessors such 68HC11 68HC05, which allow external device clock their serial port. Figure shows timing diagram mode. Data clocked internally generated serial clock. AD7701 divides each sampling interval into sixteen distinct periods. Eight periods clock pulses analog settling eight periods clock pulses digital computation. status polled beginning each digital computation period. these times then SCLK will become active data word currently output register will transmitted, first. After been transmitted DRDY goes high SDATA goes three-state. having been brought low, taken high again time during data transmission, SDATA SCLK will three-state after current finishes. subsequently brought low, transmission will resume with next during subsequent digital computation period. transmission been initiated completed time next data word available, DRDY will high four clock cycles then again word loaded into output register. more detailed diagram data transmission mode shown Figure Data bits change falling edge SCLK valid rising edge SCLK.
AGND 0.1µF AVSS DVSS
0.1µF
Figure Single Supply Operation
SLEEP MODE
power standby mode initiated taking SLEEP input low, which shuts down analog digital circuits reduces power consumption calibration coefficients still retained memory, converter been quiescent, necessary wait filter settling time (507,904 cycles) before accessing output data.
DIGITAL INTERFACE
AD7701's serial communications port allows easy interfacing industry-standard microprocessors. Three different modes operations available, optimized different types interface.
1024 CLKIN CYCLES CLKIN CYCLES INTERNAL STATUS ANALOG SETTLING CLKIN CYCLES DRDY CLKIN CYCLES DIGITAL COMPUTATION DIGITAL COMPUTATION
POLLED HI-Z HI-Z
SCLK
SDATA
HI-Z
HI-Z
Figure Timing Diagram Data Transmission Mode
REV.
-13-
AD7701
SYNCHRONOUS EXTERNAL CLOCK MODE (SEC)
mode (MODE grounded) designed direct interface synchronous serial ports industry-standard microprocessors such COPS series, 68HC11 68HC05. mode also allows customized interfaces, using port pins, microprocessors that have direct with AD7701's other modes. shown Figure falling edge enables serial data output with initially valid. Subsequent data bits change falling edge externally supplied SCLK. After been transmitted, DRDY goes high SDATA goes three-state. AD7701 still transmitting data when data word becomes available, data word continues transmitted data lost.
taken high time during data transmission, SDATA SCLK will three-state immediately. returns low, AD7701 will continue transmission with same data bit. transmission been initiated completed time next data word becomes available, high, DRDY will return high four clock cycles, then fall word loaded into output register.
CLKIN CLKIN CYCLES DRDY
HI-Z
SDATA
DB15 (MSB)
DB14
(LSB)
HI-Z
HI-Z SCLK
HI-Z
Figure Mode Showing Data Timing Relative SCLK
DRDY
SCLK
SDATA
HI-Z
DB15 (MSB)
DB14
DB13
(LSB)
HI-Z
Figure Timing Diagram Mode
-14-
REV.
AD7701
ASYNCHRONOUS COMMUNICATIONS (AC) MODE DIGITAL NOISE OUTPUT LOADING
mode (MODE tied offers UARTcompatible interface which allows AD7701 transmit data asynchronously from remote locations. external SCLK sets baud rate data transmitted bytes UARTcompatible format. Using mode, AD7701 interfaced direct microprocessors with UART interfaces, such 8051 TMS70X2. Data transmission initiated going low. falling edge SCLK, AD7701 begins transmitting 8-bit data byte (DB8-DB15) with start stop bits, Figure SDATA output will then three-state. second byte transmitted bringing again transmitted same format first byte. UART baud rates typically compared AD7701's output update rate. data still being transmitted when data word becomes available, data will ignored. However, been taken high between bytes, when data word becomes available, AD7701 could update output register before second byte transmitted. this case, UART would receive first byte word instead second byte word. When using mode, care must obviously taken ensure that this does occur.
mentioned earlier, AD7701 divides internal timing into distinct phases, analog sampling settling digital computation. mode, data transmitted only during digital computation periods, minimize effects digital noise analog performance. modes data transmission externally controlled, this automatic safeguard does exist. Whatever mode operation used, resistive capacitive loads digital outputs should minimized order reduce crosstalk between analog digital portions circuit. this reason connection low-power CMOS logic such 4000 series families recommended. especially important minimize load SDATA mode, transmission this mode inherently asynchronous. mode AD7701 should synchronized digital system clock CLKIN.
SCLK
DRDY
HI-Z SDATA
START
DB14
DB15
STOP STOP START
STOP STOP
Figure Timing Diagram Asynchronous Communications Mode
REV.
-15-
AD7701
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Pin Plastic (N-20)
20-Lead SOIC (R-20)
C1432b-2-9/96
0.0291 (0.74) 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40)
0.280 (7.11) 0.240 (6.10)
0.2992 (7.60) 0.2914 (7.40)
1.060 (26.90) 0.925 (23.50) 0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
0.4193 (10.65) 0.3937 (10.00)
0.5118 (13.00) 0.4961 (12.60)
0.1043 (2.65) 0.0926 (2.35)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27)
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
20-Pin Cerdip (Q-20)
0.005 (0.13) 0.098 (2.49)
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37)
1.060 (26.92) 0.200 (5.08) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38)
0.311 (7.9) 0.301 (7.64)
0.150 (3.81)
0.015 (0.38) 0.008 (0.20)
SEATING PLANE
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
-16-
REV.
PRINTED U.S.A.

AVDD LC2MOS 16-Bit Converter AD7701 FUNCTIONAL BLOCK DIAGRAM

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