Quick AN046 PLUS153-10 available 20-pin 20-pin PLCC package.

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Quick AN046 PLUS153-10 available 20-pin 20-pin PLCC package.

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Philips Semiconductors Programmable Logic Products
Quick
AN046
PLUS153-10 available 20-pin 20-pin PLCC package. PLUS173-10 available 24-pin 28-pin PLCC package. Both parts have greater than 10ns. Both parts provide wide input product terms, whose outputs tied inputs terms gates) below. There restrictions this interconnect product terms feed terms. Thus each term accept from inputs without leaving chip signal "wrap around". outputs bi-directional, they traded inputs used. Finally, each output polarity configured (exclusive-OR fused) each independently 3-Stateable from separate product term (each) which identical rest. Although slightly slower (from pin) than 7.5ns 20L8 structures, following example demonstrates simple case 10ns faster than 7.5ns PAL.
Example Cache Update Inhibit
modern microsystem design been simple, fast RISC processors with quick cache single cycle high performance operation. Unfortunately even using cache control chips, exception handling results clumsy designs. This reasons simple, direct-mapped caches have also become popular. Exception handling often resolving transactions which occur with data items that non-cacheable. This occurs number ways first, EPROMs, devices special state registers cacheable items, they will never into cache memory. What happens when non-cacheable item referenced? cache controller will miss begin update cache. transaction must terminated before overlays device onto least recently used cache address. deal with transaction overlay problem straightforward recognize non-cacheable transactions intercept them before controller cleans house. problem this? Figure shows what might average engineering workstation. Each device (disk controller, controller, keyboard, printer, etc.) usually several internal registers each occupying unique address. With disks, LAN, modem printer, system could instantly exceed distinct registers. best assume large number. Enter PLUS173 such system. Each product term scattered over memory needed decodes summed into single output signal generating composite inhibit. This process takes less than 10ns devices. Using 20L8-7 requires trading resolution (number address bits resolved) feeding through chip multiple times, expanding devices passes 15ns 7.5ns device). Using keeps RISC design very clean fast.
3-State open collector resistive pull-up, enable fits well. These situations where attention signals come into processor. always necessary operate full speed. Operating slower speed brings about more economical compact system. This higher costs associated with fast memory greater board area wide memory configurations. Some software routines where slower performance acceptable include power initialization, diagnostic routines, some exception routines. When speed critical, 8-bit most economical compact because readily available byte wide PROMs RAMs. 68030 easily interfaced 32-bit ports because dynamically interprets port size during each cycle. Figure shows example interfacing both slow 200ns 8-bit EPROM fast 35ns 32-bit 68030. PLUS173-10 chosen high speed large number inputs outputs. EPROM occupies memory space 0-32K while occupies addresses 64-128K. Note that because upper memory address bits were decoded, memory arrays will also appear other addresses.
PROBLEM: 16-bit Data Compare Mode Compare 8-bit fields Mode Select bits Must fast!
Example Glue Collection
This first example illustration compressing glue logic. Figure shows piece logic which performs operations 8-bit numbers. These come from different registers system, from halves 16-bit bus. goal perform input operations (compare bytes mode multiplex other) 10ns. Using parts, this could have been done except there available device series. There 74150 device available, propagation delay 17ns. this will work. Figure shows solution using 7.5ns devices. Unfortunately, because architecture provides only seven product terms term (16L8-7) multiple signal passes required. This results solution needing over 20ns. might conjectured that 15ns 22V10 could make with product terms some outputs, doing would only provide output "point 15ns. Additional time needed make final signal. 10ns 22V10 could make spec, with additional 74F32 adding 4ns. Figure shows preferred solution single PLUS173 generating final function 10ns. Figures show pinout SNAP equations this solution.
SOLUTION
8-BIT COMPARE 74F521
74F32
Example Interfacing Mixed Memory Types
Other sections microprocessor system summation large number decoded terms. instance, interrupt request, request cycle extension WAIT line contenders large number decoded summed inputs. Some asserted some high polarity control vital. Some require
MODE
SELECT
16-BIT 74150
Figure
September 1993
Philips Semiconductors Programmable Logic Products
Quick
SOLUTION MAKE PALs 20L8-7.5 A[0.7] B[0.7] WASTED PINS FEEDBACK
PALs 20L8-7.5 16L8-7.5
COMPARE FUNCTION: (1st PASS (2nd PASS (3rd PASS 22.5ns
16L8-7.5 WASTED PINS SELECT 16L8-7.5 WASTED PINS MODE FUNCTION: (1st PASS (2nd PASS (3rd PASS 22.5ns
GATE EFFICIENCY: PALs GATES USED GATES WASTED RESULT: FAST ENOUGH; SLOWER THAN SOLUTION
Figure
SOLUTION MAKE PLUS173D A[0.7] B[0.7] S[0.3] MODE PLUS173-10 Package 10ns PACKAGE COMPARE FUNCTION: PRODUCT TERMS FUNCTION: PRODUCT TERMS INVERTERS: INCLUDED ORS: INCLUDED GATE EFFICIENCY: GATES USED GATES WASTED RESULT: BEST SOLUTION; PACKAGE MODE
Figure
Figure Comparator/MUX Program
September 1993
Philips Semiconductors Programmable Logic Products
Quick
MAIN MEMORY CACHE/CONTROLLER
@PINLIST a[0.7] b[0.7] s[0.3] MODE
32-BIT MICROPROCESSOR
COMPARE MISS ADDRESS UPDATE
CACHE
@GROUPS s[0.3]; @TRUTHTABLE @LOGIC EQUATIONS comp /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode /mode; (sel mode (sel (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode (sel mode;
UPDATE INHIBIT
DEVICES
ADDRESS
DISK
ADDRESS
DISK
UPDATE INHIBIT
ADDRESS
mode
ADDRESS
PRINTER
Figure Cache Update Inhibit Using
comp; @INPUT VECTORS @OUTPUT VECTORS @STATE VECTORS @TRANSITIONS
Figure SNAP Equation Listing September 1993
Philips Semiconductors Programmable Logic Products
Quick
F174
A0-A14
D31-D24
27C256 32KX8 EPROM
20MHz CLOCK GENERATION MC68030 D0-D31 A0-A31 UMCS LMCS LLCS EPCS 74F32 SIZ0 SIZ1 STERM DSACK0 SIZ0 SIZ1 PLUS173-10 ACK0 ACK1 DLYIN A2-A15 74F244
16Kx4 SRAMs
16Kx4 SRAMs
16Kx4 SRAMs
16Kx4 SRAMs
RMCS DSTRT UUCS
EPROM
Figure Example Interfacing Mixed Memory Types
September 1993
Philips Semiconductors Programmable Logic Products
Quick
DECODER INTERFACING SRAMa EPROMs MC68030. THIS DESIGN PLUS173 DEVICE
@PINLIST dlyin a[31.30] a[19.16] a[1.0] siz0 siz1 nrmcs dstrt nuucs numcs nlmcs nllcs nepcs nack[1.0] @LOGIC EQUATIONS "EPROM enable" nepcs /a31 /a30 /a19 /a17 nas; "start shift register during EPROM access" dstrt /a31 /a30 /a19 /a17 nas; "DSACKO after clock cycles EPROM access" nack0 (dlyin); "immediate STERM upon access" nack1 /a31 /a30 /a19 /a18 /a17 /a16); "Byte select signals writes" nuucs /a17 /a19 /a30 /a31); nuucs /siz0 /siz1 /siz0 /siz1 siz0 /siz1 /siz0 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31); /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31); /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31 /a17 /a19 /a30 /a31); /a17 /a19 /a30 /a31);
Package DLYIN NRMCS DSTRT NUUCS NUMCS NLMCS NLLCS NEPCS NACK1 NACK0 SIZ1
SIZ0
nlmcs
nllcs
siz0 siz1 siz0 /siz1 siz1
nrmcs
Figure Equations PLUS173 Shown Figure
September 1993

Quick AN046 PLUS153-10 available 20-pin 20-pin PLCC package.

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