High speed 8-bit parallel serial converter AN045 INTRODUCTIO

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High speed 8-bit parallel serial converter AN045 INTRODUCTIO

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High speed 8-bit parallel serial converter
AN045
INTRODUCTION
common function many systems convert parallel data into serial data stream. microcontroller programmed shift byte register port, this relatively slow procedure. simple pre-loadable shift register could perform basic conversion. However, function complete, additional circuitry perform handshaking control process required. entire function made into cost Programmable Logic Device (PLD), including control circuitry tailored meet specific application requirements.
DESCRIPTION
Figure shows desired waveforms typical implementation. First, reset signal initializes system this circuit. Next, parallel data serialized applied device, possibly from parallel port microcontroller, write strobe (WRS) signal pulsed. then raises flag (BUSY) puts data, time, output (SDAT) under control clock signal (CLK). Another output, (SCLK) inverted copy transmitting clock, ANDed with control signal, only active when data actually being sent. used receiving device clock serial data. does perform such
function? Preferably this design should into simple, cost device such 22V10 type PLD. 22V10 outputs which individually configured registered combinatorial. possible make input multiplexer circuit front eight D-type flip-flops. could then configured shift data load parallel data upon control signal clock. However, provide output control signal BUSY gate SCLK, 3-bit counter will required indicate when last data shifted out. That would bring total registers design eleven, more than 22V10 provides. Additionally, write strobe (WRS) short duration asynchronous signal, more circuitry still required synchronize with transmitting clock (CLK). Another method serializing data multiplexer this example) counter. counter controls which output from multiplexer. count zero connects input output, count connects ID1, This will work only parallel input data held stable throughout serialization process. this example, data applied from port microcontroller held stable until after BUSY signal transitions from high-to-low, multiplexer will work this case. 8-to-1 multiplexer will only output, while three-bit counter will
three outputs 22V10, which leaves with outputs other functions. Let's this technique implement this example. Additional outputs required signals BUSY, SCLK, some currently unspecified control signals. counter constructed very easily using SNAP syntax equation "COUNT.D=COUNT#1H;". (pound) symbol means addition, ".D" signifies input D-type flip-flop, "1H" hexadecimal. equation simply COUNT equals COUNT plus actual equation Figure contains another term, more that later. addition inputs flip-flops, necessary describe flip-flops clock reset connections. Those listed lines 57and Figure multiplexer also very easy describe using SNAP syntax Boolean equations. 8-to-1 multiplexer with output SDAT inputs ID7-ID0 SDAT (COUNT==0H) (COUNT==1H) (COUNT==2H) (COUNT==3H) (COUNT==4H) (COUNT==5H) (COUNT==6H) (COUNT==7H);
RESET
ID7.ID0
SCLK
SDAT
BUSY
ID7.ID0
SCLK SDAT
RESET
BUSY
Figure Desired Input Output Waveforms
October 1993
High speed 8-bit parallel serial converter
AN045
far, have counter multiplexer serialize data. process serialization begins with asynchronous pulse write strobe input (WRS). therefore necessary construct latch capture pulse then registers synchronize signal input clock. Figure shows desired operation intermediate signals extremely simple latch made with equation: /WRS Once with low, could never reset. additional signal named GATE, will used extra term latch reset From waveforms Figure table three signals constructed. GATE WRS,GATE
have signal which latches input strobe, need synchronize input clock. That done with flip-flop following flip-flop, GATE, described later. equation simply: "Z1.D=Z;" clocked rising edge CLK. Z1's output will high upon rising edge high. will upon rising edge low. According original waveforms Figure signal named BUSY required occur after falling edge following detected strobe (WRS). internal D-type flip-flops 22V10 only clocked rising edge clock, 22V10's internal flip-flops cannot used. However Boolean equation used describe this signal. times conditions when this signal high will noted from Figure Boolean expression generated. From Figure time BUSY should high. Therefore, term equation BUSY will "Z*Z1*/CLK". When both high low, then BUSY will high. This product term will keep BUSY high until time time BUSY should remain high adding product term "BUSY*Z1" keep high until time This product term actually becomes active long before time arrives, there will glitching output. Adding another product term "BUSY*GATE" will keep BUSY high from just after time through time until time T19. Finally, last product term "BUSY*CLK", keeps high until falling edge
clock. combined equation BUSY shown Figure lines through last signal described GATE. used control gating inverted clock output SCLK, also control already described signals BUSY GATE flip-flops inside 22V10, should only switch after rising edge input clock. goes high after first rising edge after BUSY goes high. Therefore, inputs GATE flip-flop BUSY. GATE should after COUNT reaches seven, equation "GATE.D BUSY /(COUNT==7H);" input GATE flip-flop will high when BUSY goes high COUNT equal Signal GATE also added each terms multiplexer equation added term counter equation. added multiplexer SDAT would unless actual data being sent added counter counter would only count when GATE high. This design used nine possible 22V10 outputs.The input RESET added many equations force proper initialization signals. From here just matter typing equations into SNAP, running simulation, generating JEDEC file downloading device programmer. Figure shows SNAP simulation results Figure shows associated simulation control language (SCL) file.
"next state" what value output should given current inputs current state From table, Karnough constructed (shown above) equation "Z=/WRS+Z*/GATE;" derived.
BUSY
GATE
COUNT
SCLK
SDAT
Figure Waveform Timing Relationships
October 1993
High speed 8-bit parallel serial converter
AN045
High Speed 8-bit Parallel Serial Converter |@PINLIST |CLK |ID[0.7] 1|CLK/I0 VCC|24] |RESET "active low" RESET 2|I1 I/O9|23] |WRS 3|I2 I/O8|22] |BUSY 4|I3 I/O7|21] |SCLK 5|I4 I/O6|20] SDAT |SDAT 6|I5 I/O5|19] SCLK |C[0.2] 7|I6 I/O4|18] GATE |GATE 8|I7 I/O3|17] 9|I8 I/O2|16] [10|I9 I/O1|15] [11|I10 I/O0|14] BUSY |@GROUPS [12|GND I11|13] |COUNT=[C2,C1,C0]; |@TRUTHTABLE |@LOGIC EQUATIONS "write strobe latch" /WRS*reset+Z*/GATE*reset; "first flip-flop sychronize CLK" |Z1.D |Z1.CLK CLK; |Z1.RST reset; "busy flag" |BUSY Z*Z1*/CLK*reset BUSY*Z1*reset BUSY*GATE*reset BUSY*CLK*reset; "gate control synchronizing flip-flop" |GATE.D BUSY*/(COUNT==7H); |GATE.CLK CLK; |GATE.RST reset; "output clock" |SCLK /CLK*GATE; "3-bit counter" |COUNT.D GATE==1 COUNT#1H; "count only when GATE high" |COUNT.CLK CLK; |COUNT.RST reset; "Multiplexer Equations" |SDAT ID0*(COUNT==0H)*GATE*reset GATE then output low" ID1*(COUNT==1H)*GATE*reset ID2*(COUNT==2H)*GATE*reset ID3*(COUNT==3H)*GATE*reset ID4*(COUNT==4H)*GATE*reset ID5*(COUNT==5H)*GATE*reset ID6*(COUNT==6H)*GATE*reset ID7*(COUNT==7H)*GATE*reset; |@INPUT VECTORS |@OUTPUT VECTORS |@STATE VECTORS NOTE: Line numbers reference only, they |@TRANSITIONS part design file. Figure SNAP Listing File
October 1993
High speed 8-bit parallel serial converter
AN045
File: SHIFT.RES <Model> RESET BUSY GATE SCLK SDAT C[2.0]
DELAY
Marker
Sec/Div 200ns
1000
1400
1800
2200
Philips Semiconductors 1993 MODE Figure SNAP Simulation Waveforms
HELP, EXIT
Output Waveform Version 1.90 Date: 04/21/93 Time: 16:14:48 Input File Name SHIFT.SCL Rule File Name Rule Output File Name SHIFT.SCL ID0, ID1, ID2, ID3, ID4, ID5, ID6, ID7, CLK, RESET, WRS, BUSY, GATE, SCLK, SDAT, C[2.0], (5890) (5890) (5890) (5890) (5890) (5890) (9200) (14290) (100, 200, ETC) (80, 5600, 6000) RESET (180, 240, 4000, 4200) time 14290 Figure SNAP Simulation File
October 1993

High speed 8-bit parallel serial converter AN045 INTRODUCTIO

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