Altera Devices 1999, ver. Introduction output edge-trig

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Altera Devices 1999, ver. Introduction output edge-trig

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Metastability
Altera Devices
1999, ver.
Introduction
output edge-triggered flipflop valid states: high low. ensure reliable operation, designs must meet flipflop's timing requirements. input flipflop must stable minimum time before clock edge (register setup time tSU) minimum time after clock edge (register hold time tH). Specific values provided each device family data sheet this data book, they determined using MAX+PLUS® Timing Analyzer. non-synchronous systems, asynchronous input signals violate flipflop's timing requirements, output flipflop become metastable. Metastable outputs oscillate hover between high states brief period time, which cause system failure. Therefore, must analyze metastability characteristics device determine reliability non-synchronous design. synchronous systems, input signals always meet flipflop's timing requirements; therefore, metastability does occur. This application note describes metastability, quantified, minimize effect. also includes metastability data Altera® FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000, 7000 devices that used estimate system's mean time between failures (MTBF) when using these devices synchronize asynchronous data.
Metastability
Violating flipflop's setup hold time cause output become metastable. When flipflop metastable ("in between") state, output hovers voltage level between high low, causing output transition delayed beyond specified clock-to-output delay (tCO). additional time beyond that metastable output takes resolve stable state called settling time (tMET). every transition that violates setup hold times results metastable output. likelihood that flipflop enters metastable state time required return stable state varies depending process technology used manufacture device ambient conditions. Generally, flipflops will quickly return stable state (see Figure
Altera Corporation
A-AN-042-04
Metastability Altera Devices
Figure Metastability Timing Parameters
DATA
tMET
operation register analogous ball rolling over frictionless hill, shown Figure Each side hill represents stable (i.e., high low) state, hill represents metastable state. When flipflop's data input complies with minimum setup (tSU) hold (tH) times, output passes from stable state another (i.e., from high high) without additional delay. Analogously, ball travels over hill within specified time given enough push. However, when flipflop's data input violates setup hold time, flipflop marginally triggered, output immediately resolve either stable states within specified time. This marginal triggering cause output glitch remain temporarily metastable state between high logic levels, taking longer return stable state. Either condition increases delay from clock transition stable output.
Figure Effects Violating Requirements
Metastable State Metastable State
Stable
Stable
Stable
Stable
Output glitches.
Output temporarily remains metastable state return either stable state, incurring additional delays.
Altera Corporation
Metastability Altera Devices
Metastability does necessarily cause unpredictable system performance. wait time sufficient allow flipflop settle stable state, metastability does affect system; output flipflop temporarily have undefined value, provided that returns known value before signal evaluated. Therefore, allowing additional time (tMET) signal settle known state prevents propagation undefined value rest system.
Analyzing Metastability
MTBF value quantitatively shows metastability affects your design. MTBF provides estimate mean time between probable occurrence successive metastable events. MTBF synchronizing flipflop estimated with following formula: MTBF CLOCK DATA fCLOCK parameter refers system clock frequency while fDATA parameter refers data transfer frequency. tMET parameter additional time allowed system flipflop settle stable state. constants vary according process technology used manufacture device. Therefore, different devices manufactured with same process have similar values constants determined plotting natural MTBF versus tMET performing linear regression analysis data. intercept slope resulting line determine values formulas constants shown below: MTBF -MTBF CLOCK DATA Figure shows relationship between MTBF tMET shows changing system frequency affects this relationship.
Device Operation
Altera Corporation
Metastability Altera Devices
Figure MTBF tMET
Years
Increasing Clock Frequency
Year
Month Week
MTBF (Seconds)
Hour
Minute
tMET (ns)
constant scales MTBF equation linearly, shifting entire curve down. constant affects slope MTBF tMET curve. Increasing clock frequency shifts entire curve right, lowering MTBF value given settling time. Once values determined particular device, MTBF equation shown page calculate MTBF system with given settling time (tMET). tMET delay additional time required flipflop resolve legal state, i.e. difference between minimum system clock period actual clock period. also metastability equation determine tMET delay required given MTBF value, shown below: MTBF CLOCK DATA
Altera Corporation
Metastability Altera Devices
Test Circuitry
Figure shows test circuit used determine metastability characteristics Altera devices. this figure, flipflop asynchronous clock data inputs. logic that generates metastable event logic that detects both located device under test (DUT). output synchronizing flipflop directly resolving flipflops through inverter other resolving flipflop. outputs resolving flipflops feed XNOR gate that high logic level when values outputs (the signal complement) same. resolving flipflops detect that signal complement have same logical value, metastable event occurred counter incremented.
Device Operation
Figure Metastability Test Circuit
logic part device under test.
data
Resolving Flipflops
CLRN
CLRN
16-Bit Counter Synchronizing Flipflop
Display
CLRN CLRN
Because resolving flipflops clocked falling clock edge, required settling time controlled changing clock high time (t). settling time tMET determined with equation below. tACNT delay minimum clock period, which equal minimum delay from clock edge output synchronizing flipflop, plus delay from output synchronizing flipflop input resolving flipflops, plus setup time resolving flipflop. tMET parameter minimum time allowed under normal operation circuit: ACNT
Altera Corporation
Metastability Altera Devices
Metastability Characteristics Altera Devices
Figure shows metastability characteristics FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices. devices, fDATA fCLOCK MHz.
Figure Metastability Characteristics Altera Devices
1011 1010
FLEX 10K, FLEX 8000 FLEX 6000 9000 7000
Years
Year
Month
MTBF Week (Seconds)
Hour
Minute
tMET (ns)
Table summarizes values Altera's FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices.
Altera Corporation
Metastability Altera Devices
Table Metastability Equation Constants
Device
FLEX FLEX 8000 FLEX 6000 9000 7000
1.01 1.01 1.01 2.98 10-13 10-13 10-13 10-17
1.268 1010 1.268 1010 1.268 1010 5.023 5.023
2.98 10-17
Applying Metastability Equation
values listed Table calculate MTBF specific settling time, calculate minimum settling time specific MTBF. example, equation below calculates tMET needed ensure MTBF year (approximately seconds) EPF8452A device with data frequency clock frequency MHz. 1.01 1.41 1.268 When MTBF year required, 1.41 should added clock-to-output delay (tCO) synchronizing flipflop when performing timing analysis. logarithmic relationship between MTBF tMET, small changes tMET dramatically affect MTBF. required MTBF increases from year years example shown above, tMET delay increases only 1.59 Figures show tMET delay required FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices when fDATA half fCLOCK. Because MTBF inversely proportional value (fCLOCK fDATA), these figures used find MTBF many designs. Metastability probabilistic, MTBF values mean values calculated limited sample devices should only used estimate tMET delays.
Device Operation
Altera Corporation
Metastability Altera Devices
Figure FLEX 10K, FLEX 8000 FLEX 6000 MTBF Values
1011
1,000 Years
1010
Years
Years
Year
Month MTBF Week (Seconds)
fCLK fCLK fCLK fCLK
Hour
Minute
tMET (ns)
Altera Corporation
Metastability Altera Devices
Figure 9000 7000 MTBF Values
1011
1,000 Years
1010
Years
Years
Year
Device Operation
fCLK fCLK fCLK fCLK
MTBF (Seconds)
Month Week Hour
Minute
tMET (ns)
Avoiding Metastability
Several techniques used reduce metastability system. asynchronous signal several flipflops, probability that metastable event will occur greatly increases because there more flipflops that could become metastable. this case, avoid metastability using output synchronizing flipflop throughout system rather than asynchronous signal. also avoid negative effects metastability adding tMET calculated specific MTBF worst-case timing delay calculations, giving output synchronizing flipflops time settle. Faster devices provide faster times, which provide additional time tMET delay without sacrificing overall system speed.
Altera Corporation
Metastability Altera Devices
reduce effects metastability, designers most commonly multiple-stage synchronizer which more flipflops cascaded form synchronization circuit (see Figure synchronizing flipflop produces metastable output, metastable signal resolve before clocked second flipflop. This method does guarantee that second flipflop will clock undefined value, dramatically increases probability that data will valid state before reaches rest circuit.
Figure Multiple-Stage Synchronizer
asynch
CLRN
CLRN
drawback multiple-stage synchronizer that takes longer system respond asynchronous input. solution this problem output ClockBoostclock doubler clock synchronizing flipflops. Figure This approach allows system respond asynchronous input within system clock cycle, while still improving MTBF. Although ClockBoost clock could decrease MTBF, this effect more than offset synchronizing flipflops.
Figure Multiple-Stage Synchronizer with ClockBoost Circuitry
Synchronizing Registers
asynch
Rest Circuit
CLRN
CLRN
clkx2 (From ClockBoost Circuit) Rest Circuit
Conclusion
Metastability phenomenon that only affects flipflops used synchronize data from asynchronous systems. metastability characteristics particular device depend process technology used manufacture device ambient conditions. Altera devices have very good metastability characteristics; only need small tMET delay delay achieve high MTBF value.
Altera Corporation

Altera Devices 1999, ver. Introduction output edge-trig

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