Altera Devices September 2000, ver. 4.05 Introduction p

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IEEE 1149.1 (JTAG) Boundary-Scan Testing
Altera Devices
September 2000, ver. 4.05
Introduction
printed circuit boards (PCBs) become more complex, need thorough testing becomes increasingly important. Advances surfacemount packaging manufacturing have resulted smaller boards, making traditional test methods-e.g., external test probes "bed-of-nails" test fixtures-harder implement. result, cost savings from space reductions sometimes offset cost increases traditional testing methods. 1980s, Joint Test Action Group (JTAG) developed specification boundary-scan testing that later standardized IEEE Std. 1149.1 specification. This boundary-scan test (BST) architecture offers capability efficiently test components PCBs with tight lead spacing. This architecture test connections without using physical test probes capture functional data while device operating normally. Boundary-scan cells device force signals onto pins, capture data from core logic signals. Forced test data serially shifted into boundary-scan cells. Captured data serially shifted externally compared expected results. Figure illustrates concept boundary-scan testing. Figure IEEE Std. 1149.1 Boundary-Scan Testing
Boundary-Scan Cell
Serial Data
Signal
Serial Data
Core Logic
Core Logic
Interconnection Tested
JTAG Device JTAG Device
Table summarizes Altera® devices that comply with IEEE Std. 1149.1 specification providing capability input, output, dedicated configuration pins.
Altera Corporation
A-AN-039-04.05
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Table Altera Devices with Capability Family
APEX 20K, APEX 20KE ACEX FLEX® 10K, FLEX 10KE FLEX 8000 FLEX 6000 MAX® 9000 (including 9000A) 7000S 7000A 7000B 3000A Note:
EPM7032S, EPM7064S, EPM7096S devices contain IEEE Std. 1149.1 controller in-system programming. However, these devices support BST.
Devices Supporting
devices devices devices EPF8282A, EPF8282AV, EPF8636A, EPF8820A, EPF81500A devices devices EPM7128S, EPM7160S, EPM7192S, EPM7256S devices devices devices
This application note discusses IEEE Std. 1149.1 circuitry Altera devices. topics follows:
IEEE Std. 1149.1 architecture IEEE Std. 1149.1 boundary-scan register IEEE Std. 1149.1 operation control Enabling IEEE Std. 1149.1 circuitry Guidelines IEEE Std. 1149.1 boundary-scan testing Boundary-Scan Description Language (BSDL) support References
addition BST, IEEE Std. 1149.1 controller insystem programming 9000 (including 9000A), 7000S, 7000A, 7000B, 3000A devices in-circuit reconfiguration APEX 20K, ACEX FLEX devices. This application note only discusses feature IEEE Std. 1149.1 circuitry.
more information using IEEE Std. 1149.1 circuitry in-system programming in-circuit reconfiguration, following documents:
Application Note (Configuring FLEX 8000 Devices) Application Note (Configuring Multiple FLEX 8000 Devices) Application Note (In-System Programmability Devices) Application Note (Configuring APEX 20K, FLEX FLEX 6000 Devices)
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
IEEE Std. 1149.1 Architecture
device operating IEEE Std. 1149.1 mode uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. Table summarizes functions each these pins. Table IEEE Std. 1149.1 Descriptions
Description
Test data input
Function
Serial input instructions well test programming data. Data shifted rising edge TCK.
Test data output Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. Test mode select Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. Test clock input clock input circuitry. Some operations occur rising edge, while others occur falling edge. Active-low input asynchronously reset boundary-scan circuit. This only available certain APEX 20K, ACEX FLEX 10K, FLEX 8000 devices (TRST optional according IEEE Std. 1149.1).
TRST
Test reset input (optional)
APEX 20K, ACEX FLEX 9000 devices have pins dedicated IEEE Std. 1149.1 operation. EPF8820A, EPF8636A, EPF8282A, EPF8282AV, FLEX 6000, 7000S, 7000A, 7000B, 3000A devices, four JTAG pins pins turning JTAG option with MAX+PLUS software (see "Enabling IEEE Std. 1149.1 Circuitry" page this application note). Certain APEX 20K, ACEX FLEX 10K, FLEX 8000 JTAG devices have optional TRST pin. appropriate device family data sheet specific information device package combinations.
IEEE Std. 1149.1 circuitry requires following registers:
instruction register which used determine action performed data register accessed.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
bypass register which 1-bit-long data register used provide minimum-length serial path between TDO. boundary-scan register which shift register composed boundary-scan cells device.
Figure shows functional model IEEE Std. 1149.1 circuitry. Figure IEEE Std. 1149.1 Circuitry
Instruction Register UPDATEIR CLOCKIR SHIFTIR
TCLK
Controller
UPDATEDR CLOCKDR SHIFTDR
Instruction Decode
Data Registers Bypass Register
TRST
Boundary-Scan Register
Device Register
ISP/ICR Registers
Notes:
TRST available APEX 20K, ACEX some FLEX devices. device register available JTAG-compliant families except EPM9320 EPM9560 devices. private registers used in-system programmability (ISP) 9000 (including 9000A), 7000A, 7000B, 7000S, 3000A devices in-circuit reconfigurability (ICR) APEX 20K, ACEX FLEX devices. Refer appropriate device family data sheet register lengths.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
IEEE Std. 1149.1 boundary-scan testing controlled Test Access Port (TAP) Controller, which described "IEEE Std. 1149.1 Std. Operation Control" page this application note. TMS, TRST, pins operate controller, pins provide serial path data registers. also provides data instruction register, which then generates control logic data registers.
IEEE Std. 1149.1 Boundary-Scan Register
boundary-scan register large serial shift register that uses input output. boundary-scan register consists 3-bit peripheral elements that either pins (all devices), dedicated inputs (all devices), dedicated configuration pins (APEX, ACEX, FLEX devices). boundary-scan register test external connections capture internal data. Figure shows test data serially shifted around periphery IEEE Std. 1149.1 device. Figure Boundary-Scan Register
Internal Logic
Each peripheral element either pin, dedicated input pin, dedicated configuration pin.
Controller
TRST
Note:
TRST available APEX 20K, ACEX some FLEX devices.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
3-bit boundary-scan cell (BSC) consists capture registers update registers each pin. capture registers connect internal device data OUTJ, OEJ, signals, while update registers connect external data through tri-state data input, tri-state control, signals. control signals IEEE Std. 1149.1 registers (e.g., SHIFT, CLOCK, UPDATE) generated internally controller; MODE signal generated decode instruction registers. data signal path boundary-scan register runs from serial data (SDI) signal serial data (SDO) signal. scan register begins ends device. Figure shows BSCs associated with each APEX 20K, ACEX FLEX 10K, FLEX 8000 devices. Figure APEX 20K, ACEX FLEX FLEX 8000 Pins with IEEE Std. 1149.1 Circuitry
Controls
Column Interconnect
(10)
(12)
from Column Interconnect
CLRN
OUTJ
SlewRate Control
MODE
Capture Registers
SHIFT CLOCK
Update Registers
UPDATE
Element Cell Circuitry
JTAG Circuitry
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure shows BSCs associated with each 9000 devices. Figure 9000 Pins with IEEE Std. 1149.1 Circuitry
Controls
Column Interconnect
(10)
(12)
from Column Interconnect
CLRN
OUTJ
SlewRate Control
MODE
Capture Registers
SHIFT CLOCK
Update Registers
UPDATE
Element Cell Circuitry
JTAG Circuitry
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure shows BSCs that associated with each FLEX 6000 devices. Figure FLEX 6000 Pins with IEEE Std. 1149.1 Circuitry
Chip-Wide Output Enable
from Local Interconnect
Column Interconnect
from Local Interconnect
OUTJ
SlewRate Control
MODE
Capture Registers
SHIFT CLOCK
Update Registers
UPDATE
Control Block
Circuitry
Figure shows BSCs that associated with each 7000S, 7000A, 7000B, 3000A devices. BSCs Figure similar BSCs other device families, except input portion does contain update register.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure 7000S, 7000A, 7000B 3000A Pins with IEEE Std. 1149.1 Circuitry
Control Signals
from Macrocell
OUTJ
SlewRate Control
MODE
Capture Registers
SHIFT CLOCK
Update Registers
UPDATE
Control Block
JTAG Circuitry
Dedicated Input
boundary-scan register also includes dedicated input pins. Because these pins have special functions, some bits boundary-scan register internally connected ground, used only device configuration; these bits either forced static high state, used internally configuration. Figure shows BSCs dedicated input pins APEX, ACEX, FLEX devices. register normally associated with output signal, OUTJ, tied ground, tri-state control, OEJ, connected VCC. signal data from dedicated input only register that contains test data. data shifts order where data associated with dedicated input. Because only valid data, scan test pattern must either ignore expect that follow bit.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure APEX, ACEX FLEX Dedicated Input Pins with IEEE Std. 1149.1 Circuitry
Internal Logic
Dedicated Input
Update Register
Capture Registers
SHIFT CLOCK UPDATE MODE
Figure shows BSCs dedicated input devices. update registers BSCs disabled, registers normally associated with output signals OUTJ connected ground VCC, respectively. When shifting data BSCs, OUTJ should ignored.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure Dedicated Input Pins with IEEE Std. 1149.1 Circuitry
Dedicated Input
Internal Logic
Capture Registers
SHIFT CLOCK
Dedicated Clock Pins (APEX 20K, ACEX FLEX 10K)
boundary-scan register also includes dedicated clock pins. Because these pins have special functions, some bits boundary-scan register internally connected ground before configuration; these bits thus forced static high state. Figure shows BSCs dedicated clock pins APEX 20K, ACEX FLEX devices. These pins continue clock internal user registers, capture register associated with used external connectivity tests. receive data cannot force data onto external connections. data values associated with other capture registers should ignored.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure APEX, ACEX FLEX Dedicated Clock Pins with IEEE Std. 1149.1 Circuitry
Internal Controls Dedicated Clock Pins
Capture Registers
SHIFT CLOCK
Dedicated Configuration (All APEX, ACEX FLEX Devices)
APEX 20K, ACEX FLEX boundary-scan register includes dedicated configuration pins. Because these pins have special functions, some bits boundary-scan register internally connected ground, used only device configuration; these bits either forced static high state, used internally configuration. Figure shows peripheral elements associated with APEX, ACEX, FLEX dedicated configuration pins (i.e., nCONFIG, MSEL0, MSEL1, nSP, CONF_DONE, nSTATUS, DCLK). These pins used only during device configuration, capture register associated with used external connectivity tests. receive data cannot force data onto external connections. data values associated with other capture registers should ignored.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure APEX, ACEX FLEX Dedicated Configuration Pins with IEEE Std. 1149.1 Circuitry (Part
Input Configuration Pins Internal Controls
Note
Capture Registers
SHIFT CLOCK
Open-Drain Configuration Pins Internal Controls
Note
from Internal Controls
Capture Registers
SHIFT CLOCK
Notes:
APEX, ACEX, FLEX devices, these pins include nCONFIG, MSEL0, MSEL1, nCE, DCLK; FLEX 8000 devices, these pins include nCONFIG, nSP, MSEL0, MSEL1, FLEX 6000 devices, these pins include nCONFIG, MSEL, nCE, DCLK. These pins include CONF_DONE nSTATUS.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure APEX, ACEX FLEX Dedicated Configuration Pins with IEEE Std. 1149.1 Circuitry (Part
Bi-Directional Configuration Pins Internal Controls
Note
from Internal Controls
from Internal Controls
Capture Registers
SHIFT CLOCK
Output Configuration Pins
Note
from Internal Controls
Capture Registers
SHIFT CLOCK
Notes:
FLEX 8000 devices, these pins include DCLK DATA. APEX 20K, ACEX FLEX 10K, FLEX 6000 devices, these pins include nCEO.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
IEEE Std. 1149.1 Std. Operation Control
Altera IEEE Std. 1149.1 devices implement following instructions: SAMPLE/PRELOAD, EXTEST, BYPASS, USERCODE, IDCODE. Table summarizes instructions, which described detail later this application note.
Table Boundary-Scan Instructions Mode FLEX APEX ACEX
SAMPLE/ PRELOAD 0001010101
Instruction Code FLEX 8000 FLEX 6000 9000 9000A 7000S 7000A 7000B 3000A
Description
0001010101
0001010101 Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. 000000000 Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins.
EXTEST
0000000000
0000000000
BYPASS
1111111111
1111111111
1111111111 Places 1-bit bypass register between pins, which allows data pass synchronously through selected device adjacent devices during normal device operation. 0001011001 Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. 0000000111 Selects USERCODE register places between TDO, allowing USERCODE serially shifted TDO.
IDCODE
0000000110
0001011001
USERCODE
0000000111
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices Notes table:
EPM7032S, EPM7064S, EPM7096S devices support IEEE Std. 1149.1 BST. However, these devices have BYPASS mode that allows them pass IEEE Std. 1149.1 information other devices scan chain that supports IEEE Std. 1149.1 BST. 7000S devices support optional USERCODE instruction. However, 7000S devices offer 16-bit UESCODE register that serves same purpose. IDCODE available 9000 (including 9000A) devices except early versions EPM9320 EPM9560 devices.
IEEE Std. 1149.1 test access port (TAP) controller, 16-state state machine clocked rising edge TCK, uses control IEEE Std. 1149.1 operation device. Figure shows controller state machine.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure IEEE Std. 1149.1 Controller State Machine
TEST_LOGIC/ RESET
RUN_TEST/ IDLE
SELECT_DR_SCAN
SELECT_IR_SCAN
CAPTURE_DR
CAPTURE_IR
SHIFT_DR
SHIFT_IR
EXIT1_DR
EXIT1_IR
PAUSE_DR
PAUSE_IR
EXIT2_DR
EXIT2_IR
UPDATE_DR
UPDATE_IR
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
When controller TEST_LOGIC/RESET state, circuitry disabled, device normal operation, instruction register initialized. device supports IDCODE, this initial instruction IDCODE; otherwise, BYPASS. device power-up, controller starts this TEST_LOGIC/RESET state. addition, controller forced TEST_LOGIC/RESET state holding high five clock cycles holding TRST optional TRST supported.) Once TEST_LOGIC/RESET state, controller remains this state long continues held high while clocked TRST continues held low. Figure shows timing requirements IEEE Std. 1149.1 signals. Figure IEEE Std. 1149.1 Timing Waveforms
tJCP tJCH tJCL tJPSU tJPH
tJPZX tJPCO tJPXZ
tJSSU tJSH
Signal Captured Signal Driven
tJSZX
tJSCO
tJSXZ
timing values each Altera device provided appropriate device family data sheet. start IEEE Std. 1149.1 operation, select instruction mode advancing controller shift instruction register (SHIFT_IR) state shift appropriate instruction code pin. waveform diagram Figure represents entry instruction code into instruction register. shows values TCK, TMS, TDI, states controller. From RESET state, clocked with pattern 01100 advance controller SHIFT_IR.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure Selecting Instruction Mode
TAP_STATE RUN_TEST/IDLE TEST_LOGIC/RESET SELECT_IR_SCAN CAPTURE_IR SHIFT_IR EXIT1_IR
SELECT_DR_SCAN
tri-stated states except SHIFT_IR SHIFT_DR states. activated first falling edge after entering either shift states tri-stated first falling edge after leaving either shift states. When SHIFT_IR state activated, longer tri-stated, initial state instruction register shifted falling edge TCK. continues shift contents instruction register long SHIFT_IR state active. controller remains SHIFT_IR state long remains low. During SHIFT_IR state, instruction code entered shifting data rising edge TCK. last opcode must clocked same time that next state, EXIT1_IR, activated; EXIT1_IR entered clocking logic high TMS. Once EXIT1_IR state, becomes tri-stated again. always tri-stated except SHIFT_IR SHIFT_DR states. After instruction code entered correctly, controller advances perform serial shifting test data three modes-SAMPLE/PRELOAD, EXTEST, BYPASS-that described below.
SAMPLE/PRELOAD Instruction Mode
SAMPLE/PRELOAD instruction mode allows take snapshot device data without interrupting normal device operation. Figure shows capture, shift, update phases SAMPLE/PRELOAD mode.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure IEEE Std. 1149.1 SAMPLE/PRELOAD Mode
Capture Phase capture phase, signals pin, OUTJ, loaded into capture registers. register CLOCK signal supplied Controller's CLOCKDR output. data retained these registers consists signals from normal device operation.
OUTJ
Capture Registers SHIFT CLOCK
Update Registers UPDATE MODE
Shift Update Phases shift phase, previously captured signals pin, OUTJ, shifted boundaryscan register using CLOCK. data shifted out, patterns next test shifted pin. update phase, data transferred from capture registers UPDATE registers using UPDATE Clock. data stored UPDATE registers used EXTEST instruction.
OUTJ
Capture Registers SHIFT CLOCK
Update Registers UPDATE MODE
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
During capture phase, multiplexers preceding capture registers select active device data signals; this data then clocked into capture registers. multiplexers outputs update registers also select active device data prevent functional interruptions device. During shift phase, boundary-scan shift register formed clocking data through capture registers around device periphery then pin. test data simultaneously shifted into replace contents capture registers. During update phase, data capture registers transferred update registers. This data then used EXTEST instruction mode. Refer "EXTEST Instruction Mode" page more information. Figure shows SAMPLE/PRELOAD waveforms. SAMPLE/PRELOAD instruction code shifted through pin. controller advances CAPTURE_DR state then SHIFT_DR state, where remains held low. data shifted consists data that present capture registers after capture phase. test data shifted into appears after being clocked through entire boundary-scan register. Figure shows that instruction code does appear until after capture register data shifted out. held high consecutive clock cycles, controller advances UPDATE_DR state update phase. Figure SAMPLE/PRELOAD Shift Data Register Waveforms
SHIFT_IR TAP_STATE EXIT1_IR SELECT_DR_SCAN CAPTURE_DR SHIFT_DR
Instruction Code
UPDATE_IR
Data stored boundary-scan register shifted TDO.
After boundary-scan register data been shifted out, data entered into will shift TDO.
EXIT1_DR UPDATE_DR
EXTEST Instruction Mode
EXTEST instruction mode used primarily check external connections between devices. Unlike SAMPLE/PRELOAD mode, EXTEST allows test data forced onto signals. forcing known logic high levels output pins, opens shorts detected pins device scan chain.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure shows capture, shift, update phases EXTEST mode. Figure IEEE Std. 1149.1 EXTEST Mode
Capture Phase capture phase, signals pin, OUTJ, loaded into capture registers. register CLOCK signal supplied Controller's CLOCKDR output. Previously retained data update registers drives input, INJ, allows tri-state drive signal out. update register tri-states output buffer.
OUTJ
Capture Registers SHIFT CLOCK
Update Registers UPDATE MODE
Shift Update Phases shift phase, previously captured signals pin, OUTJ, shifted boundaryscan register using CLOCK. data shifted out, patterns next test shifted pin. update phase, data transferred from capture registers update registers using UPDATE Clock. update registers then drive input, INJ, allow tristate drive signal out.
OUTJ
Capture Registers SHIFT CLOCK
Update Registers UPDATE MODE
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
EXTEST selects data differently than SAMPLE/PRELOAD. EXTEST chooses data from update registers source INJ, output, output enable signals. Once EXTEST instruction code entered, multiplexers select update register data; thus, data stored these registers from previous EXTEST SAMPLE/PRELOAD test cycle forced onto signals. capture phase, results this test data stored capture registers then shifted during shift phase. test data then stored update registers during update phase. waveform diagram Figure resembles SAMPLE/PRELOAD waveform diagram, except that instruction code EXTEST uses zeros. data shifted consists data that present capture registers after capture phase. test data shifted into appears after being clocked through entire boundary-scan register. Figure EXTEST Shift Data Register Waveforms
SHIFT_IR TAP_STATE EXIT1_IR SELECT_DR CAPTURE_DR SHIFT_DR
Instruction Code
UPDATE_IR
Data stored boundary-scan register shifted TDO.
After boundary-scan EXIT1_DR register data been UPDATE_DR shifted out, data entered into will shift TDO.
BYPASS Instruction Mode
BYPASS instruction mode activated with instruction code made only ones. waveforms Figure show scan data passes through device once controller SHIFT_DR state. this state, data signals clocked into bypass register from rising edge falling edge same clock pulse.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Figure BYPASS Shift Data Register Waveforms
SHIFT_IR TAP_STATE EXIT1_IR SELECT_DR_SCAN CAPTURE_DR
SHIFT_DR
Instruction Code
UPDATE_IR
Data shifted into rising edge shifted falling edge same pulse.
EXIT1_DR UPDATE_DR
IDCODE Instruction Mode
IDCODE instruction mode used identify devices IEEE Std. 1149.1 chain. When IDCODE selected, device identification register loaded with 32-bit vendor-defined identification code connected between ports. 32-bit vendor-defined identification register Altera devices listed appropriate device family data sheet.
USERCODE Instruction Mode
USERCODE instruction mode used examine user electronic signature (UES) within devices along IEEE Std. 1149.1 chain. When this instruction selected, device identification register connected between ports user-defined shifted through device register. 7000S devices offer alternative method providing ability read user-defined 16-bit UES.
Enabling IEEE Std. 1149.1 Circuitry
IEEE Std. 1149.1 circuitry Altera devices enabled upon device power-up. Because this circuitry used BST, ISP, (depending device), this circuitry must enabled only specific times. This section describes enable IEEE Std. 1149.1 circuitry when needed ensure that circuitry inadvertently enabled when needed.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
APEX 20K, ACEX FLEX 9000 Devices
IEEE Std. 1149.1 circuitry Altera devices enabled upon device power-up. IEEE Std. 1149.1 circuitry both before after device programming configuration. However, APEX 20K, ACEX FLEX devices, nCONFIG must held when perform JTAG boundary-scan testing before configuration. Because these devices have dedicated IEEE Std. 1149.1 pins, their circuitry always enabled. disable JTAG circuitry these devices, these pins values shown Table Table Disabling IEEE Std. 1149.1 Circuitry Devices Compiler Option
APEX 20K, APEX 20KE ACEX FLEX 10K, FLEX 10KE FLEX 8000 FLEX 6000 9000 7000S, 7000A, 7000B, 3000A Notes:
design been compiled with IEEE Std. 1149.1 circuitry enabled, tying IEEE Std. 1149.1 pins appropriate state will deactivate IEEE Std. 1149.1 circuitry. signal also tied high. tied high, power-up conditions must ensure that pulled high before TCK. Pulling avoids this power-up condition. EPF81500A devices, these pins dedicated JTAG pins available user pins. JTAG used, TMS, TCK, TDI, TRST should tied GND.
JTAG Pins
User User User
Leave open Leave open Leave open User Leave open User Leave open Leave open User Leave open
TRST
JTAG Disabled JTAG Enabled JTAG Disabled JTAG Enabled JTAG Disabled JTAG Enabled
User User User User User User
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IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
FLEX 8000 FLEX 6000 Devices
IEEE Std. 1149.1 circuitry Altera devices enabled upon device power-up. IEEE Std. 1149.1 circuitry both before after device programming configuration. FLEX 8000 FLEX 6000 devices, nCONFIG must held when perform boundary-scan testing before configuration. Because these devices have four pins that used either JTAG pins user pins, must enable disable JTAG circuitry before compilation. design that been compiled with JTAG pins enabled, four pins operate dedicated pins only. these devices using IEEE Std. 1149.1 circuitry, tying pins appropriate state (shown Table disables circuitry. choosing Device Options from Device dialog (Assign menu), enable disable IEEE Std. 1149.1 support applicable devices device-by-device basis with Enable JTAG Support option. also enable JTAG support devices project choosing Global Project Device Options (Assign menu) selecting Enable JTAG Support option.
7000S, 7000A, 7000B 3000A Devices
IEEE Std. 1149.1 circuitry 7000S, 7000A, 7000B, 3000A devices enabled IEEE Std. 1149.1 enable within device. blank device will always have circuitry enabled. state this enable only programming Altera third-party programmer. state JTAG enable changed using IEEE Std. 1149.1 port. Because these devices have four pins that used either JTAG pins user pins, must enable disable JTAG circuitry before compilation. design that been compiled with JTAG pins enabled, four pins operate dedicated pins only. these devices using IEEE Std. 1149.1 circuitry, tying pins appropriate state (shown Table disables circuitry. choosing Device Options from Device dialog (Assign menu), enable disable IEEE Std. 1149.1 support applicable devices device-by-device basis with Enable JTAG Support option. also enable JTAG support devices project choosing Global Project Device Options (Assign menu) selecting Enable JTAG Support option.
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IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Guidelines IEEE Std. 1149.1 Boundary-Scan Testing
following guidelines when performing boundary-scan testing with IEEE Std. 1149.1 devices:
"10." pattern does shift instruction register during first clock cycle SHIFT_IR state, proper controller state been reached. solve this problem, following procedures: Verify that controller reached SHIFT_IR state correctly. advance controller SHIFT_IR state, return RESET state clock code 01100 pin. Check connections VCC, GND, JTAG, dedicated configuration pins device. FLEX, 7000S, 7000A, 7000B, 3000A devices, device user mode, make sure that have turned Enable JTAG Support option MAX+PLUS software. Perform SAMPLE/PRELOAD test cycle prior first EXTEST test cycle ensure that known data present device pins when EXTEST mode entered. update register contains data OUTJ update register will driven out. state must known correct avoid contention with other devices system. perform EXTEST SAMPLE/PRELOAD tests during ICR. These instructions supported before after ISP/ICR during ICR. FLEX 8000 devices, execute BYPASS shift cycle before EXTEST test cycle that requires preloaded test data. bypass boundary-scan registers shift simultaneously when controller SHIFT_DR state. Therefore, using BYPASS mode will shift test data capture registers.
problems persist, contact Altera Applications (800) 800-EPLD.
Boundary-Scan Description Language (BSDL) Support
Boundary-Scan Description Language (BSDL)-a subset VHDL- provides syntax that allows describe features IEEE Std. 1149.1 BST-capable device that tested. Test software development systems then BSDL files test generation, analysis, failure diagnostics, in-system programming. more information, receive BSDL files IEEE Std. 1149.1-compliant Altera devices, visit Altera site http://www.altera.com.
Altera Corporation
IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices
Conclusion
IEEE Std. 1149.1 circuitry available Altera devices provides cost-effective efficient test systems that contain devices with tight lead spacing. Circuit boards with Altera other IEEE Std. 1149.1compliant devices EXTEST, SAMPLE/PRELOAD, BYPASS modes create serial patterns that internally test connections between devices check device operation. Bleeker, Eijnden, Jong. Boundary-Scan Test: Practical Approach. Eindhoven, Netherlands: Kluwer Academic Publishers, 1993. Institute Electrical Electronic Engineers, Inc. IEEE Standard Test Access Port Boundary-Scan Architecture (IEEE 1149.1-1990). York: Institute Electrical Electronic Engineers, Inc., 1990. Maunder, Tulloss. Test Access Port BoundaryScan Architecture. Alamitos: IEEE Computer Society Press, 1990.
References
Revision History
information contained Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.05 supersedes information published previous versions.
Version 4.05 Changes
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.05 contains following changes:
Added APEX 20K, ACEX FLEX 10KE, 7000B, 3000A information document where relevant. Updated Table page Updated Figure page Updated Note Note page Updated Figure page Updated Note Note page Updated Figure page Updated Note page Updated Table page Updated Note page Updated Table page
Version 4.04 Changes
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.04 contains following changes:
Updated information 7000A devices Table
Altera Corporation
JTAG Boundary-Scan Testing Altera Devices
Moved IDCODE values information from "Length IEEE 1149.1 Registers" table device family data sheets. Added Note Figure Made minor style changes.
Version 4.03 Changes
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.03 contained following changes:
Added Note Table JTAG EPF81500A devices. Made minor style changes.
Version 4.02 Changes
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.02 contained following changes:
Corrected boundary-scan register length several devices Table page Corrected signal polarity pins Figures Updated information disable JTAG circuitry Table page Made minor textual style changes.
Version 4.01 Changes
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) version 4.01 contained following changes:
Corrected boundary-scan register length EPM7192S devices Table page Updated Figure accuracy.
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Altera Devices September 2000, ver. 4.05 Introduction p

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