10-Bit, 12-Bit, Multiplying Converters AD7520/AD7530 AD7521/AD753
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AD7520, AD7530, AD7521, AD7531
10-Bit, 12-Bit, Multiplying Converters
AD7520/AD7530 AD7521/AD7531 monolithic, high accuracy, cost 10-bit 12-bit resolution, multiplying digital-to-analog converters (DAC). Intersil' thin-film CMOS processing gives 10-bit accuracy with TTL/CMOS compatible operation. Digital inputs fully protected against static discharge diodes ground positive supply. Typical applications include digital/analog interfacing, multiplication division, programmable power supplies, character generation, digitally controlled gain circuits, integrators attenuators, etc. AD7530 AD7531 identical AD7520 AD7521, respectively, with exception output leakage current feedthrough specifications.
Features
AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit 10-Bit Linearity AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit 10-Bit Linearity Power Dissipation (Max) .20mW Nonlinearity Tempco 2ppm FSR/oC Current Settling Time 0.05% 1.0µs Supply Voltage Range +15V TTL/CMOS Compatible Full Input Static Protection /883B Processed Versions Available
Ordering Information
PART NUMBER AD7520JN, AD7530JN AD7520KN, AD7530KN AD7521JN, AD7531JN AD7521KN, AD7531KN AD7520LN, AD7530LN AD7521LN, AD7531LN AD7520JD AD7520KD AD7520LD AD7520SD, AD7520SD/883B AD7520UD, AD7520UD/883B LINEARITY (INL, DNL) 0.2% (8-Bit) 0.1% (9-Bit) 0.2% (8-Bit) 0.1% (9-Bit) 0.05% (10-Bit) 0.05% (10-Bit) 0.2% (8-Bit) 0.1% (9-Bit) 0.05% (10-Bit) 0.2% (8-Bit) 0.05% (10-Bit) TEMP. RANGE (oC) PACKAGE PDIP PDIP PDIP PDIP PDIP PDIP CERDIP CERDIP CERDIP CERDIP CERDIP PKG. E16.3 E16.3 E18.3 E18.3 E16.3 E18.3 F16.3 F16.3 F16.3 F16.3 F16.3
Pinouts
AD7520, AD7530 (CERDIP, PDIP) VIEW
IOUT1 IOUT2 (MSB) RFEEDBACK VREF (LSB)
AD7521, AD7531 (PDIP) VIEW
IOUT1 IOUT2 (MSB) RFEEDBACK VREF (LSB)
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
File Number
3104.1
10-7
AD7520, AD7530, AD7521, AD7531
Absolute Maximum Ratings
Supply Voltage GND). +17V VREF ±25V Digital Input Voltage Range Output Voltage Compliance -100mV
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package PDIP Package CERDIP Package Maximum Junction Temperature (Hermetic Package) 175oC Maximum Junction Temperature (Plastic Packages) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Ranges Versions .0oC 70oC Versions -25oC 85oC Versions -55oC 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied. digital control inputs zener protected; however, permanent damage occur unconnected units under high energy electrostatic fields. Keep unused units conductive foam times. apply voltages higher than less than potential terminal except VREF RFEEDBACK.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
+15V, VREF +10V, 25oC Unless Otherwise Specified AD7520/AD7530 AD7521/AD7531 UNITS
PARAMETER SYSTEM PERFORMANCE (Note Resolution Nonlinearity
TEST CONDITIONS
Over -55oC 125oC (Notes (Figure Over -55oC 125oC (Figure -10V VREF +10V Over -55oC 125oC (Figure -10V VREF +10V (Notes
±0.2 (8-Bit) ±0.1 (9-Bit) ±0.05 (10-Bit) ±200 (±300)
±0.2 (8-Bit) ±0.1 (9-Bit) ±0.05 (10-Bit) ±200 (±300)
Bits FSR/oC FSR/oC
Nonlinearity Tempco Gain Error Gain Error Tempco Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS Output Current Settling Time
±0.3
±0.3
Over Specified Temperature Range
0.05% (All Digital Inputs High High Low) (Note (Figure VREF 20VP-P 10kHz (50kHz) Digital Inputs (Note (Figure
Feedthrough Error
mVP-P
REFERENCE INPUT Input Resistance ANALOG OUTPUT Output Capacitance IOUT1 Digital Inputs High (Note (Figure IOUT2 IOUT1 Digital Inputs (Note (Figure IOUT2 Digital Inputs High IOUT1 Ground
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AD7520, AD7530, AD7521, AD7531
Electrical Specifications
+15V, VREF +10V, 25oC Unless Otherwise Specified (Continued) AD7520/AD7530 PARAMETER Output Noise DIGITAL INPUTS State Threshold, High State Threshold, Input Current, IIL, Input Coding Tables ±0.005 Digital Inputs Excluding Ladder Network Digital Inputs High Excluding Ladder Network Total Power Dissipation NOTES: Full scale range (FSR) Unipolar ±10V Bipolar modes. Using internal feedback resistor RFEEDBACK Guaranteed design, characterization production tested. Accuracy guaranteed unless outputs potential. Accuracy tested guaranteed only. Including Ladder Network Over Specified Temperature Range +15V TEST CONDITIONS Both Outputs (Note (Figure Equivalent AD7521/AD7531 Equivalent UNITS Johnson Noise
Binary/Offset Binary ±0.005
POWER SUPPLY CHARACTERISTICS Power Supply Rejection Power Supply Voltage Range 14.5V 15.5V (Note (Figure FSR/
Functional Diagram
VREF
SPDT NMOS SWITCHES
IOUT2 IOUT1 RFEEDBACK
NOTES: Switches shown Digital Inputs "High". Resistor values typical.
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AD7520, AD7530, AD7521, AD7531 Descriptions
AD7520/30 AD7521/31 NAME IOUT1 IOUT2 VREF DESCRIPTION Current summing junction ladder network. Current virtual ground, return path ladder network. Digital Ground. Ground potential digital side D/A. Digital Digital Digital Digital Digital Digital Digital Digital Digital (AD7521/31). Least Significant Digital Data (AD7520/30). Digital (AD7521/31). Least Significant Digital Data (AD7521/31). Power Supply +15V. Voltage Reference Input output range. Supplies resistor ladder.
Bits 1(MSB) Most Significant Digital Data Bit.
RFEEDBACK Feedback resistor used current voltage conversion when using external Amp.
Definition Terms
Nonlinearity: Error contributed deviation transfer function from "best straight line" through actual plot transfer function. Normally expressed percentage full scale range (sub)multiples LSB. Resolution: addressing smallest distinct analog output change that converter produce. commonly expressed number converter bits. converter with resolution bits resolve output changes full-scale range, e.g., VREF unipolar conversion. Resolution means implies linearity. Settling Time: Time required output settle within specified error band around final value (e.g., LSB) given digital input change, i.e., digital inputs HIGH HIGH LOW. Gain Error: difference between actual ideal analog output values full scale range, i.e., digital inputs HIGH state. expressed percentage full scale range (sub)multiples LSB. Feedthrough Error: Error caused capacitive coupling from VREF IOUT1 with digital inputs LOW. Output Capacitance: Capacitance from IOUT1 IOUT2 terminals ground. Output Leakage Current: Current which appears IOUT1 terminal when digital inputs IOUT2 terminal when digital inputs HIGH. current reference operational amplifier that required most voltage output applications. simplified equivalent circuit shown Functional Diagram. NMOS SPDT switches steer ladder currents between IOUT1 IOUT2 buses which must held either ground potential. This configuration maintains constant current each ladder independent input code. Converter errors further reduced using separate metal interconnections between major bits outputs. high threshold switches reduce offset (leakage) errors negligible level. level shifter circuits comprised three inverters with positive feedback from output second first, Figure This configuration results TTL/CMOS compatible operation over full military temperature range. With ladder SPDT switches driven level shifter, each switch binarily weighted resistance proportional respective ladder current. This assures constant voltage drop across each switch, creating equipotential terminations ladder resistors highly accurate currents.
LADDER
Detailed AD7520, AD7530, AD7521 AD7531 monolithic, multiplying converters. highly stable thin film R-2R resistor ladder network NMOS SPDT switches form basis converter circuit, CMOS level shifters permit power TTL/CMOS compatible operation. external voltage
DTL/TTL/ CMOS INPUT IOUT2 IOUT1
FIGURE CMOS SWITCH
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AD7520, AD7530, AD7521, AD7531 Test Circuits
following test circuits apply AD7520. Similar circuits used AD7530, AD7521 AD7531.
VREF (MSB) 10-BIT BINARY COUNTER
+15V
RFEEDBACK IOUT1 AD7520 HA2600 OUT2 (LSB) (LSB) VREF 0.01% 12-BIT REFERENCE
+15V
0.01%
VREF
+10V (MSB)
UNGROUNDED SINE WAVE GENERATOR 400Hz 1VP-P 0.01% 0.01%
500k
RFEEDBACK OUT1 AD7520 OUT2 HA2600 HA2600
CLOCK
HA2600 LINEARITY ERROR
(LSB)
FIGURE NONLINEARITY
FIGURE POWER SUPPLY REJECTION
+11V (ADJUST VOUT +15V 1kHz 15µF IOUT2 AD7520 IOUT1 QUAN TECH MODEL 134D 101ALN WAVE VOUT ANALYZER +15V (MSB) AD7520 +15V
100mVP-P 1MHz SCOPE
0.1µF (LSB)
FIGURE NOISE
FIGURE OUTPUT CAPACITANCE
VREF 20VP-P 100kHz SINE WAVE (MSB)
+15V -10V AD7520 VREF
SETTLING (1mV) EXTRAPOLATE 0.03% SETTLING RISE TIME +15V
(MSB) IOUT1 IOUT2
VOUT
DIGITAL INPUT (LSB)
(LSB)
HA2600
AD7520
+100mV IOUT2
SCOPE
FIGURE FEEDTHROUGH ERROR
FIGURE OUTPUT CURRENT SETTLING TIME
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AD7520, AD7530, AD7521, AD7531 Applications
Unipolar Binary Operation circuit configuration operating AD7520 unipolar mode shown Figure Similar circuits used AD7521, AD7530 AD7531. With positive negative VREF values circuit capable 2-Quadrant multiplication. "Digital Input Code/Analog Output Value" table unipolar mode given Table
VREF (MSB) +15V VREF (MSB) DIGITAL INPUT RFEEDBACK IOUT1 AD7520 IOUT2
"Digital Input Code/Analog Output Value" table bipolar mode given Table
+15V
(LSB) RFEEDBACK IOUT1 IOUT2
0.01% 0.01%
DIGITAL INPUT (LSB)
AD7520
VOUT
FIGURE BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) TABLE BlPOLAR (OFFSET BINARY) CODE TABLE DIGITAL INPUT ANALOG OUTPUT -VREF (1-2-(N-1)) -VREF (2-(N-1)) VREF (2-(N-1)) VREF (1-2-(N-1)) VREF 7520, 7521; 7530, 7531.
FIGURE UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) TABLE CODE TABLE UNlPOLAR BINARY OPERATION DIGITAL INPUT 1111111111 1000000001 1000000000 0111111111 0000000001 0000000000 NOTES: VREF 7520, 7530; 7521, 7531. ANALOG OUTPUT -VREF (1-2-N) -VREF (1/2 2-N) -VREF/2 -VREF (1/2-2-N) -VREF (2-N)
1111111111 1000000001 1000000000 0111111111 0000000001 0000000000 NOTES: 2-(N-1) VREF
Zero Offset Adjustment Connect digital inputs GND. Adjust offset zero adjust trimpot output operational amplifier VOUT Gain Adjustment Connect digital inputs Monitor VOUT -VREF (1-2-N) reading. AD7520/30 AD7521/31). decrease VOUT connect series resistor 250) between reference voltage VREF terminal. increase VOUT connect series resistor 250) IOUT1 amplifier feedback loop. Bipolar (Offset Binary) Operation circuit configuration operating AD7520 bipolar mode given Figure Similar circuits used AD7521, AD7530 AD7531. Using offset binary digital input codes positive negative reference voltage values, 4-Quadrant multiplication realized.
"Logic input digital input forces corresponding ladder switch steer current IOUT1 bus. "Logic input forces current IOUT2 bus. code IOUT1 IOUT2 currents complements another. current amplifier IOUT2 changes polarity IOUT2 current transconductance amplifier IOUT1 output sums currents. This configuration doubles output range. difference current resulting zero offset binary code, (MSB "Logic other bits "Logic 0"), corrected using external resistor, (10M), from VREF IOUT2 Offset Adjustment Adjust VREF approximately +10V. Connect digital inputs "Logic Adjust IOUT2 amplifier offset adjust trimpot ±1mV IOUT2 amplifier output. Connect (Bit "Logic other bits "Logic Adjust IOUT1 amplifier offset adjust trimpot ±1mV VOUT. Gain Adjustment Connect digital inputs Monitor VOUT -VREF (1-2-(N-1) volts reading. AD7520 AD7530, AD7521 AD7531). increase VOUT connect series resistor between VOUT RFEEDBACK decrease VOUT connect series resister between reference voltage VREF terminal.
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VOUT
AD7520, AD7530, AD7521, AD7531 Characteristics
DIMENSIONS: mils mils (2565micrms 2616micrms) METALLIZATION: Type: Pure Aluminum Thickness: PASSIVATION: Type: PSG/Nitride PSG: Nitride: PROCESS: CMOS Metal Gate
Metallization Mask Layout
AD7520, AD7530
(MSB)
IOUT2
IOUT1
RFEEDBACK VREF
(LSB)
10-13
AD7520, AD7530, AD7521, AD7531 Characteristics
DIMENSIONS: mils mils (2565micrms 2616micrms) METALLIZATION: Type: Pure Aluminum Thickness: PASSIVATION: Type: PSG/Nitride PSG: Nitride: PROCESS: CMOS Metal Gate
Metallization Mask Layout
AD7521, AD7531
(MSB)
IOUT2
IOUT1
RFEEDBACK VREF
(LSB)
10-14
AD7520, AD7530, AD7521, AD7531
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