AD6426 CHANNEL CODEC VOICEBAND BASEBAND CODEC INTERFACE TEST INTE
|
|
|
Top Searches for this datasheet
Enhanced Processor
AD6426
CHANNEL CODEC VOICEBAND BASEBAND CODEC INTERFACE TEST INTERFACE
Preliminary Technical Information
FEATURES Complete Single Chip Processor Channel Codec Subsystem including Channel Coder/Decoder Interleaver/De-interleaver Encryption/Decryption Control Processor Subsystem including 16-bit Control Processor (H8/300H) Parallel Serial Display Interface Keypad Interface EEPROM Interface SIM-Interface Universal System Connector Interface Interface AD6425 Control Radio Subsystem Programmable backlight duty cycle Real Time Clock with Alarm Battery Chip Interface Subsystem including 16-bit with coded firmware Full rate Speech Encoding/Decoding (GSM 06.10) Enhanced Full Rate Speech Encoding/Decoding (GSM 06.60) Equalization with 16-state Viterbi (Soft Decision) DTMF Call Progress Tone Generation Power Management Mobile Radio Slow Clocking scheme Idle Mode current Ultra Power Design On-chip Data Services 14.4 kbit/s JTAG Test Interface 2.4V 3.3V Operating Voltage 144-Lead LQFP 144-Lead PBGA packages APPLICATIONS DCS1800 PCS1900 Mobile Stations (MS) Compliant Phase Phase specifications GENERAL DESCRIPTION AD6426 Enhanced Processor (EGSMP) central component highly integrated AD20msp425 Chipset. Offering total chip count, bill materials cost long talk standby times, chipset offers designers straightforward route highly competitive product GSM/DCS1800 market. EGSMP performs baseband functions Layer processing interface. This includes data encoding decoding processes well timing radio sub-system control functions. EGSMP supports full rate enhanced full rate speech traffic well full range data services including F14.4.
UNIVERSAL SYSTEM CONN. INTERFACE
CHANNEL EQUALIZER
DISPLAY INTERFACE
INTERFACE
RADIO INTERFACE SPEECH CODEC
EEPROM INTERFACE
ACCESSORY INTERFACE
MEMORY INTERFACE
CONTROL PROCESSOR
KEYPAD BACKLIGHT INTERFACE
Figure Functional Block Diagram addition, EGSMP supports both A5/1 A5/2 encryption algorithms well operation non-encrypted mode. EGSMP integrates high performance 16-bit microprocessor (Hitachi H8/300H), that supports terminal software, including Layer protocol stack, applications software such data services, test maintenance. standard processor allows HIOS, Hitachi real time kernel, well full range software development tools including compilers, debuggers incircuit emulators. EGSMP also integrates high performance 16-bit Digital Signal Processor (DSP), which provides speech transcoding supports audio functions both transmit receive. receive equalizes received signal using 16-state (Viterbi) soft decision equalizer. EGSMP interfaces with peripheral sub-systems terminal, including keypad, memories, display driver, SIM, data services interface radio. also general purpose interface that used support external connection battery charger. EGSMP interfaces with AD6425 AD6421 Voiceband/Baseband Codec through dedicated serial port. ORDERING GUIDE Model AD6426XST AD6426XB Temperature Range -25°C +85°C -25°C +85°C Package 144-Lead LQFP 144-Lead PBGA
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
CLKIN OSC13MON OSCIN OSCOUT JTAGEN
AD6426
VCTCXO
SYSTEM CONNECTOR
USCRI USCRX USCTX USCCTS USCRTS GPIO [9:0] GPCS GPPWRCTL SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY EEPROMEN EEPROMDATA EEPROMCLK BACKLIGHT KEYPADROW [5:0] KEYPADCOL [3:0]
JTAG PORT
ACCESSORY
EVBC AD6421
CLKOUT VBCRESET ASDO ASOFS ASCLK ASDI MCLK RESET ASDI ASDIFS ASDOFS ASCLK ASDO BSDI BSDIFS BSCLK BSDO BSDOFS MODE VSDO VSDI VSCLK VSFS VSDI VSDO VSCLK VSFS
EEPROM
BACKLIGHT KEYPAD
ENHANCED PROCESSOR AD6426
BSDO BSOFS BSCLK BSDI BSIFS
FLASH
FLASHPWD ROMCS [20:0] DATA [15:0] RAMCS
SRAM DISPLAY LCDCTL DISPLAYCS POWER SUBSYSTEM
RXON TXON RXON TXENABLE TXPHASE TXPA CALIBRATERADIO RADIOPWRCTL SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB
VDDRTC PWRON
RADIO
IRQ6 RESET BOOTCODE VDD(10) GND(10)
Figure External Interfaces AD6426
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Table Contents
GENERAL DESCRIPTION FUNCTIONALITY Normal Mode) OVERVIEW.7 FUNCTIONAL PARTITIONING Channel Codec Sub-System Processor Sub-System Sub-System.8 Speech Transcoding Equalization.8 Audio Control Tone Generation Automatic Frequency Control (AFC) Automatic Gain Control (AGC).8 REGISTERS.9 GENERAL CONTROL.14 Clocks Slow Clocking Real Time Clock Alarm.14 Reset Interrupts NMI.15 Wait Automatic Booting.16 Power Control.16 INTERFACES Memory Interface.16 EEPROM Interface Interface.17 Accessory Interface Universal System Connector Interface Operating modes USC.18 Buffered UART Mode (Booting/Data Services).18 Keypad Backlight Display Interface Battery Interface.20 EVBC Interface Radio Interface Dual Band Control Timing Control Timing Control Synthesizer Control Control.25 TEST INTERFACE JTAG Port.27 Debug Port Interface MODES OPERATION.29 Normal Mode (Mode Emulation Mode (Mode FEATURE MODES.30 Mode.30 High Speed Logging.30 SPECIFICATIONS General.32 ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS.33 Clocks
AD6426
Memory Interface.34 Radio Interface High Speed Logging Interface Data Interface Test Interface.38 EVBC Interface ASPORT EVBC Interface BSPORT EVBC Interface VSPORT Parallel Display Interface Serial Display Interface.43 PACKAGING.44 LQFP Locations.44 PBGA Locations LQFP Outline Dimensions PBGA Outline Dimensions
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
FUNCTIONALITY Normal Mode) Group General Name CLKIN RESET IRQ6 OSC13MON BOOTCODE Memory Interface ADD19 GPO10 DATA15 FLASHPWD RAMCS ROMCS Interface SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY EEPRROM Interface Display Backlight Keypad Interface EEPROMDATA EEPROMCLK EEPROMEN DISPLAYCS LCDCTL BACKLIGHT KEYPADROW5 KEYPADCOL3 Pins O/I/ Default Alternative Function(s) Clock Input Reset input
AD6426
Interrupt Request Non-Maskable Interrupt (NMI) Oscillator Power Control Signal Boot Code Enable Supply Voltage Ground Processor Address General Purpose Output Address (20) Processor Data Processor Read Strobe Processor High Write Strobe Upper Byte Strobe Processor Write Strobe Lower Byte Strobe Processor Write Strobe FLASH Power Down WAIT General Purpose Output External Chip Select External Chip Select Card Detect General Purpose Data Output Data Input Clock Reset Program Enable General Purpose Supply Enable EEPROM Data EEPROM Clock High Speed Logger Clock EEPROM Enable High Speed Logger Frame Sync Display Controller Chip Select Chip Enable Control Serial Display Data Output Backlight Control Keypad Inputs Keypad Column Strobes (open drain, pull low)
Note: Functionality these pins changed under software control.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Functionality NORMAL MODE) Group EVBC Interface ASPORT Name CLKOUT EVBCRESET ASDO ASOFS ASCLK ASDI BSPORT BSDO BSOFS BSCLK BSDI BSIFS VSPORT VSDO VSDI VSCLK VSFS Radio Interface RXON TXPHASE TXENABLE TXPA CALIBRATERADIO RADIOPWRCTL SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB Universal System Connector Interface USCRI USCRX USCTX USCCTS USCRTS Pins Default Alternative Function(s) Clock Output EVBC EVBC Reset Output (also Display reset) EVBC Auxiliary Serial Port Data Output
AD6426
EVBC Auxiliary Serial Port Output Framing Signal EVBC Auxiliary Serial Port Clock Output EVBC Auxiliary Serial Port Data Input EVBC Baseband Serial Port Data Output EVBC Baseband Serial Port Output Framing Signal EVBC Baseband Serial Port Clock Input EVBC Baseband Serial Port Data Input EVBC Baseband Serial Port Input Framing Signal EVBC Voiceband Serial Port Data Output EVBC Voiceband Serial Port Data Input EVBC Voiceband Serial Port Clock Input EVBC Voiceband Serial Port Framing Signal Receiver Switches between Transmit Enable General Purpose Output Power Amplifier Enable General Purpose Output Radio Calibration General Purpose Output Radio Power-Down Control Synthesizer Enable Synthesizer Enable General Purpose Output Serial Port Data Serial Port Clock Gain Select General Purpose Output Gain Select General Purpose Output Ring Indicator Serial Clock GPO20 Receive Data Transmit Data Baseband Serial Port Data Input Clear Send Serial Frame Sync GPI22 Ready Send GPO21
Note: Functionality these pins changed under software control.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Functionality NORMAL MODE) Group Accessory Interface Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPCS Real Time Clock Interface Test Interface OSCIN OSCOUT VDDRTC PWRON JTAGEN Pins Default Alternative Function(s) General Purpose Inputs/Output
AD6426
General Purpose Inputs/Output Radio BANDSELECT1 General Purpose Inputs/Output Radio BANDSELECT0 General Purpose Inputs/Outputs Serial Display Address Output General Purpose Inputs/Outputs Serial Display Clock Output General Purpose Inputs/Outputs Battery Interface General Purpose Inputs/Output VBIAS General Purpose Inputs/Output Antenna Select General Purpose Inputs/Output DEBUG UART Transmit Data General Purpose Inputs/Output DEBUG UART Receive Data General Purpose Chip Select 32.768 Crystal Input 32.768 Oscillator Output Feedback Crystal Supply Voltage Power ON/OFF Control JTAG Enable JTAG Test Clock Data JTAG Test Mode Select Data Reset JTAG Test Data Input Data Data JTAG Test Data Output Data Data
Note: Functionality these pins changed under software control.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
OVERVIEW interface been formulated provide high quality digital mobile communication. well supporting traffic channels (speech and/or data), interface specifies number signaling channels that used call communications between network infrastructure mobile. These signaling channels provide mobile specific features such handover, well number other intelligent features. system closely follows 7-layer model communications. Specifically, defines Layers protocols. lowest level being Layer Physical Layer. this part network processing which EGSMP responsible, performing some Layer functions dedicated hardware minimum power consumption some software increased flexibility. Layer covers those signal processing functions required format speech/data transmission physical medium. Data must structured allow identification, recovery error correction that information supplied error free layer sub-systems traffic sources. addition, physical layer processing includes timing both transmit receive data, encryption data security purposes control Radio subsystem provide timing optimize radio frequency characteristics. object code license Layer software supplied with AD20msp425 chipset. FUNCTIONAL PARTITIONING This datasheet gives only overview about functionality EGSMP. EGSMP consists three main elements; Channel Codec Control Processor Sub-System including several interfaces shown Figure Channel Codec responsible Layer channel coding decoding traffic control information. Processor Sub-system supports software functions protocol stack interfaces with peripheral subsystems terminal. performs channel equalization speech transcoding. Channel Codec Sub-System Channel Codec processes data from principal sources; traffic signaling. former normally continuous latter determined demand. Traffic comes forms; speech user data. various traffic sources signaling sources processed differently physical layer. Speech traffic data supplied speech transcoder remaining data types sourced from Control Processor interfaced dedicated data interface. Channel Codec subsystem functional block diagram shown Figure
ENCODE INTERLEAVE ENCRYPT
AD6426
INTERFACE
INTERFACE
DECODE
DEINTERLEAVE
DECRYPT
REGISTERS INTERFACE RADIO SYNTHESIZER TIMING CONTROL
TEST INTERFACE
Figure Channel Codec Subsystem transmit receive functions Channel Codec timed internal timebase that maintains accurate timing sub-systems. This timebase aligned with on-air receive signal system control signals, both internal external, derived from physical layer processing divided into phases, each downlink. data transmit path undergoes ENCODE phase then TRANSMIT phase. Similarly, data downlink path termed receive data undergoes RECEIVE phase followed DECODE phase. buffer between ENCODE TRANSMIT functions INTERLEAVE module that holds data permits building transmit burst structure. Similarly DEINTERLEAVE module forms buffer between RECEIVE DECODE processes. Each these four phases controlled explicitly Control Processor control registers that define mode operation each sub-module data source they should process. Typically these control values updated every TDMA frame response interrupts from internal timebase. ENCODE process involves incorporation error protection codes. data sourced packets forms error coding applied; block coding (parity Fire code) convolution coding. resultant data block then written INTERLEAVE module where buffered RAM. Data read from interleave buffer memories contiguously written non-contiguous manner, thereby implementing interleaving function. TRANSMIT process uses different time structure associated with on-air TDMA structure. data read from INTERLEAVE module formatted into bursts with requisite timing. This involves adding fixed patterns such tail bits training sequence code. resultant burst written external Baseband Converter where modulation performed output timed system timebase before transmission.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
feature system application, part TRANSMIT process, data encryption purpose link security. After INTERLEAVE module data encrypted using prescribed A5/1 A5/2 encryption algorithm. RECEIVE function requires unmodulated baseband data from equalizer. necessary data decrypted written DEINTERLEAVE module. This conducted TDMA frame rate, although precise timing necessary this stage. DECODING process reads data from DEINTERLEAVE module, inverting interleave algorithm decodes error control codes, correcting flagging errors appropriate. data also includes measure confidence expressed additional bits received symbol. These used convolution decoder improve error decoding performance. resultant data then presented original sources determined control programming. Channel Codec interfaces with speech transcoder speech traffic data with equalizer recovered receive data. AD6426 equalizer speech transcoder implemented DSP. Processor Sub-System Processor Sub-System consists high performance 16bit microcontroller together with selection peripheral elements. processor version Hitachi H8/300H that been developed support applications which well suited support Protocol Stack Application Layer software. Sub-System Sub-System consists high performance 16-bit digital signal processor (DSP) with integrated memories. performs major tasks: speech transcoding channel equalization. Additionally several support functions performed DSP. instruction code, which advises perform these tasks, stored internal ROM. sub-system completely selfcontained, external memory user-programming necessary. Speech Transcoding Full Rate mode receives speech data stream from EVBC encodes data from kbit/s kbit/s. algorithm used Regular Pulse Excitation, with Long Term Prediction (RPE-LTP) specified 06-series Recommendations. Enhanced Full Rate mode, encodes kbit/s speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC repetition bits) additionally specified Phase version 06-series Recommendations. both modes, also performs appropriate voice activity detection discontinuous transmission (VAD/DTX) functions.
AD6426
Alternatively receives encoded speech data from channel codec sub-system including Frame Indicator (BFI). Speech decoder supports Comfort Noise Insertion (CNI) function that inserts predefined silence descriptor into decoding process. resulting data, kbit/s, transferred EVBC. Equalization Equalizer recovers demodulates received signal establishes local timing frequency references mobile terminal well RSSI calculation. equalization algorithm version Maximum Likelihood Sequence Estimation (MLSE) using Viterbi algorithm. confidence bits symbol provide additional information about accuracy each decision channel codec's convolutional decoder. equalizer outputs sequence bits including confidence bits channel codec subsystem. Audio Control subsystem also responsible control audio path. EVBC provides audio inputs audio outputs, well separate buzzer output, which switched controlled DSP. Furthermore EVBC provides variable gain sensitivity which also controlled under command Layer software. Tone Generation alert signals generated output EVBC. These alerts used buzzer earpiece. tones used alert signals fully defined user means description which provides parameters required such frequency content duration components tone. tone descriptions provided Layer software. Automatic Frequency Control (AFC) detection frequency correction burst provides frequency offset between mobile terminal received signal. This measure supplied Layer software which then requests correction master clock oscillator frequency AFC-DAC EVBC. order Layer software includes transfer function oscillator frequency against voltage applied. provides measurements AFC. Automatic Gain Control (AGC) also responsible making measurements power received signal. This used number functions including RSSI measurement, adjacent channel monitoring AGC. Layer software passes requested gain level DSP, which then analyzes received signal generates control signal. Depending radio architecture, this control signal will used digital form converted AD6425 analog form.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
REGISTERS AD6426 contains Channel Codec Control Registers, Peripheral Registers mapped into Channel Codec address space starting 8000h. registers normally accessed Layer software provided with AD20msp425 chipset. user expected read write registers other than through Layer software. Therefore only limited description these registers given here ease understanding functional behavior AD6426. Only registers which modified monitored user under control Layer software shown. Channel Codec Control Registers listed Table Peripheral Control Registers Table description Channel Codec Control Register contents shown Table Peripheral Registers Table Table Control Registers
AD6426
Address
Name
SYNTHESIZER PROGRAM TXPA OFFSET TXPA OFFSET TXPA WIDTH TXPA WIDTH ENABLE LATCH GPIO ccGPO
Address
Name
SYSTEM RADIO CONTROL BSIC TRAFFIC MODE EEPROM KEYPAD COLUMN KEYPAD EVBC SERIAL EVBC SERIAL EVBC CONTROL RESET SYNTH COUNT SYNTH CONTROL ERROR COUNT SYNTHESIZER SYNTHESIZER SYNTHESIZER SYNTHESIZER POWER CONTROL POWER CONTROL EXTERNAL SWRESET SWRESET INTERRUPT COUNTER ADDRESS BACKLIGHT VERSION CONTROL
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Table Control Register Contents
AD6426
Calibrate Radio PHASE Enable
Autocalibrate Monitor Enable
Phase Polarity
Backlight Radio Control Polarity
Test Data Enable Radio Control Polarity
Encryption Type Monitor Enable
Encrypt Load Receive Enable Training Sequence Code
Transmit Enable
Base Station Identity Code TxPA Polarity COUNT[8] BAND ENABLE OVERRIDE Interrupt Counter Override Select EEPROM Data Output Enable Keypad EVBC Serial Port EVBC Serial Port Data Delay EVBC Reset Isolate Synthesizer Synthesizer Enable Polarity Config. Dynam. Synthesizer Synthesizer Enable Type Synthesizer Interface active Synthesizer Clock Polarity Error Count Synthesizer (31: Synthesizer (23: Synthesizer (15: Synthesizer Backlight Duty Cycle Coprocessor Power Control Output Clock Enable Power Control Encryption SW-Reset Decode SW-Reset EVBC Address Modulate Version Disable Synth.1 Disable Synth. Synt. Enable Sel. Synt. Mode Mode GPO11 Data GPO11 Select IRQ5 Enable IRQ5 active GPIO9 GPO19 GPO18 IRQ4 Enable IRQ4 active GPIO8 GPO17 IRQ3 Enable IRQ3 active IRQ2 Enable IRQ2 active GPIO9 Data GPO19 GPO18 GPIO8 Data GPO17 FLASHPWD dis. Edge Pol. Backlight Control Synth. Interface Power Enable Power Control EVBC Interface SW-Reset Deinterleave SW-Reset Interrupt Counter EVBC Read Interface Power Enable Radio Power Control Interface SW-Reset interleave SW-Reset Synthes. Interface SW-Reset Encode SW-Reset Encryption Power Enable Reset Synthesizer Count Synthesizer Load Dynamic Synthesizer Load Dynamic Synthesizer Clock EVBC Rx-Buff. full EVBC Tx-Buf.empty Reset Autocalibration Type GPO10 Data Traffic Frame Enable GPO10 Select EERPOM Clock Decryption Enable Data Ser. Select EEPROM Enable Encryption Enable DAIRESET EERPOM
Keypad Column
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Table Peripheral Control Registers
AD6426
Address
64/65 8040/1h 8042h 8043h 8044h 8045h 8048h 8050h 8051h 8052h 8054h 8055h 8060h 8061h 8062h 8063h 8064h 8065h 8066h 8067h 8068h 8069h 8074h
Name
DISPDDR DISPCR DDOR DDIR WDTR PERST PERCR PERCLK RTCTR1 RTCTR2 RTCTR3 RTCTR4 RTCTR5 RTCAR1 RTCAR2 RTCAR3 RTCCR RTCSRZ SERDISPLAY/NMI
Address
8000h 8001h 8002h 8003h 8004h 8005h 8006h 8010h 8010h 8010h 8011h 8011h 8012h 8012h 8013h 8014h 8015h 8016h 8017h 8018h 8018h 8019H 801AH 801BH 801CH 801Dh 8020h 8020h 8020h 8021h 8021h 8022h 8023h 8024h 8025h 8026h 8027h 8030h 8031h 8032h 8033h 8034h 8035h
Name
SMSMR SMBRR SMSCR SMDR SMSSR SMDR SMSCMR BUFRBR BUFTHR BUFDLL BUFIER BUFDLM BUFIIR BUFFCR BUFLCR BUFMCR BUFLSR BUFMSR BUFSCR UIBRBR UIBTHR UIBSSR UIBER UIBTSR UIBTLR UIBBLR FIXRBR FIXTHR FIXDLL FIXIER FIXDLM FIXIIR FIXLCR FIXMCR FIXLSR FIXMSR FIXSCR SCCR SPSSR SDIR1 (MS) SDIR0 (LS) SDOR1 (MS) SDOR0 (LS)
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Table Peripheral Register Contents
AD6426
64/65
TDRE
RDRF
ORER
Transmit[7:0] Receive[7:0] RxData[7:0] TxData[7:0] BRR[7:0]
BRR[3:0] DATEN CLKPOL TEND
CLKEN
EDSSI BRR[15:8] FIFO FIFO RxLevel[1:0] DLAB Error FIFO TEMT Parity Out2 Framing Error DDCD
ELSI InterruptID[2:0] FIFO Stop Bits Out1 Parity Error TERI
ETBEI
ERBFI
Stick Par. THRE
Parity Loop Break Interrupt SCR[7:0] RxData[7:0] TxData[7:0]
Pend FIFO FIFO WLS[1:0] Overrun Error Data Ready DDSR DCTS
Trigger Level [3:0] Chars Buffer [3:0]
MODEM
MRESET Level
Enable PROC Time Level Trigger Level [3:0] Chars Buffer [3:0]
RxData[7:0] TxData[7:0] BRR[7:0] EDSSI BRR[15:8] FIFO DLAB Error FIFO TEST FIFO TEMT MODE SDORIE Stick Par. THRE CLOCK SDIROE InterruptID[2:0] Parity Parity Loop Out2 Break Interrupt Framing Error DDCD SCR[7:0] ENABLE CROSSPOINT SWITCH SDIRIE Receive[15:8] Receive[7:0] Transmit[15:8] Transmit[7:0] Data[7:0] Pend Stop Bits Out1 Parity Error TERI UCONN SWITCH SDOR WLS[1:0] Overrun Error DDSR SDIR SDIR FULL Data Ready DCTS ELSI ETBEI ERBFI
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Peripheral Register Contents (Continued)
AD6426
DISP CLKEN
FREQ
DDREMT
TEST
Unused
Unused KEYINT USCCLK
INTEN
TIMWEN TIMER
ALAWEN ALARM TXENABLE
SDISP Transmit Data [7:0] Receive Data [7:0] Reset Data [7:0] WDT[7:0] UART DALLAS DALLAS DALLAS Test Key[7:0] BUCLK FUCLK TR[1] TR[2] TR[3] TR[4] TR[5] AR[1] AR[2] AR[3] PWRUEN AGCENN APWRUP SERDISP MODE
SEL7
DISP SSINT DSPPLL[2:0]
SRAM16 MONINT MONIE
FBENN OSCFAIL
Unused PRESENT
Unused TESTOUT
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
GENERAL CONTROL Clocks Clock Input AD6426 requires single MHz, level clock signal, which provided CLKIN. proper operation signal level mVPP minimum required. This feature eases system design reduces need external clock buffering. Only minimal external components required shown Figure internal clock buffer accept regular waveform long find voltage points signal, which duty cycle determined. This condition sinewaves, triangles, slew-limited square waves. Dedicated circuitry searches these points generates respective bias voltage internally. external capacitor (1nF) decouples bias voltage clock signal generated oscillator from internally generated bias voltage clock buffer circuitry. LC-filter shown optional. ensures, that input signal "well behaved" sinusoidal. Additionally filters harmonics noise, that pure signal.
Optional Filter
CLKIN
AD6426
under circumstances. active-high OSC13MON output prevented from becoming inactive 32.768kHz signal present. following table describes functionality relevant pins. Name OSCIN OSCOUT OSC13MON PWRON Function 32.768kHz Crystal Input 32.768kHz Oscillator Output Oscillator Power Control Power ON/OFF Control
following table lists recommended specification 32kHz crystal. Parameter Shunt Capacitance Load Capacitance Turnover Temperature (To) Parabolic Curvature Constant 12.5 0.040 Units ppm/°C
VCTCXO
AD6422
Figure Clock Input Circuitry Clock Output input clock drives both Channel Codec directly. gated version, controlled Output Clock Enable flag Control Register drives CLKOUT EVBC interface. stand-by state CLKOUT logic zero. CLKOUT output will active reset. Slow Clocking reduce power consumption AD20msp425 solutions, slow clocking scheme been designed into AD6426. This scheme allows VCTCXO powered down between paging blocks during Idle Mode 32.768kHz oscillator keep time reference during this period. Only common 32.768kHz watch crystal required take advantage this scheme. previous generations, power consumption also kept minimum using asynchronous design techniques stopping unnecessary clocks. Layer software logic built into AD6426 responsible maintaining synchronization calibration slow clock ensure validity time reference
Real Time Clock Alarm AD6426 provides simple Real Time Clock (RTC) using 32.768kHz clock input. counter allows more than year resolution. module contains 32.768kHz chip oscillator buffer designed very power consumption registers timer, alarm, control status functions. circuit supplied sources; VDDRTC supply main system VDD. handset designer's responsibility provide suitable switching between main system backup supply ensure module permanently powered. VDDRTC intended interface backup battery circuit charge holding network order maintain timing accuracy when main battery removed handset powered down. user alarm time which handset powers alarm time set, current time matches alarm time, power alarm feature enabled, handset powered asserting PWRON period approximately seconds.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
VDDRTC designed interface with either Lithium Battery Capacitor range 0.4F (maximum hours standby) (~30 minutes standby) Reset AD6426 reset setting RESET GND. This will reset H8-processor, Channel Codec, internal well controller interface Boot logic. Both Channel Codec will held reset until RESET register written least CLKIN cycles must elapse before deasserting RESET least further cycles before writing RESET register. reset power must held reset least 2000 clock cycles enable internal lock. RESET Control Register contains following flags: Function EVBC Reset Reset Channel Codec Reset
AD6426
fetches program start vector from location 0x0000 segment zero. This either from external internal Boot ROM, depending status BOOTCODE pin. Interrupts interrupts controlled Control Registers These registers only apply Emulation Mode, that they define which interrupts able assert CCIRQ2. ENABLE Control Register Enable Enable Enable Enable LATCH Control Register active active active active
Additionally functional modules reset under control SWRESET registers: SWRESET Control Register Encryption Software Reset EVBC Interface Software Reset Interface Software Reset Synthesizer Interface Software Reset SWRESET Control Register Decode Software Reset Deinterleave Software Reset Interleave Software Reset Encode Software Reset
non-maskable interrupt input processor multiplexed with IRQ6 pin. IRQ6 default function, though asserting Select flag Control Register will select function. When selected, will tied high internally, though remains driven JTAG port test purposes. signal programmable edge level sensitive. defaults falling edge. edge polarity changed programming However, FLASHPWD used then same setting must applied Control Register default zero implies falling edge sensitive. This going active correctly deassert FLASHPWD. used test purposes user defined features. capable bringing control processor software standby mode therefore suitable functions such alarm inputs, power management etc. During manufacture used trigger special test code. addition generated internally thus freeing IRQ6 PIN. this mode TXENABLE will occur rising edge TXENABLE seen pin. should negative edge this case. Setting SERDISPLAY/NMI Peripheral Control Register enables TXENABLE NMI. However, Layer Software must program external INT6 before register set.
JTAG circuitry reset power-on reset mechanism. Further resets must done asserting input high least five clock cycles. When JTAG compliance re-enabled, JTAG reset forcing AD6426 into normal mode operation, selecting BYPASS register default.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Wait microprocessor WAIT input signal controlled externally programming FLASHPWD switch WAIT input function. Setting flag FLASHPWD Disable Control Register GPO11 Select transforms FLASHPWD output into WAIT input pin. External devices driving WAIT must drive high reset until software changed FLASHPWD WAIT function. Automatic Booting allow download FLASH memory code into final system, AD6426 provides small dedicated routine transfer code through Data Interface into FLASH memory. This routine activated asserting BOOTCODE pin. Power Control AD6426 Layer software optimized minimize mobile radio power consumption modes operation. power control registers dedicated activating deactivating functional modules: POWER CONTROL INTERNAL Control Register Synthesizer Interface Power Enable Interface Power Enable Encryption Power Enable POWER CONTROL EXTERNAL Control Register Output Clock Enable (will reset General Purpose Power Control Power Control Radio Power Control
AD6426
Memory Interface memory interface AD6426 serves purposes. Primarily, provides data, address, control lines external memories (RAM FLASH Memory). Secondly, data address lines used interface with display. pins memory interface listed Table Table Memory Interface Name ADD20 DATA15:0 RAMCS ROMCS FLASHPWD Function Address Data Read strobe High write strobe Upper Byte Strobe write strobe Lower Byte Strobe Write Strobe chip select FLASH chip select FLASH Powerdown
pins configured function LBS, respectively, setting SRAM16 (bit MEMIF Peripheral Control Register This reset power-up. When configured LBS, these pins facilitate access 16-bit SRAM conjunction with Read/Write Strobes. FLASHPWD automatically asserted when enters Software Standby Mode, de-asserted when interrupt causes exit Software Standby Mode. This allows "deep power down mode" certain FLASH memories. Also entire data driven during software standby mode. EEPROM Interface AD6426 provides 3-wire interface external EEPROM using three GPIOs control processor. Table shows functionality these three pins. Table EEPROM Interface Name EEPROMDATA EEPROMCLK EEPROMEN Function EEPROM data EEPROM clock EEPROM enable
INTERFACES Processor provides eleven external interfaces dedicated purposes: Memory Interface EEPROM Interface Interface Accessory Interface Universal System Connector Interface Keypad Backlight Display Interface Battery Interface Voiceband/Baseband Converter (EVBC) Interface Radio Interface Test Interface Debug Interface
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
EEPROM interface controlled entirely through software EEPROM register. This allows support every desired timing protocol. EEPROM Control Register EEPROM Data Output Enable when content will written pin. EEPROM Clock Connected EEPROMCLK EEPROM Enable Connected EEPROMENABLE EEPROM Data Connected EEPROMDATA
AD6426
reflects input state when read writing GPIOn Data effect. When GPIOn Enable flag GPIOn Data flag returns when read last value written controls GPIOn when written Additional general purpose inputs outputs available under software control. following pins shown Table become general purpose inputs/outputs outputs. Table Additional GPIO Pins Name SIMCARD SIMPROG ADD20 FLASHPWD TXPA CALIBRATERADIO TXENABLE SYNTHEN1 AGCA AGCB USCRI USCRTS USCCTS Function GPIO16 GPIO15 GPO10 GPO11 GPO12 GPO13 GPO14 GPO17 GPO18 GPO19 GPO20 GPO21 GPI22
Interface AD6426 allows direct interfacing card dedicated interface. This interface consists pins shown Table Some applications require SIMPROG SIMCARD; thus SIMPROG SIMCARD re-used additional general purpose I/O-pins. Table Interface Name SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY Function card detect data output data input clock reset program enable supply enable
pins SIMCARD SIMPROG required application, they used additional programmable general purpose inputs outputs. Setting GPO10 Select Control Register will transform ADD20 into general purpose output allowing directly controlled GPO10 Data. setting GPO11 Select Control Register FLASHPWD Disable FLASHPWD becomes general purpose output. state toggled setting GPO11 Data flag. increase flexibility AD6426, three pins Radio Interface multiplexed within functions. pins multiplexed are: SYNTHEN1, AGCA AGCB, with default function being Radio Interface. mode these pins controlled Channel Codec Register ccGPO. GPO[n]Sel selects function pin. Setting GPO[n]Sel will enable controlled GPO[n] bit. GPO[n]Sel will override other function selection.
Accessory Interface AD6426 provides interface pins listed Table control peripheral devices such kit. However, general purpose I/O-pins Accessory Interface proposed used additional control radio section described Radio Interface chapter. Table Accessory Interface Name GPIO9:0 GPCS Function General purpose inputs/outputs General purpose chip select
GPIO pins start inputs. GPIO8 GPIO9 controlled flags Control Register When GPIOn Enable flag GPIOn Data flag
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
transform TXPA into general purpose output, TXPA Width Control Register 76), then TxPA Polarity flag Control Register toggle state. CALIBRATERADIO general purpose output, AUTOCALIBRATE flag zero CALIBRATERADIO flag toggle state. Universal System Connector Interface typical handset requires multiple serial connections provide data during normal phone operation, manufacturing, testing, debug. ideal case many these functions could combined into single multi-purpose system connector. example, port used for: Operating modes
AD6426
Buffered UART Mode (Booting/Data Services) This mode attaches H8/DSP buffered UART USC, bringing either serial rate clock Modem Control Signal This default mode when phone powered BOOTCODE will latched RESET high. BOOTCODE high RESET, execution begins from Boot which will configure buffered UART download FLASH programming code into RAM. FLASH program itself also downloaded UART. external Data Terminal Adapter also used. this case Data Services done external phone then transferred from With external Data Terminal Adapter, serial rate clock output selected USCRI pin. This mode used variety debug tasks UART used simply shift debug information out. Note that when this mode handshake signals serial clock required, pins used extra GPO, used extra GPI. Time-shared Mode (Multi-switch) This mode allows time multiplexed communication with both DSP. This most useful hands-free solution, used other purposes also e.g., Transcoding Testing. This mode used testing DSP's speech transcoder which DSP's SPORT0 connected through Multi-switch. Acoustic Mode Testing This mode used testing 6425's phone's acoustic properties. VSPORT 6425 connects through Multi-switch. Monitoring This mode used testing receive path allows access samples from AD6425. AD6425 signals simply routed USC. This means that clock frame sync provided 6425 well. Mode This mode connects synchronous data path SDIR/SDOR Peripheral Control Registers, giving full access synchronous port bandwidth. This allows fast synchronous communication external device, intended used fast download mechanism.
Flash code download manufacturing updates Booting UART interface used download programs memory Acoustic mode testing connects System Simulator (SS) directly EVBC Transcoding mode connects 6426 speech codec testing External (Data Terminal Adapter) asynchronous link MSDI interface RS232 port on-board data services debug monitor Hands-free operation time shared port Receive monitoring
Universal System Connector (USC) 6426 designed such that external glue logic required achieve this multi-purpose functionality. Furthermore, since USC's function related voiceband data serial ports, block also responsible correct configuration these serial data streams. actual system connector minimum number pins achieve needed functionality. This save system pins, allows more reliable connector from manufacturing mechanical standpoint. defines connector that multiplexes asynchronous, synchronous, modem control signals needed: Name USCRX USCTX USCRTS USCCTS USCRI Function Receive Data Transmit Data Ready Send Clear Send Transmit Frame Sync Ring Indicator Serial Clock
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Keypad Backlight Display Interface This interface combines functions display keyboard shown Table Table Keypad Backlight Display Interface Name KEYPADROW5 KEYPADCOL3 BACKLIGHT DISPLAYCS LCDCTL GPIO3 GPIO4 Function Keypad inputs Keypad column strobes Backlight control Display Controller chip select Control Serial Display Data Output Serial Display Data Output Serial Display Clock Output Frequency 6.3475 12.695 25.390 50.780
AD6426
BACKLIGHT Control Register Modulate Backlight Control (1:0)
frequency determined flags Backlight Control (1:0) same register shown Table Table Backlight Frequency
providing keypad-column outputs (open drain, pull low) keypad-row inputs AD6426 monitor keys. Additionally, extra column implemented using "ghost column" method total keys. processor interrupted whenever pressed. KEYPADCOL pins connected Keypad Column3-0 flags KEYPAD COLUMN Control Register KEYPAD COLUMN Control Register Keypad Column
Duty cycle selected between 124/128 steps 4/128 programming Backlight Duty Cycle (4:0) flags POWER CONTROL INTERNAL Control Register POWER CONTROL INTERNAL Control Register Backlight Duty Cycle (4:0)
active period determined according formula: Active (high) Period Backlight Duty Cycle (4:0)
KEYPADROW pins connected Keypad flags KEYPADROW Control Register KEYPADROW Control Register Keypad
6426 offers both parallel serial interfaces connecting display controllers. parallel interface controller provided dedicated control signals (LCDCTL DISPLAYCS) parts address data bus. typical interface shown Figure
Controller
DATA (7:0)
backlight control output (BACKLIGHT) provided, which modulated provide same perceived brightness reduced average current. Switching frequency well duty cycle modified compensate ambient lighting levels changing battery voltage. BACKLIGHT output activated setting Backlight1 flag SYSTEM Control Register SYSTEM Control Register
AD6426
DATA (15:8) LCDCTL ADD(0) DISPLAYCS
Backlight Once activated, internal circuit control frequency duty cycle output signal. circuit enabled Modulate1 flag BACKLIGHT Control Register switch backlight continuously enable Backlight flag disable Modulate flag.
Figure Parallel Display Interface on-chip control circuit automatically generates wait states interfacing external display devices.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Serial Display Interface serial display interface compatible with display drivers Motorola Seiko-Epson. display driver Motorola uses serial which requires inverted delayed clock comparison Seiko-Epson type display driver. Motorola mode data delayed half clock cycle such that data driven rising edge SCLK instead falling edge. serial display interface consists four pins; serial data output (DISPD0), clock (DISPCLK), chip enable (DISPEN) address (DISPA0). These pins multiplexed with GPIO4, GPIO3, LCDCTL DISPLAYCS. (DISP) MEMIF Peripheral Control Register controls configuration display interface. With this parallel display interface used. Setting this enables serial display interface. This reset. (SERDISP MODE) SERDISPLAY/NMI Peripheral Control Register controls serial display mode. default setting Seiko-Epson mode. enable Motorola mode user must register ONE. Display Reset dedicated used reset display system. recommended that VBCRESET used this function connecting Reset input display Reset input AD6426 VBCRESET pin. display cannot reset independently. However GPIO pins used reset display separately. Battery Interface AD6426 provides single-wire interface compatible with Dallas SemiconductorDS2434or DS2435 Battery Identification chip. communication protocol supports three operations: RESET, READ WRITE. These operations permit reading present status battery writing updated information chip. interface available BATID function multiplexed GPIO5 pin.
AD6426
(DALLAS MEMIF Peripheral Control Register controls enabling battery interface module. Setting this zero enables interface, resetting disables This reset. EVBC Interface AD6426 interfaces directly Enhanced Voiceband Baseband Converter AD6425 through pins shown Table 12.The communication performed through three serial ports: Auxiliary Serial Port (ASPORT), Baseband Serial Port (BSPORT) Voiceband Serial Port (VSPORT). Layer software enables/disables clock output order reduce system power consumption minimum operation AD6425 required. Figure shows interface between AD6426 AD6425 well AD6432 chip. Table EVBC Interface Name CLKOUT EVBCRESET ASPORT ASDO ASOFS ASCLK ASDI BSPORT BSDO BSOFS BSCLK BSIFS BSDI VSPORT VSDO VSDI VSCLK VSFS Function Clock Output EVBC Reset Output EVBC Data Output Output Framing Signal Clock Output Data Input Data Output Output Framing Signal Clock Input Input Framing Signal Data Input Data Output Data Input Clock Input Input/Output Framing Signal
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
CLKIN MCLK RESET ASDI ASDIFS ASDOFS ASCLK ASDO BSDI BSDIFS BSCLK BSDO BSDOFS MODE VSDO VSDI VSCLK VSFS VSDI VSDO VSCLK VSFS
AD6426
XTAL
CLKOUT VBCRESET ASDO ASOFS ASCLK ASDI BSDO BSOFS BSCLK BSDI BSIFS
AD6425
XTAL TCOR BREFOUT GREF
RFCLK
AD6432
MXOP IFHI FILTER
ITXP ITXN QTXP QTXN IRXP IRXN QRXP QRXN
GAIN ITXP ITXN QTXP QTXN IRXP IRXN QRXN QRXP OSEN RXPU TXPU RFHI RFLO
FILTER
RMX_OUT MODP MODM TX_IN
FREF
TMX_OUT
Control
FILTERS
LNA-IN
RXON TXON RAMP
DUALBAND FRONT-END
RXON TXON GSM_ON DCS_ON
RXON TXENABLE GPIO2 GPIO1 RADIOPWRCTL
BANDSELECT0 BANDSELECT1
RFLO
GSM_ON RFLO DCS_ON SYNTHCLK SYNTHDATA SYNTHEN0 GPIO7 TXPHASE TXPA DCLK DATA RFCLK
VCOs SYNTHESIZERS
ANTENNASELECT
Figure EVBC Radio Interface
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Radio Interface
AD6426 Radio Interface been designed support direct connection IF-Chips AD6432, while providing full backwards compatibility existing radio designs interfacing AD20msp410 AD20msp415. Additionally AD6426 Radio Interface supports radio architectures based Siemens, TTP/Hitachi Philips chipsets. Radio Interface AD6426 consists dedicated output pins listed Table Together with optional general purpose I/O-pins they provide flexible interface variety radio architectures both 1800/1900 operation.
AD6426
CONTROL), gated with RADIO POWER CONTROL force output when Radio off. order increase flexibility AD6426, three pins Radio Interface multiplexed with functions. pins multiplexed are: SYTHEN1, AGCA AGCB, with default function being Radio Interface. mode these pins controlled ccGPO Channel Codec Register: GPO[n]Sel selects function pin. Setting GPO[n]Sel will enable controlled GPO[n] bit. GPO[n]Sel will override other function selection. Generic Pins following three pins have same functionality types radio architectures: RADIOPWRCTL This output signal typically used power down oscillators prescalers during Idle mode directly controlled Radio Power Control flag POWER CONTROL EXTERNAL Control Register POWER CONTROL EXTERNAL Control Register Radio Power Control Table Radio Interface Name GPIO1 GPIO2 RADIOPWRCTL GPIO6 GPIO7 TXPHASE TXENABLE TXPA RXON CALIBRATERADIO SYNTHEN0 SYNTHEN1 SYNTHDATA SYNTHCLK AGCA AGCB Function BANDSELECT1 BANDSELECT0 Radio Powerdown Control VBIAS ANTENNASELECT Switches PLLs Transmit Enable Power Amplifier Enable Receiver Radio Calibration Synthesizer Enable Synthesizer Enable Synthesizer Port Serial Data Synthesizer Port Clock Control Control
Dual Band Control
support dual band handsets BANDSELECT[1:0] signals provided. BANDSELECT0 multiplexed with GPIO[2], with default function this being GPIO[2]. BANDSELECT1 multiplexed with GPIO[1], default function being GPIO[1]. Dual Band solutions requiring single band select bit, BANDSELECT0 function enabled asserting BAND bit. order BANDSELECT0 high/low cause radio module operate appropriate band, least significant (bit relevant register Dynamic Synthesizer must written, i.e. different values Monitor only Dynamic Synthesizer BANDSELECT0 sampled internally valid from beginning data serialization, both demand (immediate) loading ordinary interrupt driven loading. BANDSELECT0 signal will remain this known state until next time there serialization data Dynamic Synthesizer when sample will taken least significant synthesizer register currently being serialized. Full control provided over number bits shifted synthesizer intended that this count will always less than when using BANDSELECT0 feature order prevent shifting control out. BANDSELECT0 gated with RADIO POWER CONTROL ensure that whenever RADIO off, BANDSELECT0 forced state. Dual Band Solution requiring band select bits, GSM900, DCS1800, then both BANDSELECT0 BANDSELECT1 enabled asserting both BAND DCSSEL bits. BANDSELECT0 output driven single enable mode (described above), BANDSELECT1 output inverted output BANDSELECT0 output (prior gating with RADIO POWER
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
GPIO6 VBIAS This general purpose used control powering up/down separate voltage converter, which needed provide supply voltage GaAs Power Amplifiers. Significant turn-on time voltage converter requires early power-up signal, which provided GPIO6. This control achieved entirely through software driver, without hardware support. Since this function needed radio solutions, GPIO used other functions required. GPIO7 ANTENNASELECT This general purpose used switch between different antennas, required, when mobile radio used conjunction with car-kit with external antenna. This control achieved entirely through software driver, without hardware support. Since this function needed radio solutions, GPIO used other functions required. Timing Control following radio interface pins serve different functions depending radio architecture: TXPHASE purpose this signal switch PLLs between modes. signal generated under control flags TXPHASE Enable TXPHASE Polarity RADIO CONTROL Control Register RADIO CONTROL Control Register TXPHASE Polarity Controls polarity output TXPHASE. When TXPHASE active low; When TXPHASE active high. TXPHASE Enable Enables output TXPHASE Transmit Enable Enables output TXENABLE
AD6426
TXPA This signal used power amplifier (PA) enable and/or control signal control loop. This allows isolated from supply outside Tx-slot save current. control loop used control dynamics loop. flag Polarity TRAFFIC MODE Control Register provides independent control TXPA signal. TRAFFIC MODE Control Register Polarity; active high, when reset
TXPA derived from leading edge TXENABLE signal shown Figure
TXENABLE TXPA
Figure Timing TXPA parameter programmable delay 1023 QBIT) accommodate EVBC settling time. therefore value, accessed TXPA OFFSET Control Register TXPA OFFSET Control Register TXPA OFFSET Control Register (9:8) TXPA OFFSET Control Register (7:0)
parameter programmable width 1023 QBIT) which defines enable time. therefore value, accessed TXPA WIDTH Control Register TXPA WIDTH Control Register TXPA WIDTH Control Register (9:8) TXPA WIDTH Control Register (7:0)
radios based TTP/Hitachi solution, this signal used switch radios based Siemens Philips solution, this signal used control switching PLLs, band switching PLLs. TXENABLE This signal enables modulator transmit chain including controls TXON-pin AD6425. signal generated under control flag Transmit Enable RADIO CONTROL Control Register
zero, then TXPA will disabled.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Timing Control RXON signal output RXON generated function Receive Enable Monitor Enable RADIO CONTROL Control Register used enable receiver controls RXON-pin AD6425. radios based Siemens solution this signal would connected RXON1 input. Additional RXON derived signals provided support this solution. RADIO CONTROL Control Register Monitor Enable Receive Enable
AD6426
Synthesizer Control radio interface AD6426 supports dynamic synthesizers, with each capable downloading data demand. Synthesizer Load Dynamic flags located SYNTH CONTROL Control Register will synthesizer interface load consecutive long-words from Layer SYNTH CONTROL Control Register Synthesizer Enable Polarity Selects polarity SYNTHEN outputs. SYNTHEN active signal, SYNTHEN active high signal. Synthesizer Enable Type Selects active period SYNTHEN outputs. When SYTHEN active data values determined SYNTHESIZER COUNT; when SYNTHEN goes active after last SYNTHCLK period. Synthesizer Load Dynamic (SLD1) Synthesizer Load Dynamic (SLD0)
CALIBRATERADIO modes Autocalibrate signal (Type AutoCal on/off) provided required Philips solution shown Figure
RXON RxEnable RxEnable Start (early) Start (late) AutoCalibrateEnd TYPE=0, AUTOCAL=0 RxEnableEnd
TYPE=0, AUTOCAL=1
When using Configure Dynamic Synthesizer flag SYNTH COUNT Control Register downloadon-demand function applied synthesizer selected SLD0 SLD1. Figure Autocalibration SYNTH COUNT Control Register Configure Dynamic Synthesizer
TYPE=1, AUTOCAL=0
TYPE=1, AUTOCAL=1
flags Autocalibrate Calibrate Radio SYSTEM Control Register connected output CALIBRATERADIO. SYSTEM Control Register Autocalibrate Enables autocalibrate function Calibrate Radio
Each dynamic synthesizer comprised three 32-bit word registers, Monitor phases. download demand uses register only respective synthesizer. SYNTHESIZER Control Register Synthesizer (31:24) SYNTHESIZER Control Register Synthesizer (23:16) SYNTHESIZER Control Register Synthesizer (15:8) SYNTHESIZER Control Register Synthesizer (7:0)
type autocalibration TRAFFIC MODE Control Register TRAFFIC MODE Control Register Autocalibration Type
radios based Siemens chipset, this signal would connect RXON2 input. required behavior enabled selecting Type CalibrateRadio function.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
dynamic synthesizers programmable follows, while each synthesizer independently disabled, through Disable Synthesizer flags SYNTHESIZER PROGRAM Control Register SYNTHESIZER PROGRAM Control Register Disable Synthesizer Disable Synthesizer Synthesizer Enable Select Synthesizer Mode Mode (1:0)
AD6426
SYNTH CONTROL Control Register Synthesizer Clock Polarity Selects edge, which synthesizer data enable will clocked out. Negative edge, when positive edge, when Synthesizer Clock; selects frequency SYNTHCLK output. SYNTHCLK 1.625 (default), SYNTHCLK
SYNTHEN0 AD6426 provides enable signals independent synthesizers. These signals available output pins SYNTHEN0 SYNTHEN1. polarities these signals individually programmable; i.e. Control Register applied synthesizer selected either same register. SYNTHDATA SYNTHCLK Three Modes selected support different radio architectures. selection Pin-Mode done Mode flags SYNTHESIZER PROGRAM Control Register shown Table Table Mode Mode Mode (default) Mode Mode Mode
Modes outputs these pins multiplexed with flags internal indicated Table function DSPFLAG1 Synthesizer Data defined output that DSPFLAG1 except when synthesizer interface active. this case synthesizer output priority. same applies DSPFLAG2 Synthesizer Clock. Table Function Modes AD6426 SYNTHDATA SYNTHCLK Function DSPFLAG1 Synthesizer Data DSPFLAG2 Synthesizer Clock
Control programming achieved three ways: first gain select approach, whereby DSPFLAG0 DSPFLAG1 used 2-bit gain selector (AGCA, AGCB). This available Mode flags under direct control internal timing independent synthesizer interface. Table Function Mode AD6426 AGCA AGCB Function DSPFLAG0 DSPFLAG1
default Mode which supports TTP/Hitachi Bright Philips radio architectures. Mode also supports Philips architecture, while Mode supports Siemens architecture. Mode pins SYNTHDATA SYNTHCLK have their original functionality; i.e. SYNTHDATA data output SYNTHCLK clock output serial synthesizer interface. Clock polarity frequency programmed SYNTH CONTROL Control Register Table Function Mode AD6426 SYNTHDATA SYNTHCLK Function Synthesizer Data Synthesizer Clock
second through combined with serial synthesizer interface, defined Mode function DSPFLAG0 SYNTHEN1 defined output that DSPFLAG0 except when synthesizer interface active. support Philips chipset whereby programmed over same enable line, AGCA multiplexed provide SYNTHEN1 gated with DSPFLAG0. This would wired instead SYNTHEN1 pin. Since would program during RXON, synthesizers reprogrammed following active phase, conflict occur.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Modes programming occurs MonEnableEnd through synthesizer interface. Additionally, programming, controlled DSP, performed during RXON. Table Function Mode AD6426 AGCA AGCB Function DSPFLAG0 SYNTHEN1 DSPFLAG1
AD6426
third mode support Siemens chipset, providing independent enable from SYNTHEN using Flag same serial interface constraints from Mode apply. Additionally, output provided. This Offset Correction Enable, derived from RxEnableStartEarly RxEnableStartLate timing signals shown Figure Table Function Mode AD6426 AGCA AGCB Function DSPFLAG0
RxEnableStartEarly RxEnableStartLate RXON
Figure Signal
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
TEST INTERFACE AD6426 provides complete JTAG test interface. functionality these pins shown Table Furthermore, these pins assume different functionality described detail chapter MODES OPERATION. Table Test Interface Name JTAGEN Function JTAG enable (internal pull down resistor) JTAG test clock input JTAG test mode select JTAG test data input JTAG test data output 0111 10001110 1111 Bypass Bypass Table JTAG Instructions Instr. Register 4321 0000 0001 0010 0011 01000101 0110 Mode ExTest Clamp Sample/PreLoad DoBist Code Comments
AD6426
Public Instruction Optional Public Instruction Public Instruction Private Instruction Engineering Mode Test Reserved Private Instruction Emulation Reserved Public Instruction Selects Mode Public Instruction Selects Mode (default)
JTAG Port AD6426 provides full IEEE 1149.1 compliance. JTAG Port must frequency less. JTAG Port explicitly enabled through JTAGEN. When disabled, corresponding pins re-used AD6426 Feature Modes. JTAG interface implements four registers shown Figure content Instruction register selects these four registers.
Boundary Register Bypass Register
ExTest Instruction ExTest instruction used force input output conditions boundary scan cell. Clamp Instruction This optional public instruction similar Bypass instruction, except that once loaded, will force values held boundary scan chain onto corresponding outputs device. This enables output bidirectional pads fixed, allowing other parts PCboard tested without interference from AD6426, while same time selecting Bypass register shortest possible scan path. input activity AD6426 will ignored during this time, since inputs driven from preloaded values boundary scan chain. Typically therefore this instruction would preceded Sample/Preload instruction. This instruction only valid during normal operation AD6426; i.e. Mode Sample/Preload Instruction Sample/Preload instruction fully IEEE compliant. Boundary Register boundary cell structure based definition Mode hence pins which outputs only this mode, become inputs another mode, support input scan cells, vice versa. Table shows complete Boundary register.
Bist Register
Instruction Register
Figure JTAG Registers instruction register contains bits, supports instructions listed Table Instruction register values 01XX select bypass register when JTAG compliance enabled. Values 00XX control AD6426 defined Mode therefore should used other mode.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Table Boundary Scan Path
Cell Name SIMCARD SIMCARD SIMCARD SIMCLK SIMDATAOPEN SIMDATAOP SIMDATAIP SIMRESET SIMPROG SIMPROG SIMPROG SIMSUPPLY GPIO0EN GPIO0 GPIO0 GPIO1EN GPIO1 GPIO1 FLASHPWD FLASHPWD FLASHPWD DATA0 DATA0 DATA0 DATA1 DATA1 DATA2 DATA2 DATA3 DATA3 DATA4 DATA4 DATA5 DATA5 DATA6 DATA6 DATA7 DATA7 DATA8 Cell Name DATA8 DATA8 DATA9 DATA9 DATA10 DATA10 DATA11 DATA11 DATA12 DATA12 DATA13 DATA13 DATA14 DATA14 DATA15 DATA15 ROMCS RAMCS ADD0 ADD1 ADD2 ADD4 ADD5 ADD6 ADD7 ADD8 BOOTCODEEN ADD9 ADD10 ADD11 ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 USCRTS USCCTSEN USCCTS Cell Name USCCTS USCTX USCRXEN USCRX USCRX USCRI GPIO9EN GPIO9 GPIO9 GPIO8EN GPIO8 GPIO8 IRQ6 RESET KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 KEYPADCOL0EN KEYPADCOL0 KEYPADCOL1EN KEYPADCOL1 KEYPADCOL2EN KEYPADCOL2 KEYPADCOL3EN KEYPADCOL3 GPCS OSC13MON BACKLIGHT DISPLAYCS LCDCTL GPIO3EN GPIO3 GPIO3 GPIO4EN GPIO4 GPIO4 GPIO5EN GPIO5 GPIO5 GPIO6EN
AD6426
Cell Name
GPIO6 GPIO6 GPIO7EN GPIO7 GPIO7 CLKIN TXENABLE RADIOPWRCTL CALIBRATERADIO TXPA AGCB AGCA SYNTHCLK SYNTHDATA SYNTHEN0 SYNTHEN1 PWRON OSCIN GPIO2EN GPIO2 GPIO2 TXPHASE ASDO ASOFS ASDI ASCLK BSCLK BSDI BSIFS BSOFS BSDO CLKOUT RXON VBCRESET VSCLK VSDI VSFS VSDOEN VSDO EEPROMDATAEN EEPROMDATA EEPROMDATA EEPROMCLK EEPROMEN
Notes: boundary scan supports only functionality signal directions Normal Mode (A); chapter "Modes Operation". Cells input output cells which correspond pins with same name, internal control cells shown ITALIC. Control cells either bi-directional control cells (B), tri-state output control cells (T). When type-B cells loaded with referred pins become driving output pins, otherwise pins inputs. When type-T cells loaded with referred will tri-stated, otherwise output.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
DoBist Instruction This instruction provided support engineering mode test. When instruction loaded, will generate processor. This will enable special software executed which used test operation device. During this time, 8-bit DoBist register selected scan, enabling result code test scanned out. duration test, retain their normal function. test program must therefore cope with undefined inputs, able communicate with other devices extend test procedure. This allows generated during normal phone operation. This instruction only valid during normal operation AD6426; i.e. Mode Mode Instruction This instruction switches AD6426 into Emulation Mode (Mode only valid switch modes while AD6426 held reset. Reset comply with IEEE specification, JTAG interface will forced reset whenever JTAG Port re-enabled. This will select Bypass register force AD6426 into Normal Mode (Mode Debug Port Interface normal (voice-service) operation, Universal Serial Port used monitor port, which allows monitoring internal operation channel codec section. However, during Data Services, engaged data communication cannot used monitoring. 6426 provides Debug Port enable monitoring debugging this case. This form simple UART. communication format fixed 9600 baud, data bits, stop bit, parity, asynchronous communication. Operation Debug Port under control Layer software. GPIO pins programmed used Debug Port: Name GPIO8 GPIO9 Function TXDATA RXDATA
AD6426
Table Modes Operation Mode Operation Normal Mode Reserved Reserved Emulation Mode (H8)
Normal Mode (Mode This mode used during normal operation AD6426. JTAG-pins have their normal functionality, when enabled JTAGEN used production test. Emulation Mode (Mode Selecting Mode allows emulation internal processor. this Mode several pins assume functionality longer available. Table lists pins, which have different functionality direction Emulation Mode compared Normal Mode. Emulation Mode internal remains active will have access external memory devices. internal will switched into hardware stand-by mode; controller interface Boot Code remain functional. CCIRQ0 channel codec interrupts emulator. CCIRQ2 defined Control Registers Table Functions Mode Name Normal Mode IRQ6 ADD19 ADD15 DATA7 RAMCS SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY GPIO9 GPIO8 Function Emulation Mode CCCS ADD15 CCIRQ0 CCIRQ2 CCIRQ1 H8CS0 CCGPIO8
serial port enabled asserting flag DATA SERIAL PORT SELECT Control Register MODES OPERATION AD6426 switched between main operating modes, using instructions downloaded JTAG interface. This must done while AD6426 held reset. Once instruction load completed pins immediately reflect operating mode. Table shows these modes. modes reserved available user.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
Name Normal Mode GPO10 GPCS FLASHPWD DISPLAYCS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Function Emulation Mode WAIT Forced High DISPLAYCS Reserved Forced High/ BANDSELECT1 Forced High/ BANDSELECT0 Forced High/DISPA0 Forced High/DISPCLK Forced High/BATID Reserved Reserved AD6426 EEPROMCLK FLASHPWD also used WAIT input, which case routed through gated with LCDWAIT output WAIT output GPO10/ADD20. on-chip controller used emulation, then ADD20 used ccGPO(10). FEATURE MODES additional features enabled under software control. These are; Mode (Digital Audio Interface) Mode (High Speed Logging) used monitor operation on-chip DSP. Mode This mode selected during type approval, when Digital Audio Interface required. enable this feature, JTAGEN must de-asserted, upon which JTAG pins TMS, re-assigned shown Table default feature mode thus enabled DAI. addition, voiceband serial port signals made available through facilitate testing speech transcoder well phone's acoustic properties. interface product available upon request from Analog Devices. Table Mode AD6426 VSCLK VSFS VSDO VSDI Function Mode MSCLK MSFS MSRXD MSTXD DAIRESET DAI1 DAI0 EERPROMEN
AD6426
High Speed Logging This mode selected monitoring operation internal during development field test phase. When JTAGEN de-asserted HSLEnable flag TESTADDRESS Control Register set, high speed logging port mapped JTAG- EEPROM pins shown Table internal must then instructed Layer output logging messages onto pins. Table Mode Function Mode HSLDO0 HSLDO1 HSLDO2 HSLDO3 HSLCLK HSLFS
High Speed Logging port (HSL) unidirectional port which supplies nibble-wide synchronous data from internal external data logger. data logger will connected which will responsible presenting data user. able configure either serial interfaces. enabled follows: JTAGEN enables logic setting HSLEnable flag command issued through Data Interface, configures software enable
HSLEnable flag used deselect DAIRESET favor onto JTAG pins, enable onto EEPROMCLK EEPROMEN. sends data over port writing address 0x000 Data Memory map. writes full 16-bit writes, occur maximum rate write five clock cycles. Five cycles allow time circuit serialize bits data onto 4-bit data with cycle spare. HSLFS used frame valid data nibbles. Note that HSCLK free-running that HSLFS HSLDO3-0 synchronized rising edge HSCLK.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
mapping data bits port bits Table Mapping Port Nibbles Data Bits HSLDO Nibble
AD6426
HSCLK
HSLFS HSLDO (3:0)
Figure Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
General
0.250 19.5
SPECIFICATIONS
Parameter
Ambient Operating Temperature Supply Voltage Supply Current (Idle Mode) Supply Current (Talk Mode) fCLKIN Clock Input Frequency VCLKIN Clock Input Voltage RCLKIN, Clock Input Resistance (see Note) Logic Inputs Input High Voltage Input Voltage Input Current Input Capacitance Logic Outputs Output High Voltage Output Voltage IOZL Level Output 3-State Leakage Current IOZH High Level Output 3-State Leakage Current Volt Volt
Units
Volt
Comments
sine wave, ac-coupled sine wave, ac-coupled
Note: input impedance clock buffer function voltage waveform clock input signal. sinusoidal input signals typical input impedance calculated VCLKIN [VPP]
ABSOLUTE MAXIMUM RATINGS
-0.3V Digital Voltage .-0.3V 0.3V Operating Temperature Range -25°C +85°C LQFP Package Storage Temperature Range -65°C +150°C Maximum Junction Temperature +150°C Thermal Impedance.28°C/W Lead temperature, Soldering Vapor Phase sec). +215°C Infrared sec). +220°C PBGA Package Storage Temperature Range -65°C +150°C Maximum Junction Temperature +150°C Thermal Impedance.30°C/W Lead temperature, Soldering Vapor Phase sec). +215°C Infrared sec). +220°C
Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections implied. Exposure absolute maximum rating conditions extended periods affect device reliability. +25°C unless otherwise stated.
SUSCEPTIBILITY (electrostatic discharge) sensitive device. Electrostatic charges high 4000 volts, which readily accumulate human body test equipment, discharge without detection. Although this device features proprietary protection circuitry, permanent damage still occur this device subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Clocks
76.9 76.9 Units
TIMING CHARACTERISTICS
Parameter Comment CLKIN Period (see Figure CLKIN Width CLKIN Width High CLKOUT Period (see Figure CLKOUT Width CLKOUT Width High
CLKIN
Ouput 50pF
+2.1V
Figure Clock Input
CLKOUT
Figure Load Circuit Timing Specifications
Figure Clock Output
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Memory Interface
Units
TIMING SPECIFICATION
Parameter Comment Timing 3-state access, Figure
Timing Requirement t10b t12b Control Processor read chip select data valid Control Processor read address data valid Control Processor read enable data valid Control Processor data hold
Switching Characteristic t10a t12a Control Processor write chip select setup Control Processor chip select hold Control Processor write address setup Control Processor address hold Control Processor write pulse width Control Processor data setup Control Processor data hold Control Processor read pulse width
WRITE
t10a t12a 15:0 HWR/LWR DATA15:0
READ
t10b ADD15:0 t12b DATA7:0
Figure Memory Interface Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Radio Interface
TIMING CHARACTERISTICS
Parameter
t42a t42b t43a t43b
Comment Figure
Synthesizer clock period Synthesizer clock high Synthesizer data setup Synthesizer data hold Synthesizer enable delay Type Synthesizer enable delay Type Synthesizer enable width Type
Units
SYNTHCLK t42a SYNTHDATA t43a SYNTHEN[0:1] TYPE t42b
SYNTHCLK t42a SYNTHDATA t42b SYNTHEN[0:1] TYPE t43b
Figure Synthesizer Interface Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
High Speed Logging Interface
25.6 Units
TIMING CHARACTERISTICS
Parameter Comment Figure HSCLK Period HSCLK Width HSCLK Width High HSCLK HSLDO HSCLK HSLFS
HSCLK HSLFS HSLDO3:0
Figure High Speed Logging Interface
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Data Interface
Units
TIMING CHARACTERISTICS
Parameter Data Interface (see Figure Clock Period Transmit Data Delay time Receive Data Setup time Receive Data Hold time
MONCLK
MONTX MONRX
Figure Data Interface Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Test Interface
Units
TIMING CHARACTERISTICS
Parameter
JTAG Port Period
Width
Width High*
Note: These parameters have been functionally verified, tested.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
EVBC Interface ASPORT
Units
TIMING CHARACTERISTICS
Parameter Comment (see Figure ASCLK period ASOFS setup time before ASCLK high ASOFS hold time after ASCLK high ASDI setup time before clock ASDI hold time after clock ASDO delay after clock high
ASCLK ASOFS ASDI ASDO
Figure EVBC Interface ASPORT Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
EVBC Interface BSPORT
76.9 Units
TIMING CHARACTERISTICS
Parameter Comment (see Figure BSCLK period BSIFS setup time before BSCLK BSIFS hold time after BSCLK BSDI setup time before BSCLK BSDI hold time after BSCLK BSOFS delay after BSCLK high BSDO delay after BSCLK high
BSCLK BSIFS BSDI BSOFS BSDO
Figure EVBC Interface BSPORT Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
EVBC Interface VSPORT
76.9 Units
TIMING CHARACTERISTICS
Parameter Comment (see Figure VSCLK period VSFS setup time before VSCLK VSFS hold time after VSCLK VSDI setup time before VSCLK VSDI hold time after VSCLK VSDO delay after VSCLK high
VSCLK VSFS VSDI VSDO
Figure EVBC Interface VSPORT Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Parallel Display Interface
Units
TIMING CHARACTERISTICS
Parameter t100 t101 t102 Comments (see Figure Control width CLKIN cycles) Control high width CLKIN cycles) Control high width read extension CLKIN cycle)
19:O
DISPLAYCS
t100
LCDCTL
t101
t102
Figure Parallel Display Interface Timing
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
AD6426
Serial Display Interface
t1*8 t1*16 0.25 *t103+ 0.25 *t103 0.25 *t103- Units
TIMING CHARACTERISTICS
Parameter t103 t104 t105 t106 t107 Comment (see Figure DISP_CLK Period DISP_CS Data Valid DISP_CLK Data Valid DISP_CLK DISP_CS high Data Valid DISP_CLK High
t103
DISP_CLK DISP_D0
t104 t107
t105
t106
DISP_CS
DISP_A0
Figure Serial Display Interface
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
PACKAGING LQFP Locations
Name USCRI (MONCLK) USCRX (MONRX) USCTX (MONTX) USCCTS (ADD20) USCRTS (GPIO9) GPO10 (GPIO8) ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 BOOTCODE (GND) ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 RAMCS ROMCS DATA15 DATA14 DATA13 Name DATA12 DATA11 DATA10 DATA9 DATA8 (HWR) (LWR) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FLASHPWD (GPIO2) GPIO1 GPIO0 SIMSUPPLY SIMPROG SIMRESET SIMDATAIP SIMDATAOP SIMCLK SIMCARD Name JTAGEN EEPROMEN EEPROMCLK EEPROMDATA VSDO VSFS VSDI VSCLK VBCRESET RXON CLKOUT BSDO BSOFS BSIFS BSDI BSCLK ASCLK ASDI ASOFS ASDO TXPHASE GPIO2 (CPPWD) (GND) (VDD) OSCIN (SAMCS) OSCOUT (CPFS) VDDRTC (CPDO) PWRON (CPDI) SYNTHEN1 SYNTHEN0 SYNTHDATA SYNTHCLK AGCA Name AGCB TXPA
AD6426
CALIBRATERADIO RADIOPWRCTL TXENABLE CLKIN GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 LCDCTL DISPLAYCS BACKLIGHT OSC13MON (GPPWRCTL) GPCS KEYPADCOL3 KEYPADCOL2 KEYPADCOL1 KEYPADCOL0 KEYPADROW5 KEYPADROW4 KEYPADROW3 KEYPADROW2 KEYPADROW1 KEYPADROW0 RESET IRQ6 GPIO8 (BOOTCODE) GPIO9 (H8MODE)
Note: names AD6422 names from AD20msp415 chipset.
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
PBGA Locations
IRQ6 KEYPADROW0 KEYPADROW4 KEYPADCOL1 GPCS CLKIN Name USCR1 Name ADD16 ADD17 USCCTS GPIO8 BACKLIGHT GPIO5 SYNTHCLK PWRON OSCOUT ADD13 ADD12 ADD18 ADD15 ADD19 KEYPADROW3 KEYPADCOL3 LCDCTL SYNTHEN1 TXPHASE ASDO ADD10 ADD14 ADD8 DISPLAYCS BSDO VDDRTC GPIO2 BSCLK ASOFS ASCLK Name BOOTCODE ADD7 ADD9 ADD4 ADD1 ADD11 DATA3 ASDI BSOFS VBCRESET BSDI BSIFS ADD6 ADD3 ADD5 FLASHPWD SIMPROG VSCLK VSDO CLKOUT RXON ADD2 RAMCS ADD0 DATA14 DATA7 DATA2 GPIO1 SIMCLK EEPROMCLK VSFS VSDI
AD6426
Name ROMCS DATA10 DATA9 DATA6 SIMRESET EEPROMEN EEPROMDATA DATA15 DATA13 DATA8 DATA4 DATA0 GPIO0 SIMDATAIP SIMCARD JTAGEN DATA12 DATA11 DATA5 DATA1 SIMSUPPLY SIMDATAOP
TXPA AGCB USCRX GPIO9 RESET KEYPADROW1 KEYPADROW5 KEYPADCOL2 GPIO3 GPIO7
TXENABLE AGCA SYNTHDATA GPIO10 USCRTS USCTX KEYPADROW2 KEYPADCOL0 OSC13MON GPIO4 GPIO6 RADIOPWRCTL
CALIBRATERADIO SYNTHEN0 OSCIN
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
GPIO9 GPIO8 IRQ6 RESET KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 GPCS OSC13MON BACKLIGHT DISPLAYCS LCDCTL GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 CLKIN TXENABLE RADIOPWRCTL CALIBRATERADIO TXPA AGCB
AD6426
USCRI USCRX USCTX USCCTS USCRTS GPIO10 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 BOOTCODE ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 RAMCS ROMCS DATA15 DATA14 DATA13
AGCA SYNTHCLK SYNTHDATA SYNTHEN0 SYNTHEN1 PWRON VDDRTC OSCOUT OSCIN GPIO2 TXPHASE ASDO ASOFS ASDI ASCLK BSCLK BSDI BSIFS BSOFS BSDO CLKOUT RXON VBCRESET VSCLK VSDI VSFS VSDO EEPROMDATA EEPROMCLK EEPROMEN JTAGEN DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FLASHPWD GPIO1 GPIO0 SIMSUPPLY SIMPROG SIMRESET SIMDATAIP SIMDATAOP SIMCLK SIMCARD
AD6426
VIEW (PINS DOWN)
Figure LQFP Locations
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
LQFP Outline Dimensions
AD6426
TQFP
VIEW (PINS DOWN)
MILLIMETERS 0.05 1.35 21.80 19.90 0.17 1.60 0.15 1.45 22.20 20.10 0.75 0.27 0.08
0.002 0.053 0.858 0.783 0.019 0.007
INCHES
0.063 0.006 0.057 0.874 0.791 0.030 0.011 0.003
1.40 22.00 20.00 0.50 0.22
0.055 0.866 0.787 0.024 0.020 0.009
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
Preliminary Technical Information
PBGA Outline Dimensions
AD6426
AD6426
VIEW (Pins Down)
0.10
-Caaa
1.42 0.30 0.75 12.85 9.95 12.85 9.95 0.45 0.27
MILLIMETERS 1.65 0.40 0.90 13.00 11.00 10.75 13.00 11.00 10.75 0.55 0.35 1.00 1.80 0.50 0.97 13.15 11.55 13.15 11.55 0.65 0.43 0.15 0.20 0.25
0.05591 0.01181 0.02953 0.50590 0.39173 0.50591 0.39173 0.17716 0.01063
INCHES 0.06496 0.01575 0.03543 0.51181 0.43307 0.42323 0.51181 0.43307 0.42323 0.02165 0.01378 0.03937
0.07087 0.01968 0.03819 0.51772 0.45472 0.51772 0.45472 0.02559 0.01693 0.00591 0.00787 0.00984
NOTE: Between Spacing Centers
This Information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture unless otherwise agreed writing. responsibility assumed Analog Devices use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Revision Preliminary (June
Confidential Information
AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision
(Changes from Revision 1.0)
Number Date 5/19/98 5/19/98 5/19/98 5/19/98 5/19/98 Description Change Motorola Serial Display mode added. TXENABLE function freeing IRQ6 added. Dimensional tolerances package outline drawing added. Memory timing specs separated into characteristics requirements. Dual band control signals renamed- BANDSELECT0 multiplexed with GPIO[2], BANDSELECT1 multiplexed with GPIO[1]. radios requiring single Bandselect bit, BANDSELECT0 enabled. radios requiring Bandselect bits then both BANSELECT0,1 enabled. These signals were previously referred BANDSELECT DCSSEL. radio diagram Figure updated show generic radio I/F. Pins updated consistent with users manual. GPIO[7:0] functions Mode (Table were incorrectly listed being Tristate outputs. correct function GPIO7 GPIO[6:0] Requirements 32kHz crystal slow clocking added. functions Emulation mode 0,6,7 Table renamed reserve. Memory Interface Timing Specification: read timing specs changed with exception Control Processor data hold Parameters broken separately into requirements characteristics. following pins were incorrectly labeled thus changed; from from from from
5/19/98 5/19/98 5/19/98 5/20/98 5/20/98 5/20/98
6/9/98
June 1998
Page
AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision
(Changes from Revision 0.1)
Number Date 1/15/98 1/15/98 1/15/98 1/15/96 1/15/98 1/15/98 1/15/98 Description Change Dallas added Feature list. Dallas enable polarity changed from logic Dual Band control section added describing BANDSELECT DCSSEL signals. Serial Display Interface Timing Characteristics Diagram added Figure General Description: F7.2 data services deleted, this supported EGSMP. General Description: AD6421/25 interfaces EGSMP. Serial Display Reset signal removed from Figure Display driver chip reset input connected AD6425 Reset Input both driven AD6426 reset output. Functionality: VBCRESET added note, also used Display Reset. Functionality: GPIO1 added note, alternate function DCS_ON. Control Registers: Interrupt counter (Addr. changed from bits. Interface timing characteristics deleted signals completely asynchronous with respect SIMCLK. Plastic Ball Grid Array (PBGA) Package pinout outline drawing added. EVBC radio Interface block diagram Figure updated with dual band control signals. VCLKIN, Clock Input Voltage ac-coupled sine wave input changed from mVPP mVPP. Added scan registers USCRX (O), USCRXEN (B), VSDOEN Corrected output polarity Notes active-low (0=output). Added Control registers register contents Tables Buffered UART Register Contents added Table IIH, Input Current spec -10, added. IIH, Input Current spec -10, added. IOZL, Level Output 3-State Leakage Current IOZH, High Level Output 3-State Leakage Current Absolute ratings broken separately PBGA package. Control Processor Data setup time changed from Radio interface section: reference TTP/Hitachi radios added "AD6426 Radio Interface supports radio architectures based Siemens, Philips, TTP/Hitachi chipsets". Functionality: OSC13MON moved from section general section. Memory interface timing diagram replaced with used 6422 data sheet. register bits SIMCLOCK Polarity, SIMCLOCK off. SIMCLOCK Control, STBYCLKON removed longer used 6426. registers 80-87 slow clocking control removed from Table TTP's request. Peripheral registers 106-109 removed from Table TTP's request. Buffered UART registers removed TTP's request.
1/15/98 1/15/98 1/15/98 1/15/98 1/15/98 2/16/98 2/16/98 2/16/98 2/16/98 2/16/98 2/26/98 2/26/98 2/26/98 2/26/98 2/26/98 2/26/98 2/27/98 2/27/98 2/27/98 3/9/98 3/9/98 3/9/98
June 1998
Page
Other recent searches
UC1526A - UC1526A UC1526A Datasheet
UC2526A - UC2526A UC2526A Datasheet
UC3526A - UC3526A UC3526A Datasheet
SY02-MFTC - SY02-MFTC SY02-MFTC Datasheet
Si1557DH - Si1557DH Si1557DH Datasheet
MSM51V16160F - MSM51V16160F MSM51V16160F Datasheet
LTC6087 - LTC6087 LTC6087 Datasheet
LTC6088 - LTC6088 LTC6088 Datasheet
HS301 - HS301 HS301 Datasheet
DR-38 - DR-38 DR-38 Datasheet
AND180AYP - AND180AYP AND180AYP Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
