CMOS Dual 8-Bit Buffered Multiplying AD7528 GENERAL DESCRIPTION

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CMOS Dual 8-Bit Buffered Multiplying AD7528 GENERAL DESCRIPTION

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FEATURES On-Chip Latches Both DACs Operation DACs Matched Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys Required) APPLICATIONS Digital Control Gain/Attenuation Filter Parameters Stereo Audio Circuits Graphics
CMOS Dual 8-Bit Buffered Multiplying AD7528
GENERAL DESCRIPTION
ORDERING GUIDE1 Model2 AD7528JN AD7528KN AD7528LN AD7528JP AD7528KP AD7528LP AD7528JR AD7528KR AD7528LR AD7528AQ AD7528BQ AD7528CQ AD7528SQ AD7528TQ AD7528UQ AD7528SE AD7528TE AD7528UE Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C Relative Gain Accuracy Error Package Option3 N-20 N-20 N-20 P-20A P-20A P-20A R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20 Q-20 Q-20 E-20A E-20A E-20A
AD7528 monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. available skinny 0.3" wide 20-pin DIPs 20-terminal surface mount packages. Separate on-chip latches provided each allow easy microprocessor interface. Data transferred into either data latches common 8-bit TTL/CMOS compatible input port. Control input A/DAC determines which loaded. AD7528's load cycle similar write cycle random access memory device compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80. device operates from power supply, dissipating only power. Both DACs offer excellent four quadrant multiplication characteristics with separate reference input feedback resistor each DAC.
PRODUCT HIGHLIGHTS
matching: since both AD7528 DACs fabricated same time same chip, precise matching tracking between inherent. AD7528's matched CMOS DACs make whole range applications circuits possible, particularly audio, graphics process control areas. Small package size: combining inputs on-chip latches into common data adding A/DAC select line allowed AD7528 packaged either small 20-pin DIP, SOIC, PLCC LCCC. REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
NOTES Analog Devices reserves right ship side-brazed ceramic lieu cerdip. Parts will marked with cerdip designator "Q." Processing MIL-STD-883C, Class available. order, suffix "/883B" part number. further information, Analog Devices' 1990 Military Products Databook. Leadless Ceramic Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier; Cerdip; SOIC.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7528-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Version1 +25°C 0.007
VREF unless otherwise noted)
+25°C TMIN, TMAX 0.0035 0.0035 Units Bits Test Conditions/Comments
TMIN, TMAX 0.007
This Endpoint Linearity Specification
Differential Nonlinearity Gain Error
Grades Guaranteed Monotonic Over Full Operating Temperature Range Measured Using Internal Both Latches Loaded with 11111111 Gain Error Adjustable Using Circuits Figures
Gain Temperature Coefficient Gain/Temperature Output Leakage Current (Pin (Pin Input Resistance REFA, VREFB) VREF A/VREF Input Resistance Match DIGITAL INPUTS Input High Voltage Input Voltage Input Current Input Capacitance DB0-DB7 A/DAC SWITCHING CHARACTERISTICS Chip Select Write Time Chip Select Write Hold Time Select Write Time Select Write Hold Time Data Valid Write Time Data Valid Write Hold Time Write Pulse Width POWER SUPPLY
%/°C Latches Loaded with 00000000 Input Resistance -300 ppm/°C, Typical Input Resistance
13.5
13.5
Timing Diagram
Figure Digital Inputs Digital Inputs
PERFORMANCE CHARACTERISTICS5
Parameter SUPPLY REJECTION (GAIN/VDD) CURRENT SETTLING TIME Version1 +25°C 0.02 0.04
(Measured Using Recommended P.C. Board Layout (Figure AD644 Output Amplifiers)
Test Conditions/Comments LSB. A/Out load DB0-DB7 VREF VREF Load CEXT DB0-DB7 Code Transition 00000000 11111111 Latches Loaded with 00000000 Latches Loaded with 11111111 0.01 0.02
TMIN, TMAX +25°C TMIN, TMAX Units
PROPAGATION DELAY (From Digital Input Final Analog Output Current)
DIGITAL-TO-ANALOG GLITCH IMPULSE OUTPUT CAPACITANCE COUTA COUTB COUTA COUTB FEEDTHROUGH VREF VREF
VREF VREF Sine Wave
REV.
AD7528
Parameter CHANNEL-TO-CHANNEL ISOLATION VREF VREFB DIGITAL CROSSTALK HARMONIC DISTORTlON Version1 +25°C Test Conditions/Comments Both Latches Loaded with 11111111. VREF Sine Wave VREF Figure VREF Sine Wave VREF Figure Measured Code Transition 00000000 11111111 TMIN, TMAX +25°C TMIN, TMAX Units
NOTES Temperature Ranges Versions: -40°C +85°C Versions: -40°C +85°C Versions: -55°C +125°C Specifications applies both DACs AD7528. Logic inputs Gates. Typical input current (+25°C) less than Guaranteed design production tested. These characteristics design guidance only subject test. Feedthrough further reduced connecting metal ceramic package (suffix DGND. Specifications subject change without notice.
AD7528, ideal maximum output VREF LSB. Gain error both DACs adjustable zero with external resistance.
Output Capacitance:
Capacitance from AGND.
Digital Analog Glitch lmpulse:
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
AGND DGND AGND DGND DGND AGND Digital Input Voltage DGND -0.3 VPIN2, VPIN20 AGND -0.3 VREF VREF AGND VRFB VRFB AGND Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C Operating Temperature Range Commercial Grades -40°C +85°C Industrial Grades -40°C +85°C Extended Grades -55°C +125°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, secs) +300°C
CAUTION:
amount charge injected from digital inputs analog output when inputs change state. This normally specified area glitch either pA-secs nV-secs depending upon whether glitch measured current voltage signal. Glitch impulse measured with VREF VREF AGND.
Propagation Delay:
This measure internal delays circuit defined time from digital input change analog output current reaching final value.
Channel-to-Channel Isolation:
proportion input signal from DAC's reference input which appears output other DAC, expressed ratio
Digital Crosstalk:
glitch energy transferred output converter change digital input code other converter. Specified secs.
CONFIGURATIONS PLCC
sensitive device. digital control inputs diode protected; however, permanent damage occur unconnected devices subjected high energy electrostatic fields. Unused devices must stored conductive foam shunts. insert this device into powered sockets. Remove power before insertion removal.
TERMINOLOGY Relative Accuracy: DIP, SOIC
Relative accuracy endpoint nonlinearity measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero full scale normally expressed LSBs percentage full scale reading.
Differential Nonlinearity:
LCCC
Differential nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity over operating temperature range ensures monotonicity.
Gain Error:
Gain error full-scale error measure output error between ideal actual device output. REV.
AD7528
INTERFACE LOGIC INFORMATION Selection:
Both latches share common 8-bit input port. control input A/DAC selects which accept data from input port.
Mode Selection:
Figure inverted R-2R ladder structure used, that binary weighted currents switched between output AGND thus maintaining fixed currents each ladder independent switch state.
EQUIVALENT CIRCUIT ANALYSIS
Inputs control operating mode selected DAC. Mode Selection Table below.
Write Mode:
When both selected write mode. input data latches selected transparent analog output responds activity DB0-DB7.
Hold Mode:
Figure shows approximate equivalent circuit AD7528's converters, this case similar equivalent circuit drawn Note that AGND (Pin common both current source ILEAKAGE composed surface junction leakages and, with most semiconductor devices, approximately doubles every 10°C. resistor shown Figure equivalent output resistance device which varies with input code (excluding code) from typically COUT capacitance N-channel switches varies from about depending upon digital input. g(VREF Thevenin equivalent voltage generator reference input voltage VREF transfer function R-2R ladder.
selected latch retains data which present DB0-DB7 just prior assuming high state. Both analog outputs remain values corresponding data their respective latches.
Mode Selection Table
A/DAC WRITE HOLD HOLD HOLD HOLD WRITE HOLD HOLD
State; High State; Don't Care.
WRITE CYCLE TIMING DIAGRAM
Figure Equivalent Analog Output Circuit
CIRCUIT INFORMATION-DIGITAL SECTION
input buffers simple CMOS inverters designed such that when AD7528 operated with buffer converts input levels (2.4 into CMOS logic levels. When region volts volts input buffers operate their linear region pass quiescent current, Figure minimize power supply currents recommended that digital input voltages close supply rails (VDD DGND) practically possible. AD7528 operated with supply voltage range volts. With input logic levels CMOS compatible only, i.e., 13.5
CIRCUIT INFORMATION-D/A SECTION
AD7528 contains identical 8-bit multiplying converters, Each consists highly stable thin film R-2R ladder eight N-channel current steering switches. simplified circuit shown
Figure Typical Plots Supply Current, Logic Input Voltage VIN, Figure Simplified Functional Circuit
REV.
AD7528
Table Unipolar Binary Code Table
Latch Contents 11111111 10000001 10000000 01111111 00000001 00000000
Note:
Analog Output (DAC
Figure Dual Unipolar Binary Operation Quadrant Multiplication); Table
Table Bipolar (Offset Binary) Code Table
Latch Contents 11111111 10000001 10000000 01111111 00000001 00000000
Note:
Analog Output (DAC
Figure Dual Bipolar Operation Quadrant Multiplication); Table
Table III. Recommended Trim Resistor Values Grade
Trim Resistor
J/A/S
K/B/T
L/C/U
REV.
AD7528
APPLICATIONS INFORMATION Application Hints SINGLE SUPPLY APPLICATIONS
ensure system performance consistent with AD7528 specifications, careful attention must given following points: GENERAL GROUND MANAGEMENT: transient voltages between AD7528 AGND DGND cause noise injection into analog output. simplest method ensuring that voltages AGND DGND equal AGND DGND together AD7528. more complex systems where AGND-DGND intertie backplane, recommended that diodes connected inverse parallel between AD7528 AGND DGND pins (1N914 equivalent). OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit code-dependent output resistance which turn causes code-dependent amplifier noise gain. effect codedependent differential nonlinearity term amplifier output which depends (VOS amplifier input offset voltage). This differential nonlinearity term adds R/2R differential nonlinearity. maintain monotonic operation, recommended that amplifier greater than over temperature range interest. HIGH FREQUENCY CONSIDERATIONS: output capacitance CMOS works conjunction with amplifier feedback resistance pole open loop response. This cause ringing oscillation. Stability restored adding phase compensation capacitor parallel with feedback resistor.
DYNAMIC PERFORMANCE
AD7528 R-2R ladder termination resistors connected AGND within device. This arrangement particularly convenient single supply operation because AGND biased voltage between DGND VDD. Figure shows circuit which provides analog outputs biasing AGND from DGND. reference inputs tied together reference input voltage obtained without buffer amplifier making constant matched impedances reference inputs. Current flows through R-2R ladders into adjusted until VREF VREF inputs analog output voltages range from codes 00000000 11111111.
dynamic performance DACs AD7528 will depend upon gain phase characteristics output amplifiers together with optimum choice board layout decoupling components. Figure shows relationship between input frequency channel channel isolation. Figure shows printed circuit layout AD7528 AD644 dual op-amp which minimizes feedthrough crosstalk.
Figure AD7528 Single Supply Operation
Figure shows AD7528 connected positive reference, voltage switching mode. This configuration useful that VOUT same polarity allowing single supply operation. However, retain specified linearity, must range +2.5 output buffered loaded with high impedance, Figure Note that input voltage connected output voltage taken from VREF pin.
Figure Channel Channel Isolation
Figure AD7528 Single Supply, Voltage Switching Mode
Figure Suggested Board Layout AD7528 with AD644 Dual
Figure Typical AD7528 Performance Single Supply Voltage Switching Mode (K/B/T, L/C/U Grades)
REV.
AD7528
MICROPROCESSOR INTERFACE
Figure AD7528 Dual 6800 Interface
PROGRAMMABLE WINDOW COMPARATOR
Figure AD7528 Dual 8085 Interface
circuit Figure AD7528 used implement programmable window comparator. DACs loaded with required upper lower voltage limits test, respectively. test input within programmed limits, pass/fail output will indicate fail (logic zero).
Figure Digitally Programmable Window Comparator (Upper Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER CIRCUIT EQUATIONS
RFBB1
Note: equivalent resistance equals
Figure Digitally Controlled State Variable Filter
(DAC Ladder resis tance Digital Code
this state variable universal filter configuration (Figure DACs control gain filter characteristic while DACs control cutoff frequency, DACs must track accurately simple expression hold. This readily accomplished AD7528. amps AD644. compensates effects gain bandwidth limitations. REV.
filter provides pass, high pass band pass outputs ideally suited applications where microprocessor control filter parameters required, e.g., equalizer, tone controls, etc. Programmable range component values shown 4.5.
AD7528
DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR Table Attenuation Code Circuit this configuration AD7528 functions 2-channel digiof Figure tally controlled attenuator. Ideal stereo audio telephone
signal level control applications. Table gives input codes attenuation 15.5 range. Input Code
Attenuation
Attn. Input Code 11111111 11110010 11100100 11010111 11001011 11000000 10110101 10101011 10100010 10011000 10010000 10001000 10000000 01111001 01110010 01101100
Code Decimal
Attn. Input Code 88.0 88.5 89.0 89.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 01100110 01100000 01011011 01010110 01010001 01001100 01001000 01000100 01000000 00111101 00111001 00110110 00110011 00110000 00101110 00101011
Code Decimal
C681d-10-6/86 PRINTED U.S.A.
further applications information reader referred Analog Devices Application Note AD7528.
Figure Digitally Controlled Dual Telephone Attenuator
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Pin Cerdip (Q-20)
20-Pin Plastic (N-20)
20-Terminal Plastic Leaded Chip Carrier (P-20A)
20-Pin SOIC (R-20)
20-Terminal Leadless Ceramic Chip Carrier (E-20A)
REV.

CMOS Dual 8-Bit Buffered Multiplying AD7528 GENERAL DESCRIPTION

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