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A62S8316 Series

Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History

A62S8316 Series
Preliminary
Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History
Rev. No.
256K X 16 BIT LOW VOLTAGE CMOS SRAM
History
Initial issue
Issue Date
February 12, 2001
Remark
Preliminary
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Preliminary
Features
n Operating voltage: 2.7V to 3.6V n Access times: 70 ns (max.) n Current: A62S8316-S series: Operating: Standby: A62S8316-SI series: Operating: Standby: n Extended operating temperature range : -25°C to 85°C for -SI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I / O using three-state output n Data retention voltage: 2V (min.) n Available in 44-pin TSOP and 48-ball Mini BGA (6X8) packages.
256K X 16 BIT LOW VOLTAGE CMOS SRAM
50mA (max.) 10µA (max.) 50mA (max.) 15µA (max.)
General Description
Pin Configuration
n TSOP (Type II)
PRELIMINARY
A62S8316V
A62S8316G
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Block Diagram
VCC GND 2048X 2048 DECODER
MEMORY ARRAY
I / O0 COLUMN I / O INPUT DATA CIRCUIT
INPUT DATA CIRCUIT
CONTROL CIRCUIT
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Pin Description - TSOP
Pin No. 1 - 5, 18 - 27, 42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 41 11, 33 12, 34 28 Symbol A0 - A17 CE I / O0 - I / O15 WE LB HB OE VCC GND NC Description Address Inputs Chip Enable Input
Data Input / Outputs Write Enable Input Byte Enable Input (I / O0 to I / O7) Byte Enable Input (I / O8 to I / O15) Output Enable Input Power Ground No Connection
Recommended DC Operating Conditions
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Absolute Maximum Ratings
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN / OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -25°C to +85°C Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Output Leakage Current
ICC ICC1
Active Power Supply Current
Dynamic Operating Current ICC2
ISB ISB1 VOL VOH Standby Power Supply Current Output Low Voltage Output High Voltage
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Truth Table
CE H OE X WE X LB X L L L H L H L L X L L H L L H H X X X X H L H High - Z Not selected High - Z Not selected ICC1, ICC2, ICC ISB1, ISB HB X L H L L H L X I / O0 to I / O7 Mode Not selected Read Read High - Z Write Write Not Write / Hi - Z High - Z I / O8 to I / O15 Mode Not selected Read High - Z Read Write Not Write / Hi - Z Write High - Z VCC Current ISB1, ISB ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Symbol Parameter A62S8316-70S / SI Min. Read Cycle tRC tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH Write Cycle tWC tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 70 60 60 0 60 50 0 30 0 5 30 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 70 10 5 5 10 70 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns Max. Unit
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Timing Waveforms
Read Cycle 1
tRC Address
tAA tOH tOH
Read Cycle 2
tRC Address
CE tACE tCLZ 5 tBE
tCHZ 5
HB, LB
tBLZ 5
tBHZ 5
OE tOHZ 5
tOE tOLZ 5 DOUT
Notes:
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Timing Waveforms (continued)
Write Cycle 1 (Write Enable Controlled)
tWC Address tAW tCW CE tWR3
tBW HB, LB
tDW DATA IN tWHZ 4
tOW DATA OUT
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Timing Waveforms (continued)
Write Cycle 2 (Chip Enable Controlled)
tWC Address tAW tAS1 CE tCW2 tWR3
tBW HB, LB
tDW DATA IN tWHZ 4
tOW DATA OUT
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Timing Waveforms (continued)
Write Cycle 3 (Byte Enable Controlled)
tWC Address
tAW tCW CE tWR3
HB, LB
tWP WE
DATA IN tWHZ 4 tOW DATA OUT
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
AC Test Conditions
Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 5 ns 1.5V See Figures 1 and 2
CL 30pF
CL 5pF
Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
S-Version ICCDR Data Retention Current SI-Version tCDR tR Chip Disable to Data Retention Time Operation Recovery Time ICCDR: max. ICCDR: max.
See Retention Waveform
A62S8316-70S A62S8316-70SI
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Low VCC Data Retention Waveform
DATA RETENTION MODE VCC 2.7V tCDR VDR 2V 2.7V tR
VIH CE VDR - 0.2V
Ordering Information
Part No. A62S8316V-70S A62S8316V-70SI 70 A62S8316G-70S A62S8316G-70SI 50 50 10 15 48B Mini BGA 48B Mini BGA Access Time (ns) Operating Current Max. (mA) 50 50 Standby Current Max. (µA) µ 10 15 Package 44L TSOP 44L TSOP
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Package Information TSOP 44L (Type II) Outline Dimensions
unit: inches / mm
Dimensions in inches
Dimensions in mm Min 0.05 0.95 0.30 0.12 18.28 11.56 10.03 0.49 Nom 1.00 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC Max 1.20 0.15 1.05 0.45 0.21 18.54 11.96 10.29 0.69
Symbol
Min 0.002 0.037 0.012 0.005 0.720 0.455 0.395 0.019
Nom 0.039 0.725 0.032 REF 0.463 0.400 0.023 0.031 REF 0.031 BSC
Max 0.047 0.006 0.041 0.018 0.008 0.730 0.471 0.405 0.027
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension ZD includes end flash.
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
A62S8316 Series
Package Information Mini BGA 6X8 (48 BALLS) Outline Dimensions
unit : millimeter(mm)
Bottom View Pin A1 Index 6 5 4 3 2 1 Pin A1 Index
Top View
A B1 Diameter D Solder Ball
Min 5.90 7.90 0.30 1.00 -
Typ 0.75 6.00 3.75 8.00 5.25 0.35 1.10 0.36 0.22
Max 6.10 8.10 0.40 1.20 -
PRELIMINARY
(February, 2001, Version 0.0)
AMIC Technology, Inc.
0.10 E1