BLOCK DIAGRAMEMORY ARRAY ADDRESS DECODER 2.5V Microwire® Serial E

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BLOCK DIAGRAMEMORY ARRAY ADDRESS DECODER 2.5V Microwire® Serial E

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93LC46A/B
BLOCK DIAGRAMEMORY ARRAY ADDRESS DECODER
2.5V Microwire® Serial EEPRO
Single supply with operation down 2.5V power CMOS technology active current (typical) standby current (maximum) organization (93LC46A) organization (93LC46B) Self-timed ERASE WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial interface Device status signal during ERASE/WRITE cycles Sequential READ function 1,000,000 cycles guaranteed Data retention years 8-pin PDIP/SOIC 8-pin TSSOP packages Available following temperature ranges: Commercial (C): +70°C Industrial (I): -40°C +85°C
ADDRESS COUNTER DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR OUTPUT BUFFER
DESCRIPTION
Microchip Technology Inc. 93LC46AX/BX 1Kbit, voltage serial Electrically Erasable PROMs. device memory configured (93LC46A) bits (93LC46B). Advanced CMOS technology makes these devices ideal power nonvolatile memory applications. 93LC46AX/BX available standard 8-pin DIP, 8-pin surface mount SOIC, TSSOP packages. 93LC46AX/BX offered only 150-mil SOIC package.
PACKAGE TYPE
SOIC SOIC TSSOP 93LC46A/B
93LC46AX/BX
93LC46A/B
93LC46A/B
Microwire registered trademark National Semiconductor Incorporated.
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
93LC46A/B
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE
Name
FUNCTION TABLE
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Connect Power Supply
.7.0V inputs outputs w.r.t. -0.6V +1.0V Storage temperature .-65°C +150°C Ambient temp. with power applied.-65°C +125°C Soldering temperature leads seconds) +300°C protection pins.4
*Notice: Stresses above those listed under "Maximum ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operational listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
TABLE
ELECTRICAL CHARACTERISTICS
Commercial (C): Industrial (I): Symbol VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 CIN, COUT write +2.5V +6.0V +2.5V +6.0V Min. -0.3 -0.3 VCC-0.2 Max. Tamb +70°C Tamb -40°C +85°C Units cycles Relative Relative (Note ERASE/WRITE mode ERAL mode WRAL mode 25°C, 5.0V, Block Mode (Note Relative Relative FCLK MHz; 6.0V FCLK MHz; 3.0V 4.5V 4.5V Conditions 2.7V 5.5V (Note 2.7V 2.7V (Note 2.7V 4.5V =100 Min. -400 4.5V -100 Min. VOUT VIN/VOUT (Notes Tamb +25°C, FCLK
parameters apply over specified operating ranges unless otherwise noted Parameter High level input voltage
level input voltage
level output voltage
High level output voltage Input leakage current Output leakage current capacitance (all inputs/outputs) Operating current Standby current Clock frequency Clock high time Clock time Chip select setup time Chip select hold time Chip select time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time
read ICCS FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH
Program cycle time
Endurance
Note This parameter tested Tamb 25°C Fclk MHz. This parameter periodically sampled 100% tested. This application tested guaranteed characterization. endurance estimates specific application, please consult Total Endurance Model which obtained Microchip's website.
DS21173D-page
Preliminary
1997 Microchip Technology Inc.
93LC46A/B
DESCRIPTION
Chip Select (CS)
cycles required during self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection START condition specified number clock cycles (respectively high transitions CLK) must provided. These clock cycles required clock required opcode, address, data bits before instruction executed (Table Table 2-2). then become don't care inputs waiting START condition detected.
high level selects device; level deselects device forces into standby mode. However, programming cycle which already progress will completed, regardless Chip Select (CS) input signal. brought during program cycle, device will into standby mode soon programming cycle completed. must minimum (TCSL) between consecutive instructions. low, internal control logic held RESET status.
Data (DI)
Data (DI) used clock START bit, opcode, address, data synchronously with input.
Serial Clock (CLK)
Data (DO)
Serial Clock used synchronize communication between master device 93LC46AX/ Opcodes, address, data bits clocked positive edge CLK. Data bits also clocked positive edge CLK. stopped anywhere transmission sequence high level) continued anytime with respect clock high time (TCKH) clock time (TCKL). This gives controlling master freedom preparing opcode, address, data. "Don't Care" (device deselected). high, START condition been detected, number clock cycles received device without changing status (i.e., waiting START condition).
Data (DO) used READ mode output data synchronously with input (TPD after positive edge CLK). This also provides READY/BUSY status information during ERASE WRITE cycles. READY/BUSY status information available brought high after being minimum chip select time (TCSL) ERASE WRITE operation been initiated. status signal available held during entire ERASE WRITE cycle. this case, HIGH-Z mode. status checked after ERASE/WRITE cycle, data line will high indicate device ready.
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC46A
Opcode
Address
Data
Data
(RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY)
Req. Cycles
TABLE
Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL
INSTRUCTION 93LC46B
Opcode
Address
Data
Data
(RDY/BSY) (RDY/BSY) HIGH-Z HIGH-Z (RDY/BSY) (RDY/BSY)
Req. Cycles
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
93LC46A/B
FUNCTIONAL DESCRIPTION
Data (DI) Data (DO)
Instructions, addresses, write data clocked into rising edge clock (CLK). normally held HIGH-Z state except when reading data from device, when checking READY/BUSY status during programming operation. READY/BUSY status verified during ERASE/WRITE operation polling pin; indicates that programming still progress, while high indicates device ready. will enter HIGH-Z state falling edge possible connect Data (DI) Data (DO) pins together. However, with this configuration, logic-high level, possible "bus conflict" occur during "dummy zero" that precedes READ operation. Under such condition voltage level seen undefined will depend upon relative impedances signal source driving higher current sourcing capability higher voltage pin.
START Condition
Data Protection
START detected device both high with respect positive edge first time. Before START condition detected, CLK, change combination (except that START condition), without resulting device operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, WRAL). soon high, device longer standby mode. instruction following START condition will only executed required amount opcodes, addresses, data bits particular instruction clocked After execution instruction (i.e., clock last required address data bit) become don't care bits until START condition detected.
During power-up, programming modes operation inhibited until reached level greater than 2.2V. During power-down, source data protection circuitry acts inhibit programming modes when fallen below 2.2V nominal conditions. ERASE/WRITE Disable (EWDS) ERASE/ WRITE Enable (EWDS) commands give additional protection against accidentally programming during normal operation. After power-up, device automatically EWDS mode. Therefore, EWEN instruction must performed before ERASE WRITE instruction executed.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
TCSS TCKH TCKL TCSH
TDIS (READ) (PROGRAM) Note: Test Conditions: 0.4V, 2.4V TDIH
STATUS VALID
DS21173D-page
Preliminary
1997 Microchip Technology Inc.
93LC46A/B
ERASE Erase (ERAL)
ERASE instruction forces data bits specified address logical state. brought following loading last address bit. This falling edge initiates self-timed programming cycle. indicates READY/BUSY status device brought high after minimum (TCSL). logical indicates that programming still progress. logical indicates that register specified address been erased device ready another instruction. Erase (ERAL) instruction will erase entire memory array logical state. ERAL cycle identical ERASE cycle, except different opcode. ERAL cycle completely self-timed commences falling edge Clocking necessary after device entered ERAL cycle. indicates READY/BUSY status device, brought high after minimum (TCSL) before entire ERAL cycle complete.
FIGURE 3-2:
ERASE TIMING
TCSL CHECK STATUS
AN-1
AN-2
READY HIGH-Z
HIGH-Z
BUSY
FIGURE 3-3:
ERAL TIMING
TCSL CHECK STATUS
READY HIGH-Z
HIGH-Z
BUSY
Guaranteed 4.5V +6.0V.
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
93LC46A/B
ERASE/WRITE Disable Enable (EWDS/EWEN) READ
READ instruction outputs serial data addressed memory location pin. dummy zero precedes 8-bit (93LC46A) 16-bit (93LC46B) output string. output data bits will toggle rising edge stable after specified time delay (TPD). Sequential read possible when held high. memory data will automatically cycle next register output sequentially.
93LC46A/B powers ERASE/WRITE Disable (EWDS) state. programming modes must preceded ERASE/WRITE Enable (EWEN) instruction. Once EWEN instruction executed, programming remains enabled until EWDS instruction executed removed from device. protect against accidental data disturbance, EWDS instruction used disable ERASE/WRITE functions should follow programming operations. Execution READ instruction independent both EWEN EWDS instructions.
FIGURE 3-4:
EWDS TIMING
TCSL
FIGURE 3-5:
EWEN TIMING
TCSL
FIGURE 3-6:
READ TIMING
HIGH-Z
DS21173D-page
Preliminary
1997 Microchip Technology Inc.
93LC46A/B
WRITE Write (WRAL)
WRITE instruction followed bits (93LC46A) bits (93LC46B) data which written into specified address. After last data pin, falling edge initiates self-timed autoerase programming cycle. indicates READY/BUSY status device, brought high after minimum (TCSL) before entire write cycle complete. logical indicates that programming still progress. logical indicates that register specified address been written with data specified device ready another instruction. Write (WRAL) instruction will write entire memory array with data specified command. WRAL cycle completely self-timed commences falling edge Clocking necessary after device entered WRAL cycle. WRAL command does include automatic ERAL cycle device. Therefore, WRAL instruction does require ERAL instruction chip must EWEN status. indicates READY/BUSY status device brought high after minimum (TCSL).
FIGURE 3-7:
WRITE TIMING
TCSL
READY
HIGH-Z
BUSY
HIGH-Z
FIGURE 3-8:
WRAL TIMING
TCSL
HIGH-Z
BUSY
READY HIGH-Z
Guaranteed 4.5V +6.0V.
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
93LC46A/B
NOTES:
DS21173D-page
Preliminary
1997 Microchip Technology Inc.
93LC46A/B
NOTES:
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
93LC46A/B
NOTES:
DS21173D-page
Preliminary
1997 Microchip Technology Inc.
93LC46A/B
93LC46A/B PRODUCT IDENTIFICATION SYSTETo order obtain information, e.g., pricing delivery, refer factory listed sales office. 93LC46A/B Package: Plastic (300 Body), 8-lead Plastic SOIC (150 Body), 8-lead Plastic SOIC (208 Body), 8-lead TSSOP, 8-lead
Temperature Range:
Blank +70°C -40°C +85°C 93LC46A 93LC46AT 93LC46AX 93LC46AXT Microwire Serial EEPROM (x8) Microwire Serial EEPROM (x8) Tape Reel Microwire Serial EEPROM (x8) alternate pinout only) Microwire Serial EEPROM (x8) alternate pinout, Tape Reel only) Microwire Serial EEPROM (x16) Microwire Serial EEPROM (x16) Tape Reel Microwire Serial EEPROM (x16) alternate pinout only) Microwire Serial EEPROM (x16) alternate pinout, Tape Reel only)
Device:
93LC46B 93LC46BT 93LC46BX 93LC46BXT
Sales Support
Data Sheets Products supported preliminary Data Sheet have errata sheet describing minor operational differences recommended workarounds. determine errata sheet exists particular device, please contact following: Your local Microchip sales office. Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. Microchip's Bulletin Board, your local CompuServe number (CompuServe membership required).
1997 Microchip Technology Inc.
Preliminary
DS21173D-page
WORLDWIDE SALES SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 786-7627 Web: http://www.microchip.com
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific 3801B, Tower Metroplaza Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. Unit Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire Tel: 44-1628-851077 Fax: 44-1628-850259
France
Arizona Microchip Technology SARL Zone Industrielle Bonde Buisson Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
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Microchip Technology Inc. Sugar Mill Road, Suite 200B Atlanta, 30350 Tel: 770-640-0034 Fax: 770-640-0307
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Microchip Technology India Legacy, Convent Road Bangalore 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
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Microchip Technology Inc. 14651 Dallas Parkway, Suite Dallas, 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
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Microchip Technology Taiwan Singapore Branch Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
JAPAN
Microchip Technology Intl. Inc. Benex 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 5/8/97
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Microchip Technology Inc. Prestige Place, Suite Miamisburg, 45342 Tel: 937-291-1654 Fax: 937-291-9175
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Microchip Technology Inc. 18201 Karman, Suite 1090 Irvine, 92612 Tel: 714-263-1888 Fax: 714-263-1338
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Microchip Technology Inc. 2107 North First Street, Suite Jose, 95131 Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite Mississauga, Ontario 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
rights reserved. 1997, Microchip Technology Incorporated, USA. 6/97 Printed recycled paper.
Preliminary
Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
DS21173D-page
1997 Microchip Technology Inc.

BLOCK DIAGRAMEMORY ARRAY ADDRESS DECODER 2.5V Microwire® Serial E

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