Todsen This application bulletin discusses issues that arise when

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USING EXTERNAL INTEGRATION CAPACITORS DDC112
Todsen
This application bulletin discusses issues that arise when using external integration capacitors DDC112. expands explanation given data sheet provides some data help select capacitors. does assume basic understanding DDC112's operation. good introduction DDC112, please DDC112's data sheet. Digital input pins RANGE0, RANGE1 RANGE2 DDC112 full-scale range. Table lists corresponding range each combination. Ranges through provide full-scale ranges starting 50pC increasing
FULL-SCALE RANGE 0.96 CEXT VREF 50pC 100pC 150pC 200pC 250pC 300pC 350pC
steps 50pC. These ranges capacitors internal DDC112. applications requiring other ranges, Range0 allows user choose full-scale range disabling internal capacitors using external ones. Figure shows simplified block diagram front-end integrators using external integration capacitors. integration capacitors connect operational amplifiers pins 23-26. Notice pins internally connect directly inputs These pins extremely sensitive must treated very carefully. Table summarizes connections. When external capacitors being used, leave pins 23-26 disconnected. DDC112 ties them internally analog ground.
AMP'S NEGATIVE INPUT (VERY SENSITIVE)
RANGE2
RANGE1
RANGE0
SIDE
AMP'S OUTPUT
Table Full-Scale Range Selection.
Input
Table External Capacitor Connections.
Voltage-Input
DDC112
Input
FIGURE Simplified Block Diagram Front-End Integrators Using External Integration Capacitors.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
1998 Burr-Brown Corporation
AB-138
Printed U.S.A. September, 1998
DDC112 operates same with internal external integration capacitors. First, integration capacitor precharges VREF. integration begins, input signal removes charge from capacitor, driving voltage amp's output lower. integration, input signal switches other side, while voltage-input measures held value against VREF. This cycle continues (see data sheet more information) effectively allowing continuous integration input signal. following sections help selecting external capacitor, show performance data discuss layout issues. SELECTING CAPACITOR VALUE value integration capacitor VREF fullscale range. shown Table full-scale range when using external integration capacitors 0.96 VREF CEXT average current reach full-scale then: 0.96VREF TINT TINT
Charge builds input dumped side when integration switches sides. This charge produces error which corrupts side readings even though input signal below side full-scale range. input signal must kept below smaller full-scale range side valid side data. There similar restriction between inputs different value capacitors inputs used. specified maximum integration capacitor 250pF. VREF 4.096V, this corresponds roughly full-scale range 1000pC. This conservative specification. many applications, much larger capacitors used. Experiments have shown good results room temperature even with capacitors exceeding (7800pC) 10MHz. Slowing down allows even larger value capacitors used there will more time integration capacitor precharge VREF. DDC112 designed handle maximum input current 750µA. careful exceed this limit when using large external capacitors. DDC112 will work with very high input currents, running this places stress internal metal lines which cause premature device failure. SELECTING CAPACITOR DIELECTRIC quality external integration capacitor strongly affects performance. Some more critical parameters include: voltage coefficient, temperature coefficient dielectric absorption. voltage coefficient capacitor introduces nonlinearities which degrade INL. temperature coefficient produces gain error drift over temperature. Dielectric absorption degrade performance higher frequency input signals also affect linearity. Suitable dielectrics capacitors include high-quality multilayer ceramics, mica, polystyrene. capacitors should physically small allow them placed close possible pins DDC112. general, have found ceramic NPO) capacitors surfacemount packages good choice. They small, inexpensive, stable available wide range values. sure avoid ceramics. These capacitors often have very poor linearity performance. PERFORMANCE Noise main contributors noise DDC112 front-end integrators voltage-input ADC. internal ranges, particularly lower ones, noise integrators dominates. noise inversely proportional integration capacitor proportional sensor capacitance, CSENSOR. Since external capacitors typically much larger value than internal capacitors, when they used integrator usually contributes less noise. This
external capacitors allow select full-scale range desire. external range should larger than what available internally. While small external capacitors used, ranges less than 350pC it's best internal capacitors. These capacitors tend more linear integrator slightly better noise performance using internal ranges. Plus, using internal capacitors saves components printed circuit board (PCB) floor space. general, same value capacitor should used sides input. Doing helps match offset gain between sides. some reason want different value capacitors sides, will limited full-scale range smaller capacitor. Here's why: input signals exceeding full-scale range integrator rail output ground. longer provides virtual ground input additional input current forces input node rise above ground until diode input (not shown Figure turns voltage across input creates charge buildup. When integration switches other side, charge then dumped onto that side's integration capacitor causing error. This error usually large enough make data from larger capacitor's side unusable. example, assume sides 100pF 200pF capacitors, respectively, VREF 4.096V total charge supplied input signal during integration time 500pC. This signal exceeds side full-scale range (393pC) side (786pC). During integration side that side's rails causing input rise above ground.
turn reduces sensitivity noise CSENSOR. Figure illustrates typical noise (with low-level input signal) versus CSENSOR different values external capacitor, CEXT. Notice slope noise CSENSOR plot decreases larger external capacitors result decreased sensitivity front-end integrators.
versus DDC112 output reading with ceramic capacitors. endpoint used calculate INL. external capacitors were approximately 270pF integration time 500µs. comparison, largest internal capacitor (Range also plotted. LAYOUT layout external capacitors traces printed circuit board critical. Using small surface-mount packages like "0805" capacitors allows compact layouts without need vias PCB. Figure shows enlarged layout with only external capacitors included simplicity. discussed earlier, pins connect internally inputs should kept short possible reduce pickup leakage. Consider using top-side metal ground plane make sure ground plane surrounds capacitors traces provide shielding. different layer used ground plane, then unused metal near external capacitors ground form shield. remember, external capacitors being used, leave pins 23-26 floating.
CEXT 100pF
Noise (rms, ppm)
CEXT 150pF
CEXT 220pF CEXT 270pF
1000
CSENSOR (pF)
FIGURE Noise CSENSOR Different Values CEXT. Linearity front-end integrators linearity performance DDC112 integrators voltage coefficient integration capacitor ultimately limits linearity. input signal increases, voltage across integration capacitors increases. This turn changes value integration capacitor capacitor's non-zero voltage coefficient causes transfer function deviate from ideal linear integrator. Fortunately, internal capacitors DDC112 have voltage coefficient provide good performance. keep same level performance with external capacitors, it's important choose capacitors with voltage coefficients. Figure shows plot integral non-linearity (INL)
DDC112
FIGURE Layout Example Using External Integration Capacitors.
(ppm)
Range
Output Reading Full Scale) CEXT 270pF
FIGURE Output Reading Using External Integration Capacitor.

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